ES510691A0 - Circuito operativo para actuar en palabras de datos digitales. - Google Patents

Circuito operativo para actuar en palabras de datos digitales.

Info

Publication number
ES510691A0
ES510691A0 ES510691A ES510691A ES510691A0 ES 510691 A0 ES510691 A0 ES 510691A0 ES 510691 A ES510691 A ES 510691A ES 510691 A ES510691 A ES 510691A ES 510691 A0 ES510691 A0 ES 510691A0
Authority
ES
Spain
Prior art keywords
sup
data words
digital data
act
operational circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES510691A
Other languages
English (en)
Other versions
ES8307393A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of ES510691A0 publication Critical patent/ES510691A0/es
Publication of ES8307393A1 publication Critical patent/ES8307393A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724—Finite field arithmetic
    • G06F7/726—Inversion; Reciprocal calculation; Division of elements of a finite field
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1809—Pulse code modulation systems for audio signals by interleaving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/03—Digital function generators working, at least partly, by table look-up
    • G06F1/0307—Logarithmic or exponential functions

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Algebra (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Probability & Statistics with Applications (AREA)
  • Data Mining & Analysis (AREA)
  • Databases & Information Systems (AREA)
  • Software Systems (AREA)
  • Error Detection And Correction (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Detection And Correction Of Errors (AREA)
  • Complex Calculations (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Mobile Radio Communication Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Burglar Alarm Systems (AREA)
  • Optical Communication System (AREA)
ES510691A 1981-03-23 1982-03-23 Circuito operativo para actuar en palabras de datos digitales. Expired ES8307393A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56041921A JPS57155667A (en) 1981-03-23 1981-03-23 Arithmetic circuit of galois matter

Publications (2)

Publication Number Publication Date
ES510691A0 true ES510691A0 (es) 1983-06-16
ES8307393A1 ES8307393A1 (es) 1983-06-16

Family

ID=12621708

Family Applications (1)

Application Number Title Priority Date Filing Date
ES510691A Expired ES8307393A1 (es) 1981-03-23 1982-03-23 Circuito operativo para actuar en palabras de datos digitales.

Country Status (11)

Country Link
US (1) US4473887A (es)
EP (1) EP0061345B1 (es)
JP (1) JPS57155667A (es)
KR (1) KR900005435B1 (es)
AT (1) ATE40927T1 (es)
AU (1) AU553405B2 (es)
BR (1) BR8201573A (es)
CA (1) CA1174764A (es)
DE (1) DE3279459D1 (es)
DK (1) DK160377C (es)
ES (1) ES8307393A1 (es)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58140846A (ja) * 1982-02-16 1983-08-20 Hitachi Ltd ２進化１０進数除算装置
DE3376907D1 (en) * 1982-06-15 1988-07-07 Toshiba Kk Apparatus for dividing the elements of a galois field
DE3377029D1 (en) * 1982-06-15 1988-07-14 Toshiba Kk Apparatus for dividing the elements of a galois field
JPS58219852A (ja) * 1982-06-15 1983-12-21 Toshiba Corp エラ−訂正回路
US4538240A (en) * 1982-12-30 1985-08-27 International Business Machines Corporation Method and apparatus for performing hashing operations using Galois field multiplication
FR2549984B1 (fr) * 1983-07-29 1985-10-18 Telediffusion Fse Systeme de correction d'erreurs de signaux numeriques codes en code de reed-solomon
EP0136587B1 (en) * 1983-09-06 1991-04-17 Kabushiki Kaisha Toshiba Error correction circuit
JPH0680491B2 (ja) * 1983-12-30 1994-10-12 ソニー株式会社 有限体の演算回路
JPS60160729A (ja) * 1984-01-31 1985-08-22 Sony Corp 有限体の演算回路
EP0169908B1 (en) * 1984-01-21 1993-12-01 Sony Corporation Method and circuit for decoding error coded data
JPS60183820A (ja) * 1984-03-02 1985-09-19 Trio Kenwood Corp 除算回路
FR2582888B1 (fr) * 1985-05-30 1987-08-21 Dornstetter Jean Louis Procede de transmission, avec possibilite de correction de paquets d'erreurs, de messages d'information et dispositifs de codage et de decodage pour la mise en oeuvre de ce procede.
JPH0728227B2 (ja) * 1985-06-07 1995-03-29 ソニー株式会社 Ｂｃｈ符号の復号装置
US4918638A (en) * 1986-10-15 1990-04-17 Matsushita Electric Industrial Co., Ltd. Multiplier in a galois field
JPS63132531A (ja) * 1986-11-25 1988-06-04 Ricoh Co Ltd 拡張ガロア体上の多項式除算回路
JPS63132532A (ja) * 1986-11-25 1988-06-04 Ricoh Co Ltd 拡張ガロア体上の多項式除算回路
AU613701B2 (en) * 1987-06-26 1991-08-08 Digital Equipment Corporation Apparatus for computing multiplicative inverses in data encoding decoding devices
US4975867A (en) * 1987-06-26 1990-12-04 Digital Equipment Corporation Apparatus for dividing elements of a Galois Field GF (2QM)
KR940001147B1 (ko) * 1991-03-20 1994-02-14 삼성전자 주식회사 부분체 GF(2^m/2)을 이용한 GF(2^m)상의 연산방법 및 장치
US6341327B1 (en) 1998-08-13 2002-01-22 Intel Corporation Content addressable memory addressable by redundant form input
US6172933B1 (en) * 1998-09-04 2001-01-09 Intel Corporation Redundant form address decoder for memory system
GB2537371B (en) * 2015-04-13 2019-10-02 Imagination Tech Ltd Modulo calculation using polynomials

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3805037A (en) * 1972-02-22 1974-04-16 J Ellison N{40 th power galois linear gate
JPS5825294B2 (ja) * 1975-12-18 1983-05-26 富士通株式会社 ３ジヨウカイロオシヨウシタエラ−テイセイカイロ
US4107652A (en) * 1975-12-27 1978-08-15 Fujitsu Limited Error correcting and controlling system
US4037093A (en) * 1975-12-29 1977-07-19 Honeywell Information Systems, Inc. Matrix multiplier in GF(2m)
US4030067A (en) * 1975-12-29 1977-06-14 Honeywell Information Systems, Inc. Table lookup direct decoder for double-error correcting (DEC) BCH codes using a pair of syndromes
US4099160A (en) * 1976-07-15 1978-07-04 International Business Machines Corporation Error location apparatus and methods
US4142174A (en) * 1977-08-15 1979-02-27 International Business Machines Corporation High speed decoding of Reed-Solomon codes
JPS554623A (en) * 1978-06-27 1980-01-14 Kokusai Electric Co Ltd Decoder circuit for bch code
DE2855807A1 (de) * 1978-12-22 1980-06-26 Siemens Ag Schaltungsanordnung zur korrektur von bytestrukturierten fehlern
US4251875A (en) * 1979-02-12 1981-02-17 Sperry Corporation Sequential Galois multiplication in GF(2n) with GF(2m) Galois multiplication gates

Also Published As

Publication number Publication date
DE3279459D1 (en) 1989-03-30
KR900005435B1 (ko) 1990-07-30
BR8201573A (pt) 1983-02-08
AU553405B2 (en) 1986-07-17
DK160377B (da) 1991-03-04
US4473887A (en) 1984-09-25
AU8173182A (en) 1982-09-30
JPS57155667A (en) 1982-09-25
ATE40927T1 (de) 1989-03-15
EP0061345A3 (en) 1984-05-02
EP0061345B1 (en) 1989-02-22
JPS645334B2 (es) 1989-01-30
DK128182A (da) 1982-09-24
KR830009529A (ko) 1983-12-21
ES8307393A1 (es) 1983-06-16
EP0061345A2 (en) 1982-09-29
DK160377C (da) 1991-08-12
CA1174764A (en) 1984-09-18

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20000301