JPS5484946A - Error correction unit - Google Patents

Error correction unit

Info

Publication number
JPS5484946A
JPS5484946A JP15340377A JP15340377A JPS5484946A JP S5484946 A JPS5484946 A JP S5484946A JP 15340377 A JP15340377 A JP 15340377A JP 15340377 A JP15340377 A JP 15340377A JP S5484946 A JPS5484946 A JP S5484946A
Authority
JP
Japan
Prior art keywords
bytes
error
data
error correction
check
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15340377A
Other languages
Japanese (ja)
Other versions
JPS5848938B2 (en
Inventor
Osamu Araya
Yutaka Kamiyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP52153403A priority Critical patent/JPS5848938B2/en
Publication of JPS5484946A publication Critical patent/JPS5484946A/en
Publication of JPS5848938B2 publication Critical patent/JPS5848938B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To extend the error correction function, by automatically correcting the error at two bytes mutually related, in which error is easily caused in advance.
CONSTITUTION: In the unit correcting byte error of the data taking the data bytes Do, D1...Dk-1 of K sets (4<K<2b) constituted in b-bit, the data bytes Do'...Dk-1' constituted with 1 byte b-bit and the check bytes C1' to C4' are read out from the memory unit 3, and error correction is made with the syndrome generation circuit 4, pointer generation circuit 5 and data reproduction circuit 6 and they are fed to CPU1. In corrective processing like this, when the check bytes C1 to C4 are generated at the specific non-zero dimensions T, T2...Tk-1 and dimensions T-1, T-2...Tk-1 and indentity dimension I at the Galois field 2b, two bytes arbitrarily determined in advance are related, and the check bytes C1 to C4 are caused as the relation of equation (1), when two data bytes are (Do, D1) (D1, D2)... (Dk-2, Dk-1).
COPYRIGHT: (C)1979,JPO&Japio
JP52153403A 1977-12-20 1977-12-20 error correction device Expired JPS5848938B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52153403A JPS5848938B2 (en) 1977-12-20 1977-12-20 error correction device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52153403A JPS5848938B2 (en) 1977-12-20 1977-12-20 error correction device

Publications (2)

Publication Number Publication Date
JPS5484946A true JPS5484946A (en) 1979-07-06
JPS5848938B2 JPS5848938B2 (en) 1983-11-01

Family

ID=15561718

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52153403A Expired JPS5848938B2 (en) 1977-12-20 1977-12-20 error correction device

Country Status (1)

Country Link
JP (1) JPS5848938B2 (en)

Also Published As

Publication number Publication date
JPS5848938B2 (en) 1983-11-01

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