JPS55102057A - Error correction unit - Google Patents

Error correction unit

Info

Publication number
JPS55102057A
JPS55102057A JP902279A JP902279A JPS55102057A JP S55102057 A JPS55102057 A JP S55102057A JP 902279 A JP902279 A JP 902279A JP 902279 A JP902279 A JP 902279A JP S55102057 A JPS55102057 A JP S55102057A
Authority
JP
Japan
Prior art keywords
circuit
bit
output
error correction
tripple
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP902279A
Other languages
Japanese (ja)
Inventor
Yutaka Kamiyanagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP902279A priority Critical patent/JPS55102057A/en
Publication of JPS55102057A publication Critical patent/JPS55102057A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To perform semiparallel decoding without remarkable increase in the hardware under the minimum inspection bit, by using the double error correction/ tripple error detection BCH code.
CONSTITUTION: The readout word includes K sets of information bits, 2m sets of inspection bits and one full parity bit, and logical sum is made with the circuit AD logically summing the output S3 of the double error bit indication circuit providing the circuits SQ and QB calculating the second and the third power on the Galois field GF(2m) and the output S1 of single error bit indication circuit, and the exclusive OR of the output of the circuit AD and each bit of the readout word is obtained in the circuit CMP. Accordingly, double error correction and further, tripple error detection can be made.
COPYRIGHT: (C)1980,JPO&Japio
JP902279A 1979-01-29 1979-01-29 Error correction unit Pending JPS55102057A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP902279A JPS55102057A (en) 1979-01-29 1979-01-29 Error correction unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP902279A JPS55102057A (en) 1979-01-29 1979-01-29 Error correction unit

Publications (1)

Publication Number Publication Date
JPS55102057A true JPS55102057A (en) 1980-08-04

Family

ID=11709023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP902279A Pending JPS55102057A (en) 1979-01-29 1979-01-29 Error correction unit

Country Status (1)

Country Link
JP (1) JPS55102057A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033523A (en) * 1989-05-12 1991-01-09 American Teleph & Telegr Co <Att> Method and device for correcting error and transmission system thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH033523A (en) * 1989-05-12 1991-01-09 American Teleph & Telegr Co <Att> Method and device for correcting error and transmission system thereof

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