JPS554623A - Decoder circuit for bch code - Google Patents

Decoder circuit for bch code

Info

Publication number
JPS554623A
JPS554623A JP7702878A JP7702878A JPS554623A JP S554623 A JPS554623 A JP S554623A JP 7702878 A JP7702878 A JP 7702878A JP 7702878 A JP7702878 A JP 7702878A JP S554623 A JPS554623 A JP S554623A
Authority
JP
Japan
Prior art keywords
circuit
error
reg
code
polynominal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7702878A
Other languages
Japanese (ja)
Inventor
Shinsuke Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP7702878A priority Critical patent/JPS554623A/en
Publication of JPS554623A publication Critical patent/JPS554623A/en
Pending legal-status Critical Current

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  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)

Abstract

PURPOSE: To shorten a decoding processing time by composing a circuit for the polynominal calculation of the number of error locations and error-bit-position calculation of a conversion table between vector expression codes of elements in a Galois field and powers, adder-subtracter circuit and register.
CONSTITUTION: To decode a two-element BCH code, syndrome Sj is calculated by received code polynominal expression r(X). Syndrome Sj is inputted to the calculation circuit for coefficient (σj) of the polynominal expression of error location composed of registers REG1 to REG7, adder circuit ADD, and exclusive-OR circuit EXOR. This circuit is provided with both-way conversion tables TB1 and TB2 between vector expression code (ak) of element (a) in the Galois field and power (k), and multiplication is substituted by addition. Similarly, coefficient (σj) is inputted to the error-bit-position calculation circuit consisting of registers REG8 to REG11, ADD, EXOR, and conversion tables TB1 and TB2; error bit position (k) is calculated and after it is discriminated by decision circuit CHK, the code error of a received-code sequence r(X) stored in REG11 is corrected, thereby outputting decoding output s(X).
COPYRIGHT: (C)1980,JPO&Japio
JP7702878A 1978-06-27 1978-06-27 Decoder circuit for bch code Pending JPS554623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7702878A JPS554623A (en) 1978-06-27 1978-06-27 Decoder circuit for bch code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7702878A JPS554623A (en) 1978-06-27 1978-06-27 Decoder circuit for bch code

Publications (1)

Publication Number Publication Date
JPS554623A true JPS554623A (en) 1980-01-14

Family

ID=13622283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7702878A Pending JPS554623A (en) 1978-06-27 1978-06-27 Decoder circuit for bch code

Country Status (1)

Country Link
JP (1) JPS554623A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155667A (en) * 1981-03-23 1982-09-25 Sony Corp Arithmetic circuit of galois matter
US6523054B1 (en) 1998-12-04 2003-02-18 Fujitsu Limited Galois field arithmetic processor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57155667A (en) * 1981-03-23 1982-09-25 Sony Corp Arithmetic circuit of galois matter
US6523054B1 (en) 1998-12-04 2003-02-18 Fujitsu Limited Galois field arithmetic processor

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