ES2177313T3 - Circuito de interfaz y procedimiento para la transmision de datos entre un interfaz en serie y un procesador. - Google Patents

Circuito de interfaz y procedimiento para la transmision de datos entre un interfaz en serie y un procesador.

Info

Publication number
ES2177313T3
ES2177313T3 ES99941524T ES99941524T ES2177313T3 ES 2177313 T3 ES2177313 T3 ES 2177313T3 ES 99941524 T ES99941524 T ES 99941524T ES 99941524 T ES99941524 T ES 99941524T ES 2177313 T3 ES2177313 T3 ES 2177313T3
Authority
ES
Spain
Prior art keywords
processor
data transmission
interface
procedure
serial interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES99941524T
Other languages
English (en)
Inventor
Klaus Klosa
Harald Hofmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of ES2177313T3 publication Critical patent/ES2177313T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
  • Bus Control (AREA)
  • Power Sources (AREA)

Abstract

Circuito de interfaz para la transmisión de datos a través de un interfaz en serie desde y hacia un procesador (CPU), caracterizado porque solamente está dispuesta una memoria para varias longitudes de palabra del bus o del procesador entre el interfaz en serie y el procesador (CPU), pudiendo ser escrita y leída la memoria (52) palabra por palabra o bit a bit.
ES99941524T 1998-08-05 1999-08-05 Circuito de interfaz y procedimiento para la transmision de datos entre un interfaz en serie y un procesador. Expired - Lifetime ES2177313T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP98114750A EP0978786A1 (de) 1998-08-05 1998-08-05 Interface-Schaltung und Verfahren zur Übertragung von Daten zwischen einer seriellen Schnittstelle und einem Prozessor

Publications (1)

Publication Number Publication Date
ES2177313T3 true ES2177313T3 (es) 2002-12-01

Family

ID=8232409

Family Applications (1)

Application Number Title Priority Date Filing Date
ES99941524T Expired - Lifetime ES2177313T3 (es) 1998-08-05 1999-08-05 Circuito de interfaz y procedimiento para la transmision de datos entre un interfaz en serie y un procesador.

Country Status (12)

Country Link
US (1) US6751689B2 (es)
EP (2) EP0978786A1 (es)
JP (1) JP3998911B2 (es)
KR (1) KR20010074800A (es)
CN (1) CN1210661C (es)
AT (1) ATE217428T1 (es)
BR (1) BR9913356A (es)
DE (1) DE59901408D1 (es)
ES (1) ES2177313T3 (es)
RU (1) RU2225028C2 (es)
UA (1) UA57155C2 (es)
WO (1) WO2000008566A2 (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6895518B2 (en) * 2001-05-31 2005-05-17 Koninklijke Philips Electronics N.V. Power and frequency adjustable UART device
US6993619B2 (en) * 2003-03-28 2006-01-31 International Business Machines Corporation Single request data transfer regardless of size and alignment
CN101355523B (zh) * 2008-09-26 2010-12-08 福建星网锐捷网络有限公司 一种数据传输控制方法与系统
JP5527512B2 (ja) * 2009-09-28 2014-06-18 ソニー株式会社 バスプロトコル変換装置及びバスプロトコル変換方法
KR101558687B1 (ko) * 2013-12-10 2015-10-08 현대자동차주식회사 직렬 통신 테스트 장치, 시스템 및 방법
RU2730116C2 (ru) * 2015-11-30 2020-08-17 Общество с ограниченной ответственностью "Параллелз" (ООО "Параллелз") Способ передачи данных между интерфейсами модулей обработки данных вычислительной системы
CN110968270B (zh) * 2019-11-22 2024-06-07 中山优感科技有限公司 一种Flash空间的高效存储方法及装置

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1993011509A1 (en) * 1991-12-04 1993-06-10 Citizen Watch Co., Ltd. Data carrier
EP0290172A3 (en) * 1987-04-30 1991-01-16 Advanced Micro Devices, Inc. Bidirectional fifo with variable byte boundary and data path width change
CA1286420C (en) 1987-10-14 1991-07-16 Youssef Alfred Geadah Fifo buffer controller
JP2750704B2 (ja) 1988-08-29 1998-05-13 日立マクセル株式会社 Ｉｃカードの情報書込み方式及びｉｃカード
KR900005313A (ko) * 1988-09-14 1990-04-14 존 지.웨브 16비트 데이타 버스에 바이트폭 uart 전송을 이행하는 방법 및 장치
RU2047920C1 (ru) 1989-11-09 1995-11-10 Сараев Василий Григорьевич Устройство для программирования микросхем постоянной памяти
US5293381A (en) * 1992-03-27 1994-03-08 Advanced Micro Devices Byte tracking system and method
JPH0652052A (ja) * 1992-07-28 1994-02-25 Hitachi Ltd 仮想共用記憶方式
JPH06110798A (ja) * 1992-09-26 1994-04-22 Ricoh Co Ltd Ｉ／ｏ疑似動作装置
US6295572B1 (en) * 1994-01-24 2001-09-25 Advanced Micro Devices, Inc. Integrated SCSI and ethernet controller on a PCI local bus
JP3371174B2 (ja) 1994-09-22 2003-01-27 ソニー株式会社 パケット受信装置
US5717870A (en) * 1994-10-26 1998-02-10 Hayes Microcomputer Products, Inc. Serial port controller for preventing repetitive interrupt signals
JPH08202469A (ja) * 1995-01-30 1996-08-09 Fujitsu Ltd ユニバーサル非同期送受信回路を備えたマイクロ・コントローラユニット
JPH08314851A (ja) * 1995-05-23 1996-11-29 Fujitsu Ltd データ処理システム
JPH1063617A (ja) * 1996-08-15 1998-03-06 Sony Corp シリアル通信装置
JPH1084528A (ja) 1996-09-10 1998-03-31 Sony Corp 記録媒体再生装置および方法
JP3451576B2 (ja) * 1996-09-20 2003-09-29 株式会社日立製作所 情報処理システム
US6201817B1 (en) * 1998-05-28 2001-03-13 3Com Corporation Memory based buffering for a UART or a parallel UART like interface

Also Published As

Publication number Publication date
ATE217428T1 (de) 2002-05-15
CN1322319A (zh) 2001-11-14
JP3998911B2 (ja) 2007-10-31
RU2225028C2 (ru) 2004-02-27
DE59901408D1 (de) 2002-06-13
US6751689B2 (en) 2004-06-15
US20010012326A1 (en) 2001-08-09
EP1101170A2 (de) 2001-05-23
CN1210661C (zh) 2005-07-13
UA57155C2 (uk) 2003-06-16
KR20010074800A (ko) 2001-08-09
BR9913356A (pt) 2001-05-15
WO2000008566A3 (de) 2000-06-15
EP1101170B1 (de) 2002-05-08
JP2002522828A (ja) 2002-07-23
WO2000008566A2 (de) 2000-02-17
EP0978786A1 (de) 2000-02-09

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