ES2075856T3 - Tampon bidireccional con capacidad de bascula de retencion y de paridad. - Google Patents
Tampon bidireccional con capacidad de bascula de retencion y de paridad.Info
- Publication number
- ES2075856T3 ES2075856T3 ES89480053T ES89480053T ES2075856T3 ES 2075856 T3 ES2075856 T3 ES 2075856T3 ES 89480053 T ES89480053 T ES 89480053T ES 89480053 T ES89480053 T ES 89480053T ES 2075856 T3 ES2075856 T3 ES 2075856T3
- Authority
- ES
- Spain
- Prior art keywords
- data
- circuit
- parity
- intermediate storage
- hitching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
- G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
- G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/0823—Multistate logic
- H03K19/0826—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
- H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
- H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
- H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
- H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Quality & Reliability (AREA)
- Logic Circuits (AREA)
- Detection And Correction Of Errors (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
- Information Transfer Systems (AREA)
Abstract
CIRCUITO PARA ALMACENAR Y CONTROLAR LA PARIDAD DE DATOS DIGITALES COMUNICADOS ENTRE UN PRIMER Y UN SEGUNDO BUSES DE DATOS, QUE INCLUYE UNA PLURALIDAD DE CIRUITOS BIDIRECCIONALES DE ALMACENAMIENTO INTERMEDIO. CADA UNO DE LOS CIRCUITOS BIDIRECCIONALES DE ALMACENAMIENTO INTERMEDIO INCLUYE UNA VIA DE DATOS QUE CONSTA DE UN RECEPTOR DE DATOS, UN ELEMENTO ENGANCHADOR Y UN EXCITADOR CONECTADOS EN SERIE ENTRE EL PRIMER Y EL SEGUNDO BUSES DE DATOS, RESPECTIVAMENTE; UNA SEGUNDA VIA DE DATOS QUE CONSTA DE UN RECEPTOR DE DATOS, UN ELEMENTO DE ENGANCHE Y UN EXCITADOR CONECTADOS EN SERIE ENTRE EL SEGUNDO Y EL PRIMER BUSES DE DATOS, RESPECTIVAMENTE; UN MECANISMO DE CONTROL PARA CONTROLAR QUE LOS EXCITADORES COLOQUEN SELECTIVAMENTE SU SALIDA EN UN ESTADO DE EXCITACION ACTIVA O DE ALTA IMPEDANCIA; Y UN MECANISMO DE CONTROL PARA CONTROLAR LOS ELEMENTOS DE ENGANCHE DE DATOS PARA ENGANCHARSE O PASAR A TRAVES DE LOS DATOS DE FORMA SELECTIVA. UN CIRCUITO GENERADOR DE PARIDAD ESTA CONECTADO A LA SALIDA DEL ELEMENTO DE ENGANCHE EN LA PRIMERA VIA DE DATOS DE CADA CIRCUITO BIDIRECCIONAL DE ALMACENAMIENTO INTERMEDIO PARA GENERAR UN BIT DE PARIDAD QUE RESPONDA A LOS DATOS DE LA SALIDA DE DICHOS ELEMENTOS DE ENGANCHE. HAY UN CIRCUITO TRANSPARENTE Y EXCITADOR CON DIVISOR DE FASE PARA INCREMENTAR LA VELOCIDAD DEL CIRCUITO SIN INCREMENTAR SUSTANCIALMENTE LAS NECESIDADES DE ENERGIA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/198,961 US5107507A (en) | 1988-05-26 | 1988-05-26 | Bidirectional buffer with latch and parity capability |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2075856T3 true ES2075856T3 (es) | 1995-10-16 |
Family
ID=22735618
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES89480053T Expired - Lifetime ES2075856T3 (es) | 1988-05-26 | 1989-04-11 | Tampon bidireccional con capacidad de bascula de retencion y de paridad. |
Country Status (12)
Country | Link |
---|---|
US (1) | US5107507A (es) |
EP (2) | EP0630112A3 (es) |
JP (1) | JPH01314338A (es) |
KR (1) | KR920010553B1 (es) |
CN (1) | CN1011556B (es) |
AR (1) | AR246645A1 (es) |
BR (1) | BR8902376A (es) |
CA (1) | CA1338155C (es) |
DE (1) | DE68923818T2 (es) |
ES (1) | ES2075856T3 (es) |
MY (2) | MY104736A (es) |
SG (1) | SG44402A1 (es) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173619A (en) * | 1988-05-26 | 1992-12-22 | International Business Machines Corporation | Bidirectional buffer with latch and parity capability |
JP3118266B2 (ja) * | 1990-03-06 | 2000-12-18 | ゼロックス コーポレイション | 同期セグメントバスとバス通信方法 |
US5498976A (en) * | 1990-10-26 | 1996-03-12 | Acer Incorporated | Parallel buffer/driver configuration between data sending terminal and data receiving terminal |
US5355377A (en) * | 1993-11-23 | 1994-10-11 | Tetra Assoc. Inc. | Auto-selectable self-parity generator |
JP3101552B2 (ja) * | 1994-11-14 | 2000-10-23 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | 周辺バス利用の通信システム及び方法 |
IT1277386B1 (it) * | 1995-07-28 | 1997-11-10 | Alcatel Italia | Apparato per lo scambio di informazioni tra carte di identificazione a circuiti integrati e un dispositivo terminale |
US5761465A (en) * | 1996-03-29 | 1998-06-02 | Cirrus Logic, Inc. | System for coupling asynchronous data path to field check circuit of synchronous data path when the asynchronous data path communicating data in synchronous format |
US7132247B1 (en) * | 1998-09-17 | 2006-11-07 | Regents Of The University Of Minnesota | Composite devices incorporating biological material and methods |
US7737727B2 (en) * | 2007-12-17 | 2010-06-15 | Intersil Americas Inc. | Bi-directional buffer for open-drain or open-collector bus |
US7692450B2 (en) * | 2007-12-17 | 2010-04-06 | Intersil Americas Inc. | Bi-directional buffer with level shifting |
US7639045B2 (en) * | 2008-05-23 | 2009-12-29 | Intersil Americas Inc. | Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback |
US9183713B2 (en) | 2011-02-22 | 2015-11-10 | Kelly Research Corp. | Perimeter security system |
Family Cites Families (56)
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US2873363A (en) * | 1954-01-18 | 1959-02-10 | North American Aviation Inc | Logical gating system for digital computers |
US2951951A (en) * | 1955-10-31 | 1960-09-06 | Philips Corp | Electric gating and the like |
US3215852A (en) * | 1960-06-29 | 1965-11-02 | Ibm | Monostable transistor trigger having both transistors normally biased in the non-conducting state |
US3112413A (en) * | 1960-08-12 | 1963-11-26 | Honeywell Regulator Co | Synchronous logic circuit |
NL282320A (es) * | 1961-08-22 | |||
US3170075A (en) * | 1962-07-24 | 1965-02-16 | Bunker Ramo | Delay flip-flop circuit |
US3231763A (en) * | 1963-10-07 | 1966-01-25 | Bunker Ramo | Bistable memory element |
US3283175A (en) * | 1964-01-08 | 1966-11-01 | James E Webb | A.c. logic flip-flop circuits |
US3421026A (en) * | 1964-06-29 | 1969-01-07 | Gen Electric | Memory flip-flop |
US3324307A (en) * | 1964-09-10 | 1967-06-06 | Bunker Ramo | Flip-flop circuit |
US3424923A (en) * | 1965-06-29 | 1969-01-28 | Logicon Inc | Binary circuit |
US3602733A (en) * | 1969-04-16 | 1971-08-31 | Signetics Corp | Three output level logic circuit |
US3805233A (en) * | 1972-06-28 | 1974-04-16 | Tymshare Inc | Error checking method and apparatus for group of control logic units |
US3914628A (en) * | 1972-10-27 | 1975-10-21 | Raytheon Co | T-T-L driver circuitry |
US3824408A (en) * | 1973-07-20 | 1974-07-16 | Microsystems Int Ltd | Driver circuit |
US4044271A (en) * | 1974-09-09 | 1977-08-23 | The United States Of America As Represented By The Secretary Of The Navy | Monolithic NTDS driver and receiver |
JPS5710511B2 (es) * | 1974-12-27 | 1982-02-26 | ||
JPS53116121A (en) * | 1977-03-18 | 1978-10-11 | Beltek Corp | Device for attaching*detaching cassette |
US4153883A (en) * | 1977-12-16 | 1979-05-08 | Harris Corporation | Electrically alterable amplifier configurations |
JPS54159143A (en) * | 1978-06-06 | 1979-12-15 | Nippon Telegr & Teleph Corp <Ntt> | Combined circuit with parity check and parity generation |
US4287433A (en) * | 1979-01-24 | 1981-09-01 | Fairchild Camera & Instrument Corp. | Transistor logic tristate output with reduced power dissipation |
US4251884A (en) * | 1979-02-09 | 1981-02-17 | Bell Telephone Laboratories, Incorporated | Parity circuits |
US4311927A (en) * | 1979-07-18 | 1982-01-19 | Fairchild Camera & Instrument Corp. | Transistor logic tristate device with reduced output capacitance |
US4357547A (en) * | 1981-02-23 | 1982-11-02 | Motorola, Inc. | EFL Toggle flip-flop |
US4429391A (en) * | 1981-05-04 | 1984-01-31 | Bell Telephone Laboratories, Incorporated | Fault and error detection arrangement |
US4462102A (en) * | 1981-11-13 | 1984-07-24 | International Business Machines Corporation | Method and apparatus for checking the parity of disassociated bit groups |
JPS58147807A (ja) * | 1982-02-26 | 1983-09-02 | Toshiba Corp | 誤り訂正回路 |
US4477904A (en) * | 1982-03-08 | 1984-10-16 | Sperry Corporation | Parity generation/detection logic circuit from transfer gates |
JPS58182922A (ja) * | 1982-04-21 | 1983-10-26 | Toshiba Corp | 入力インタ−フエイス回路 |
JPS58219852A (ja) * | 1982-06-15 | 1983-12-21 | Toshiba Corp | エラ−訂正回路 |
US4485470A (en) * | 1982-06-16 | 1984-11-27 | Rolm Corporation | Data line interface for a time-division multiplexing (TDM) bus |
US4409189A (en) * | 1982-07-13 | 1983-10-11 | The United States Of America As Represented By The Secretary Of The Interior | Recovery of tungsten from brines |
US4528465A (en) * | 1982-11-15 | 1985-07-09 | Advanced Micro Devices, Inc. | Semiconductor circuit alternately operative as a data latch and a logic gate |
JPS59148199A (ja) * | 1983-02-15 | 1984-08-24 | Nec Corp | メモリパリテイ回路 |
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US4872172A (en) * | 1987-11-30 | 1989-10-03 | Tandem Computers Incorporated | Parity regeneration self-checking |
-
1988
- 1988-05-26 US US07/198,961 patent/US5107507A/en not_active Expired - Fee Related
-
1989
- 1989-04-11 EP EP94113671A patent/EP0630112A3/en not_active Withdrawn
- 1989-04-11 ES ES89480053T patent/ES2075856T3/es not_active Expired - Lifetime
- 1989-04-11 DE DE68923818T patent/DE68923818T2/de not_active Expired - Fee Related
- 1989-04-11 SG SG1996000189A patent/SG44402A1/en unknown
- 1989-04-11 EP EP89480053A patent/EP0344081B1/en not_active Expired - Lifetime
- 1989-04-14 CA CA000596778A patent/CA1338155C/en not_active Expired - Fee Related
- 1989-04-20 JP JP1099040A patent/JPH01314338A/ja active Pending
- 1989-04-26 MY MYPI89000551A patent/MY104736A/en unknown
- 1989-04-26 MY MYPI93001905A patent/MY112563A/en unknown
- 1989-04-26 KR KR898905485A patent/KR920010553B1/ko not_active IP Right Cessation
- 1989-05-03 CN CN89102936A patent/CN1011556B/zh not_active Expired
- 1989-05-17 AR AR89313950A patent/AR246645A1/es active
- 1989-05-24 BR BR898902376A patent/BR8902376A/pt unknown
Also Published As
Publication number | Publication date |
---|---|
EP0344081B1 (en) | 1995-08-16 |
BR8902376A (pt) | 1990-01-16 |
CN1011556B (zh) | 1991-02-06 |
JPH01314338A (ja) | 1989-12-19 |
US5107507A (en) | 1992-04-21 |
DE68923818D1 (de) | 1995-09-21 |
DE68923818T2 (de) | 1996-04-18 |
CA1338155C (en) | 1996-03-12 |
EP0630112A2 (en) | 1994-12-21 |
MY112563A (en) | 2001-07-31 |
AR246645A1 (es) | 1994-08-31 |
CN1037981A (zh) | 1989-12-13 |
SG44402A1 (en) | 1997-12-19 |
EP0344081A2 (en) | 1989-11-29 |
KR920010553B1 (en) | 1992-12-05 |
MY104736A (en) | 1994-05-31 |
KR890017904A (ko) | 1989-12-18 |
EP0630112A3 (en) | 1995-11-22 |
EP0344081A3 (en) | 1991-05-02 |
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FG2A | Definitive protection |
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