DE68923818D1 - Bidirektionaler Puffer mit Verriegelungs- und Paritätsfähigkeiten. - Google Patents

Bidirektionaler Puffer mit Verriegelungs- und Paritätsfähigkeiten.

Info

Publication number
DE68923818D1
DE68923818D1 DE68923818T DE68923818T DE68923818D1 DE 68923818 D1 DE68923818 D1 DE 68923818D1 DE 68923818 T DE68923818 T DE 68923818T DE 68923818 T DE68923818 T DE 68923818T DE 68923818 D1 DE68923818 D1 DE 68923818D1
Authority
DE
Germany
Prior art keywords
locking
bidirectional buffer
parity
capabilities
parity capabilities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923818T
Other languages
English (en)
Other versions
DE68923818T2 (de
Inventor
Patrick Maurice Bland
Kevin Gerrard Kramer
Mark Edward Dean
Susan Lynn Tempest
Gene Joseph Gaudenzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE68923818D1 publication Critical patent/DE68923818D1/de
Publication of DE68923818T2 publication Critical patent/DE68923818T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/0823—Multistate logic
    • H03K19/0826—Multistate logic one of the states being the high impedance or floating state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Quality & Reliability (AREA)
  • Logic Circuits (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Dc Digital Transmission (AREA)
  • Information Transfer Systems (AREA)
DE68923818T 1988-05-26 1989-04-11 Bidirektionaler Puffer mit Verriegelungs- und Paritätsfähigkeiten. Expired - Fee Related DE68923818T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/198,961 US5107507A (en) 1988-05-26 1988-05-26 Bidirectional buffer with latch and parity capability

Publications (2)

Publication Number Publication Date
DE68923818D1 true DE68923818D1 (de) 1995-09-21
DE68923818T2 DE68923818T2 (de) 1996-04-18

Family

ID=22735618

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923818T Expired - Fee Related DE68923818T2 (de) 1988-05-26 1989-04-11 Bidirektionaler Puffer mit Verriegelungs- und Paritätsfähigkeiten.

Country Status (12)

Country Link
US (1) US5107507A (de)
EP (2) EP0630112A3 (de)
JP (1) JPH01314338A (de)
KR (1) KR920010553B1 (de)
CN (1) CN1011556B (de)
AR (1) AR246645A1 (de)
BR (1) BR8902376A (de)
CA (1) CA1338155C (de)
DE (1) DE68923818T2 (de)
ES (1) ES2075856T3 (de)
MY (2) MY112563A (de)
SG (1) SG44402A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5173619A (en) * 1988-05-26 1992-12-22 International Business Machines Corporation Bidirectional buffer with latch and parity capability
JP3118266B2 (ja) * 1990-03-06 2000-12-18 ゼロックス コーポレイション 同期セグメントバスとバス通信方法
US5498976A (en) * 1990-10-26 1996-03-12 Acer Incorporated Parallel buffer/driver configuration between data sending terminal and data receiving terminal
US5355377A (en) * 1993-11-23 1994-10-11 Tetra Assoc. Inc. Auto-selectable self-parity generator
JP3101552B2 (ja) * 1994-11-14 2000-10-23 インターナショナル・ビジネス・マシーンズ・コーポレ−ション 周辺バス利用の通信システム及び方法
IT1277386B1 (it) * 1995-07-28 1997-11-10 Alcatel Italia Apparato per lo scambio di informazioni tra carte di identificazione a circuiti integrati e un dispositivo terminale
US5761465A (en) * 1996-03-29 1998-06-02 Cirrus Logic, Inc. System for coupling asynchronous data path to field check circuit of synchronous data path when the asynchronous data path communicating data in synchronous format
US7132247B1 (en) * 1998-09-17 2006-11-07 Regents Of The University Of Minnesota Composite devices incorporating biological material and methods
US7692450B2 (en) * 2007-12-17 2010-04-06 Intersil Americas Inc. Bi-directional buffer with level shifting
US7737727B2 (en) * 2007-12-17 2010-06-15 Intersil Americas Inc. Bi-directional buffer for open-drain or open-collector bus
US7639045B2 (en) * 2008-05-23 2009-12-29 Intersil Americas Inc. Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback
US9183713B2 (en) 2011-02-22 2015-11-10 Kelly Research Corp. Perimeter security system

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US3215852A (en) * 1960-06-29 1965-11-02 Ibm Monostable transistor trigger having both transistors normally biased in the non-conducting state
US3112413A (en) * 1960-08-12 1963-11-26 Honeywell Regulator Co Synchronous logic circuit
NL282320A (de) * 1961-08-22
US3170075A (en) * 1962-07-24 1965-02-16 Bunker Ramo Delay flip-flop circuit
US3231763A (en) * 1963-10-07 1966-01-25 Bunker Ramo Bistable memory element
US3283175A (en) * 1964-01-08 1966-11-01 James E Webb A.c. logic flip-flop circuits
US3421026A (en) * 1964-06-29 1969-01-07 Gen Electric Memory flip-flop
US3324307A (en) * 1964-09-10 1967-06-06 Bunker Ramo Flip-flop circuit
US3424923A (en) * 1965-06-29 1969-01-28 Logicon Inc Binary circuit
US3602733A (en) * 1969-04-16 1971-08-31 Signetics Corp Three output level logic circuit
US3805233A (en) * 1972-06-28 1974-04-16 Tymshare Inc Error checking method and apparatus for group of control logic units
US3914628A (en) * 1972-10-27 1975-10-21 Raytheon Co T-T-L driver circuitry
US3824408A (en) * 1973-07-20 1974-07-16 Microsystems Int Ltd Driver circuit
US4044271A (en) * 1974-09-09 1977-08-23 The United States Of America As Represented By The Secretary Of The Navy Monolithic NTDS driver and receiver
JPS5710511B2 (de) * 1974-12-27 1982-02-26
JPS53116121A (en) * 1977-03-18 1978-10-11 Beltek Corp Device for attaching*detaching cassette
US4153883A (en) * 1977-12-16 1979-05-08 Harris Corporation Electrically alterable amplifier configurations
JPS54159143A (en) * 1978-06-06 1979-12-15 Nippon Telegr & Teleph Corp <Ntt> Combined circuit with parity check and parity generation
US4287433A (en) * 1979-01-24 1981-09-01 Fairchild Camera & Instrument Corp. Transistor logic tristate output with reduced power dissipation
US4251884A (en) * 1979-02-09 1981-02-17 Bell Telephone Laboratories, Incorporated Parity circuits
US4311927A (en) * 1979-07-18 1982-01-19 Fairchild Camera & Instrument Corp. Transistor logic tristate device with reduced output capacitance
US4357547A (en) * 1981-02-23 1982-11-02 Motorola, Inc. EFL Toggle flip-flop
US4429391A (en) * 1981-05-04 1984-01-31 Bell Telephone Laboratories, Incorporated Fault and error detection arrangement
US4462102A (en) * 1981-11-13 1984-07-24 International Business Machines Corporation Method and apparatus for checking the parity of disassociated bit groups
JPS58147807A (ja) * 1982-02-26 1983-09-02 Toshiba Corp 誤り訂正回路
US4477904A (en) * 1982-03-08 1984-10-16 Sperry Corporation Parity generation/detection logic circuit from transfer gates
JPS58182922A (ja) * 1982-04-21 1983-10-26 Toshiba Corp 入力インタ−フエイス回路
JPS58219852A (ja) * 1982-06-15 1983-12-21 Toshiba Corp エラ−訂正回路
US4485470A (en) * 1982-06-16 1984-11-27 Rolm Corporation Data line interface for a time-division multiplexing (TDM) bus
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US4528465A (en) * 1982-11-15 1985-07-09 Advanced Micro Devices, Inc. Semiconductor circuit alternately operative as a data latch and a logic gate
JPS59148199A (ja) * 1983-02-15 1984-08-24 Nec Corp メモリパリテイ回路
JPS607549A (ja) * 1983-06-24 1985-01-16 Mitsubishi Electric Corp 故障診断装置
JPS6043753A (ja) * 1983-08-18 1985-03-08 Fuji Xerox Co Ltd 故障検出回路
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JPS60153223A (ja) * 1984-01-20 1985-08-12 Ricoh Co Ltd 入力バツフア回路
US4622475A (en) * 1984-03-05 1986-11-11 Tektronix, Inc. Data storage element having input and output ports isolated from regenerative circuit
US4608693A (en) * 1984-05-07 1986-08-26 At&T Bell Laboratories Fault detection arrangement for a digital conferencing system
JPS60251442A (ja) * 1984-05-29 1985-12-12 Fujitsu Ltd 双方向バス用パリテイ回路
US4661727A (en) * 1984-07-19 1987-04-28 Fairchild Semiconductor Corporation Multiple phase-splitter TTL output circuit with improved drive characteristics
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US4685088A (en) * 1985-04-15 1987-08-04 International Business Machines Corporation High performance memory system utilizing pipelining techniques
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US4872172A (en) * 1987-11-30 1989-10-03 Tandem Computers Incorporated Parity regeneration self-checking

Also Published As

Publication number Publication date
JPH01314338A (ja) 1989-12-19
CN1037981A (zh) 1989-12-13
EP0344081A3 (de) 1991-05-02
MY112563A (en) 2001-07-31
EP0344081B1 (de) 1995-08-16
DE68923818T2 (de) 1996-04-18
EP0630112A3 (de) 1995-11-22
BR8902376A (pt) 1990-01-16
CA1338155C (en) 1996-03-12
SG44402A1 (en) 1997-12-19
KR920010553B1 (en) 1992-12-05
ES2075856T3 (es) 1995-10-16
MY104736A (en) 1994-05-31
US5107507A (en) 1992-04-21
AR246645A1 (es) 1994-08-31
EP0630112A2 (de) 1994-12-21
KR890017904A (ko) 1989-12-18
CN1011556B (zh) 1991-02-06
EP0344081A2 (de) 1989-11-29

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee