ES2056057T3 - Metodo y circuito para la carga inicial de un ordenador secundario. - Google Patents

Metodo y circuito para la carga inicial de un ordenador secundario.

Info

Publication number
ES2056057T3
ES2056057T3 ES87117034T ES87117034T ES2056057T3 ES 2056057 T3 ES2056057 T3 ES 2056057T3 ES 87117034 T ES87117034 T ES 87117034T ES 87117034 T ES87117034 T ES 87117034T ES 2056057 T3 ES2056057 T3 ES 2056057T3
Authority
ES
Spain
Prior art keywords
computer
memory
cpu2
processing unit
central processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87117034T
Other languages
English (en)
Inventor
Dieter Kopp
Thomas Hormann
Uwe Ackermann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel NV filed Critical Alcatel NV
Application granted granted Critical
Publication of ES2056057T3 publication Critical patent/ES2056057T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stored Programmes (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

UN COMPUTADOR SECUNDARIO (RE2) ESTA CONECTADO POR UN DEPOSITO (M) GENERAL CON UN COMPUTADOR PRINCIPAL (RE1). PARA CARGA DEL COMPUTADOR SECUNDARIO (RE2) SE ARCHIVA UN PROGRAMA DE CARGA EN UN DEPOSITO DE MASA (MSP) DEL COMPUTADOR PRINCIPAL (RE1), EN LUGAR DE LO HABITUAL EN UN DEPOSITO RUTINARIO DE PARTIDA. EL COMPUTADOR PRINCIPAL (RE1) CARGA EL PROGRAMA DE CARGA EN EL DEPOSITO GENERAL (M), COLOCA UN MANDO DE NUEVO ARRANQUE EN UN UNIDAD CENTRAL (CPU2) DEL COMPUTADOR SECUNDARIO (RE2) Y DIRIGE UNA LOGICA DE AGARRE DE DEPOSITO (SZL) DE MODO QUE TODOS LOS MANDOS DE AGARRE DE DEPOSITO DEL PROGRAMA QUE LLEGAN A LA UNIDAD CENTRAL (CPU2) SE CONDUCEN SOBRE LA PARTE DEL DEPOSITO GENERAL (M), EN EL QUE SE HA DESARCHIVADO EL PROGRAMA DE CARGA, HASTA QUE EL COMPUTADOR SECUNDARIO (RE2) HA LEIDO EL PROGRAMA DE CARGA. ENTONCES LA LOGICA DE AGARRE DEL DEPOSITO (SZL) RECIBE DE LA UNIDAD CENTRAL (CPU2) UNA SEÑAL DE RECIBO, POR LO QUE LA LOGICA DE AGARRE DE DEPOSITO (SZL) CONDUCE CON TODOS LOS SIGUIENTES MANDOS DE AGARRE DE DEPOSITO DEL PROGRAMA DE LA UNIDAD CENTRAL (CPU2) EN UN DEPOSITO DE PROGRAMA (MP2) DEL COMPUTADOR SECUNDARIO (RE2).
ES87117034T 1986-11-20 1987-11-19 Metodo y circuito para la carga inicial de un ordenador secundario. Expired - Lifetime ES2056057T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19863639571 DE3639571A1 (de) 1986-11-20 1986-11-20 Verfahren und schaltungsanordnung zum urladen eines zweitrechners

Publications (1)

Publication Number Publication Date
ES2056057T3 true ES2056057T3 (es) 1994-10-01

Family

ID=6314314

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87117034T Expired - Lifetime ES2056057T3 (es) 1986-11-20 1987-11-19 Metodo y circuito para la carga inicial de un ordenador secundario.

Country Status (6)

Country Link
US (1) US4943911A (es)
EP (1) EP0268285B1 (es)
JP (1) JPS63233460A (es)
AT (1) ATE106151T1 (es)
DE (2) DE3639571A1 (es)
ES (1) ES2056057T3 (es)

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CA2111237C (en) * 1991-06-26 2002-01-15 Barry Kennedy Multiprocessor distributed initialization and self-test system
EP0535265B1 (de) * 1991-09-30 1998-03-18 Siemens Aktiengesellschaft Verfahren zur Erstellung einer ablauffähigen Konfiguration eines in einen Systemspeicherbereich eines Prozessorsystems ladbaren Systemprogramms
US5452454A (en) * 1991-12-10 1995-09-19 Digital Equipment Corporation Generic remote boot for networked workstations by creating local bootable code image
WO1993025945A1 (en) * 1992-06-12 1993-12-23 The Dow Chemical Company Stealth interface for process control computers
US6438683B1 (en) 1992-07-28 2002-08-20 Eastman Kodak Company Technique using FIFO memory for booting a programmable microprocessor from a host computer
US5448716A (en) * 1992-10-30 1995-09-05 International Business Machines Corporation Apparatus and method for booting a multiple processor system having a global/local memory architecture
US5537654A (en) * 1993-05-20 1996-07-16 At&T Corp. System for PCMCIA peripheral to execute instructions from shared memory where the system reset signal causes switching between modes of operation by alerting the starting address
JPH07253960A (ja) * 1994-03-16 1995-10-03 Fujitsu Ltd マルチプロセッサシステムにおけるｉｐｌ方式
GB9422854D0 (en) * 1994-11-12 1995-01-04 Int Computers Ltd High availability data processing system
DE19503312A1 (de) * 1995-02-02 1996-08-08 Sel Alcatel Ag Verfahren und Schaltungsanordnung für das Laden von Rechnern mit einem Rechnerstartprogramm
US5696949A (en) * 1995-06-15 1997-12-09 Intel Corporation System for PCI slots expansion using asynchronous PCI-to-PCI bridge with clock generator for providing clock signal to the expansion mother board and expansion side of bridge
US5898869A (en) * 1996-09-20 1999-04-27 The Foxboro Company Method and system for PCMCIA card boot from dual-ported memory
JPH10283329A (ja) 1997-04-02 1998-10-23 Matsushita Electric Ind Co Ltd メモリ排他制御方法
DE19751093A1 (de) * 1997-11-18 1999-05-27 Siemens Ag Programmgesteuerte Einheit
US6055631A (en) * 1997-12-18 2000-04-25 Intel Corporation Method and apparatus for booting a portable computing device
WO2001027753A2 (en) * 1999-10-12 2001-04-19 Scientific-Atlanta, Inc. Method and apparatus for loading software into a plurality of processors
US6738852B1 (en) * 2000-09-27 2004-05-18 Palm Source, Inc. Palmtop computer expansion using shared memory access
US7032106B2 (en) * 2001-12-27 2006-04-18 Computer Network Technology Corporation Method and apparatus for booting a microprocessor
CN101091159B (zh) * 2004-12-30 2011-02-23 Nxp股份有限公司 数据处理装置
US7356680B2 (en) * 2005-01-22 2008-04-08 Telefonaktiebolaget L M Ericsson (Publ) Method of loading information into a slave processor in a multi-processor system using an operating-system-friendly boot loader
JP2007157150A (ja) * 2005-12-06 2007-06-21 Samsung Electronics Co Ltd メモリシステム及びそれを含むメモリ処理方法
KR101275752B1 (ko) 2005-12-06 2013-06-17 삼성전자주식회사 메모리 시스템 및 그것의 부팅 방법
US8209527B2 (en) 2006-10-26 2012-06-26 Samsung Electronics Co., Ltd. Memory system and memory management method including the same
KR100855580B1 (ko) * 2007-06-18 2008-09-01 삼성전자주식회사 프로세서 리셋 기능을 갖는 반도체 메모리 장치 및 그를 채용한 멀티 프로세서 시스템과 그에 따른 프로세서 리셋 제어방법
KR20090095955A (ko) * 2008-03-07 2009-09-10 삼성전자주식회사 불휘발성 메모리의 공유 구조에서 다이렉트 억세스 기능을제공하는 멀티포트 반도체 메모리 장치 및 그를 채용한멀티 프로세서 시스템
US8838949B2 (en) * 2010-03-22 2014-09-16 Qualcomm Incorporated Direct scatter loading of executable software image from a primary processor to one or more secondary processor in a multi-processor system
US9058191B2 (en) * 2010-03-22 2015-06-16 Qualcomm Incorporated Direct transfer of executable software image to memory allocated by target processor based on transferred image header
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Also Published As

Publication number Publication date
ATE106151T1 (de) 1994-06-15
US4943911A (en) 1990-07-24
DE3789889D1 (de) 1994-06-30
EP0268285A3 (de) 1991-02-20
EP0268285B1 (de) 1994-05-25
JPS63233460A (ja) 1988-09-29
DE3639571A1 (de) 1988-06-01
EP0268285A2 (de) 1988-05-25

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