EP3127161A1 - Procédé de formation d'une plaque de champ diélectrique dans une tranchée d'un substrat, substrat correspondant et transistor de puissance - Google Patents

Procédé de formation d'une plaque de champ diélectrique dans une tranchée d'un substrat, substrat correspondant et transistor de puissance

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Publication number
EP3127161A1
EP3127161A1 EP15708232.2A EP15708232A EP3127161A1 EP 3127161 A1 EP3127161 A1 EP 3127161A1 EP 15708232 A EP15708232 A EP 15708232A EP 3127161 A1 EP3127161 A1 EP 3127161A1
Authority
EP
European Patent Office
Prior art keywords
substrate
dielectric
trench
walls
etchant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP15708232.2A
Other languages
German (de)
English (en)
Inventor
Achim Trautmann
Christian Tobias Banzhaf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP3127161A1 publication Critical patent/EP3127161A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Definitions

  • the present invention relates to a process for producing a
  • Silicon based substrates for example a silicon carbide layer
  • Metal oxide semiconductor transistors such as trench metal oxide semiconductor field effect transistor (trench MOSFET) or trench bipolar transistors with trench MOSFET
  • insulated gate electrode (trench IGBT), using such
  • Such power semiconductors can be found in, for example
  • Microelectromechanical systems can also be used with such devices
  • Substrate further comprises a silicon dioxide layer, a silicon nitride layer or a
  • Silicon carbide layer has a hexagonal crystal structure and is n-doped.
  • An n-doped silicon carbide buffer layer is between the silicon carbide layer
  • n-drift zone n-doped silicon carbide drift zone
  • n + source is a p + terminal (p + -plug) to the p "layer is implanted such that a top of the p + -plug adjoins the top side of the n + source and p + -plug
  • the p " layer and the n + source are each structured by a recess located above a structure (trench) with which the n-drift zone is patterned.
  • the trench may be coated with a gate oxide after patterning.
  • a highly doped implantation can take place in the bottom of the trench.
  • a polysilicon gate is deposited in the trench. This results in a vertical channel region in the p " layer, which allows a higher packing density of transistors connected in parallel than in the case of transistors with a lateral channel region.
  • a method according to claim 1 for producing a dielectric field plate in a trench of a substrate is presented.
  • the method is characterized by comprising the steps of: (a)
  • the dielectric material (s) comprised by the dielectric structure is the one or more materials including the walls, the bottom, and the substrate Distinguish surface sections of the substrate, (b)
  • Stop material wherein the stop material of the or the
  • Materials of the substrate distinguishes, (c) selectively back etching a portion of the stop material with a first etchant such that a portion of the dielectric
  • a dielectric field plate can be produced in a trench of a substrate.
  • Field plate comprises at least one dielectric layer, which, however, covers only the bottom of the trench and a part of the walls of the trench which extends from the bottom of the trench.
  • the height of the sub-section of the trench wall covered by the dielectric layer is varied as a function of the specific application, for example, of the desired one
  • step (a) at least one dielectric layer or stack of dielectric layers is deposited on the substrate.
  • the dielectric layer covers at least walls and bottom of the trench, preferably also a surface of the substrate.
  • step (b) provides that at least the remaining volume of the trench is completely filled with a material serving as a temporary masking, preferably also the covered surface of the substrate is covered with the material serving as a temporary masking.
  • This material - referred to herein as stop material - differs from the material of the at least one dielectric layer. The choice of the specific stop material depends on the fact that selectively acting etchant in the sense of steps (c) to (e) are available.
  • Etch be largely inert, so only slowly etchable with the first etchant be. At the same time, there must be another (different, second) etchant for the dielectric material that will be used subsequently and not simultaneously the material (or materials) of the substrate and not the same
  • the first etchant used first is selectively caustic to the stop material and does not etch the dielectric
  • the second etchant subsequently used is selectively corrosive to the dielectric material and at least does not etch the material (or materials) of the substrate.
  • the stop material there must be another (third) etchant for the stop material that will not etch either the dielectric material or the material (or materials) of the substrate, leaving the remainder of the
  • Stop material can be removed.
  • the first etchant and the third etchant may be identical or different. It is also possible that the second etchant also does not etch the stop material.
  • Selective means that the etch rates of the stop material or the dielectric layer for the respective selectively etching etchant by at least a factor of 2,
  • the etch rate of the (or the) non-corrosive but accessible material (s) is zero.
  • the etch rate describes the etch removal per time and is expressed, for example, in nanometers per
  • it may proceed with selection by first selecting a common dielectric material for the first dielectric layer for which there is a proven etching process that does not etch the material (s) forming the walls and bottom of the trench. He then selects the stop material so that it is compared to the etching process for the dielectric
  • Material is at least substantially inert, and also an etching process for this stop material exists that neither the dielectric material nor the material or materials that form the walls and the bottom of the trench attacks.
  • Suitable etching processes for dielectrics, semiconductor materials and metals can be numerous Refer to standard works, so that is omitted at this point to further explanations.
  • the dielectric material may be composed of a material group comprising silicon dioxide (Si0 2 ), silicon nitride (Si 3 N 4 ),
  • Alumina Al 2 O 3
  • intrinsic polysilicon carbide SiC
  • thermally oxidized polysilicon SiC
  • the other dielectric material may also be selected from the group of materials comprising silicon dioxide (SiO 2 ), silicon nitride (Si 3 N), alumina (Al 2 O 3 ), intrinsic polysilicon carbide (SiC), and thermally oxidized polysilicon.
  • the further dielectric material may advantageously be part of a gate dielectric.
  • the stopping material may be selected from a group of materials including dielectrics, semiconductors or metals.
  • the trench and the remainder of the dielectric structure may be U-shaped.
  • Another aspect of the invention is to provide a substrate with a trench having walls and a bottom.
  • the substrate presented according to the invention is characterized in that the substrate has a dielectric field plate of at least one first dielectric layer, wherein the dielectric field plate only adjoins the lower portions of the walls of the trench and the bottom of the trench.
  • the substrate is obtainable in particular by the method described above.
  • the substrate may comprise a silicon carbide layer and a p-type silicon carbide layer disposed directly on the silicon carbide layer, the trench extending through the p-type silicon carbide layer into the silicon carbide layer and the dielectric field plate only to the lower sections of the walls of the trench, by the
  • Silicon carbide layer are formed, and the bottom of the trench borders.
  • a substrate having a trench coated with a dielectric material may be used for different power electronic devices.
  • MEMS microelectromechanical systems
  • application examples of power transistors include MOS transistors, such as trench MOSFET or trench IGBT.
  • MOS transistors such as trench MOSFET or trench IGBT.
  • the at least one dielectric layer serves as a field plate.
  • the arrangement of such a field plate counteracts, in particular, a compression of field lines in the transition from trench wall to trench bottom when using the substrate for a power transistor with a gate oxide.
  • the field plate also allows faster switching operations and lower power losses during switching (Umladebate), which are also beneficial to the lifetime.
  • one aspect of the invention also relates to a power transistor with the substrate provided according to the invention.
  • FIG. 1 shows an exemplary substrate with trenches
  • Figure 2 shows the exemplary substrate of Figure 1 with a dielectric layer on a surface of the substrate, walls and bottoms of the trenches;
  • FIG. 3 shows the exemplary substrate of FIG. 2 with a stop material deposited on the dielectric layer so that the trenches are filled;
  • FIG. 4 shows the exemplary substrate from FIG. 3, the stop material being selectively etched back so far that the dielectric layer is deposited on the surface of the substrate
  • Figure 5 illustrates the exemplary substrate of Figure 4 with the dielectric layer selectively etched back to expose top wall portions of the trenches;
  • FIG. 6 shows an embodiment of the present invention presented substrate, wherein the stop material is completely removed from the trench;
  • FIG. 7 shows the exemplary substrate of FIG. 1 comprising a layer stack with a further dielectric layer on which the dielectric layer is arranged and which is arranged on another further dielectric layer;
  • Figure 8 shows the exemplary substrate of Figure 7 with a stop material deposited on the dielectric layer so that the trenches are filled;
  • Figure 9 illustrates the exemplary substrate of Figure 8 with the stop material selectively etched back to the extent that the dielectric layer is exposed;
  • FIG. 10 shows the exemplary substrate from FIG. 9, wherein the dielectric layer has been selectively etched back so far that the further dielectric layer is exposed in upper wall sections of the trenches;
  • Figure 11 shows a further embodiment of the present invention
  • FIGS. 1, 2, 3, 4 and 5 show exemplary structures of a substrate before and during the production of dielectric field plates in trenches of the substrate and thus schematically visualize steps and intermediates of an embodiment of the method presented according to the invention.
  • FIG 1 shows an exemplary substrate 10 of one or more materials having two trenches 60.
  • the trenches are preferably in the shape of a "U.”
  • the trenches 60 are formed with walls 61 that are substantially perpendicular to a surface 11 of the substrate 10, and FIG a bottom 62 that is substantially parallel to the surface 11 of the substrate 10.
  • FIG. 2 shows the exemplary substrate of FIG. 1 with a dielectric structure formed as a single dielectric layer 80.
  • the dielectric layer 80 is conformally deposited. A part of the dielectric layer 80 is provided on surface portions 11 of FIG. 1
  • the dielectric material taking into account the material or materials of the substrate that are accessible to etchants, is selected such that with respect to at least one etchant, an etch rate of the dielectric material is greater than an etch rate of the material or material
  • the ratio of the etching rates may for example be equal to 2, 5, 10 or 100.
  • the dielectric material is also referred to as selectively etchable with respect to the material (or materials) of the substrate. It has a selective etchability against the material (or materials) of the
  • the material or materials form at least the surface of the substrate and the walls and the bottom of the trench. If the dielectric structure comprises different dielectric layers, then all of the dielectric layers must be selectively etchable with respect to the material (or materials) of the substrate.
  • the dielectric material may include, for example, silicon dioxide, silicon nitride, aluminum oxide, intrinsic polysilicon carbide, and thermally oxidized silicon dioxide
  • a polysilicon dielectric layer may be etched by hydrofluoric acid (HF) via a wet chemical etching process.
  • HF hydrofluoric acid
  • the etching process must not attack the materials of the substrate lying directly below the dielectric layer. Accordingly, the etchant must also be selectively corrosive in the sense outlined above with respect to these substrate materials. This is the case, for example, if this
  • Substrate areas consist of silicon carbide.
  • FIG. 3 shows the exemplary substrate of FIG. 2 with a stop material 90 that differs from the material (or materials) of the substrate and the dielectric material in the sense that the stop material takes into account the material (or materials) of the substrate and of the dielectric material is selected such that with respect to at least one other etchant, an etch rate of the stop material is greater than an etch rate of the material (or materials) of the substrate by a first factor and greater than an etch rate of the dielectric material by a second factor.
  • the first and second factors may be the same or different. Example values for the first and second factors are 2, 5, 10, and 100.
  • the stop material 90 can thus be etched selectively with the at least one other etchant that significantly etches the stop material, but the dielectric layer 80, ie, the dielectric material, and the substrate 10 is not or only slightly etched.
  • the stop material is also referred to as being selectively etchable with respect to the material (or materials) of the substrate and to the dielectric material. It has a selective etchability against the material (or materials) of the substrate and the dielectric material. If the dielectric structure comprises different dielectric layers, the stop material must be selectively etchable with respect to all these dielectric layers.
  • the stop material 90 is deposited on the dielectric layer 80.
  • a first part 91 of the stop material 90 is deposited in the trenches 60 so that they are completely filled.
  • a second part 92 of the stop material 90 is on the portion of the dielectric layer 80 disposed on the surface portions 11 of the substrate 10 adjacent to the trench and deposited on the filled trench 60.
  • the other selectively etching etchant may be a mixture of ammonium fluoride (NH 4 F) and nitric acid (HNO 3 ), which may additionally contain water.
  • the stop material may also be a metal, for example tungsten. Furthermore, the stop material of the materials silicon dioxide, silicon nitride,
  • FIG. 4 shows the exemplary substrate of FIG. 3, the second part 92 of FIG
  • Stop material 90 using the other etchant which is also referred to as the first etchant due to the etching sequence, selectively
  • FIG. 5 shows the exemplary substrate from FIG. 4, wherein the remainder 82 and the further part 81 of the dielectric layer 80 are selectively etched back using the etchant, which is also referred to as the second etchant due to the etching sequence, so that the upper sections of the walls 61 the trenches 60 are exposed. It remains in the example U-shaped part 83.
  • FIG. 6 shows an exemplary embodiment of the substrate presented according to the invention.
  • the exemplary substrate includes a silicon carbide layer in which a trench 60 is formed and a dielectric field plate 83 disposed on lower portions of the walls 61 of the trench on a bottom 62 of the trench so that top portions of the walls 61 are not separated from the trench 60
  • the substrate can be produced, for example, by also including the first part 91 of the stop material 90 of the exemplary substrate from FIG.
  • the first etchant is fully selectively etched back so that the remaining of the etching portion 83 of the dielectric layer 80 is exposed at bottoms 62 of the trenches 60. This remaining portion 83 of the dielectric layer 80 may then serve as the dielectric field plate. Instead of the first
  • Etching agent may also be a different third etchant for the removal of the remainder of the stop material 90 may be used. Then, the first etchant need only be selectively corrosive to the stop material 90 and non-corrosive to the dielectric layer 80. Above the portion 83 of the dielectric field plate may then be a
  • Gate electrode 50 are arranged.
  • FIGS. 7, 8, 9 and 10 show exemplary structures of another exemplary substrate during the production of field plates in trenches of the substrate and thus schematically visualize steps as well as intermediates of a further embodiment of the present invention
  • FIG. 7 shows the further exemplary substrate with a layer stack of two dielectric layers as part of the substrate, the walls and bottoms of the two
  • the dielectric layer 80 made of a dielectric material is in this case applied in conformity to the layer stack, which comprises a further dielectric layer 100 made of a further dielectric material, which adjoins the dielectric layer 80.
  • the layer stack comprises at least the one further dielectric layer 100, wherein the second etchant which etches the dielectric layer 80, the other dielectric layer 100 is not or only slightly etched.
  • the other additional dielectric layer 110 of the layer stack, which is separated from the dielectric layer 80 by the further dielectric layer 100, is optional. If present, the other additional dielectric layer 110 may comprise the same dielectric (dielectric material) as the dielectric
  • FIG. 8 shows the exemplary substrate of FIG. 7 with a stop material 90 deposited on the dielectric sight 80 so that the trenches 60 are completely filled.
  • a first part 91 of the stop material 90 is in the
  • Stop material 90 is deposited on the further part 81 of the dielectric layer 80 and on the filled trench 60.
  • the stop material is different from the dielectric materials in the
  • the stop material taking into account the dielectric materials, is selected such that, with respect to at least one first etchant, an etch rate of the stop material is greater than an etch rate of the dielectric material and greater than an etch rate of the different dielectric material.
  • the dielectric material is selected such that, with respect to at least one (other) second etchant, an etch rate of the dielectric material is greater than an etch rate of the different material.
  • Exemplary etch rate ratios are 2, 5, 10 and 100.
  • the stop material 90 can therefore be etched selectively with the at least one first etchant, which etches the stop material significantly, but the
  • Dielectric layer 80 and the further dielectric layer 100 does not etch or only slightly etched.
  • FIG. 9 shows the exemplary substrate of FIG. 8, wherein the stop material 90 has been selectively etched back using the second etchant such that the portion 81 of the dielectric layer 80 disposed over the surface 11 of the substrate 10 is exposed.
  • FIG. 10 shows the exemplary substrate of FIG. 9, wherein the remainder 82 and the further part 81 of the dielectric layer 80 have been selectively etched back using the first etchant, so that the further dielectric layer 100 is in upper portions of the walls 61 of the trenches 60 and above the surface 1 1 of the substrate 10 is exposed.
  • Figure 1 1 shows a further embodiment of the present invention presented substrate.
  • the further exemplary substrate comprises a
  • the further dielectric layer 100 is arranged on another further dielectric layer 110.
  • the substrate may be made, for example, by also having the first part 91 of the stop material 90 of the exemplary substrate of FIG. 10 completely etched back completely using the other selectively etching etchant, so that the etching remaining part 83 of the dielectric
  • Layer 80 is exposed on bottoms 62 of the trenches 60. This remaining portion 83 of the dielectric layer 80 may then serve as the dielectric field plate.
  • FIG. 12 shows the detail of a metal-oxide-semiconductor field-effect transistor whose gate electrodes 50 are arranged partially in trenches in the substrate 10 over remaining parts 83 of a dielectric layer which serve as dielectric field plates 83.
  • the substrate comprises a drain electrode 5, a wafer substrate 15 arranged thereon, an n-doped epitaxial silicon carbide drift zone 12 arranged on the wafer substrate 15, a p-doped silicon carbide layer 20 arranged on the silicon carbide drift zone 12 and an n-doped silicon carbide layer 30 (n + source).
  • the sidewalls of the trenches comprise a portion of the p-type silicon carbide layer 20 and a portion of the n-type silicon carbide layer 30.
  • a remaining portion 83 of the dielectric layer as a field plate is formed on lower portions of the walls and on the bottom a stack of dielectric
  • Silicon carbide layer 20 is a vertical channel region 25.
  • the p + plugs 40 are implanted sunk in the substrate surface areas between adjacent trenches in the p-type silicon carbide layer 20 so that they extend partially into the silicon carbide drift zone 12.
  • a source electrode 35 is connected to the p + -plugs 40.
  • the field plate itself may be formed as a stack of dielectric layers.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Element Separation (AREA)

Abstract

Des substrats comportant une tranchée dotée de parois et d'un fond sont de plus en plus employés pour des composants standard. Un substrat est caractérisé en ce qu'il comprend une plaque de champ diélectrique (83) constituée d'au moins une première couche diélectrique qui jouxte uniquement les segments inférieurs des parois ainsi que le fond de la tranchée (60). L'utilisation de ce substrat dans des transistors de puissance permet de réduire les capacités parasites.
EP15708232.2A 2014-04-03 2015-03-09 Procédé de formation d'une plaque de champ diélectrique dans une tranchée d'un substrat, substrat correspondant et transistor de puissance Withdrawn EP3127161A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102014206361.2A DE102014206361A1 (de) 2014-04-03 2014-04-03 Verfahren zur Herstellung einer dielektrischen Feldplatte in einem Graben eines Substrats, nach dem Verfahren erhältliches Substrat und Leistungstransistor mit einem solchen Substrat
PCT/EP2015/054821 WO2015150023A1 (fr) 2014-04-03 2015-03-09 Procédé de formation d'une plaque de champ diélectrique dans une tranchée d'un substrat, substrat correspondant et transistor de puissance

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CN110767740B (zh) * 2018-07-27 2021-10-15 无锡华润上华科技有限公司 半导体器件及其制造方法
US10712500B2 (en) * 2018-10-17 2020-07-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method of the same
CN112993006B (zh) * 2019-12-12 2022-08-12 珠海格力电器股份有限公司 一种终端结构、其制作方法及电子器件

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DE102014206361A1 (de) 2015-10-08
US9972690B2 (en) 2018-05-15
JP2017516298A (ja) 2017-06-15
US20170117369A1 (en) 2017-04-27

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