EP2617132B1 - Circuit for capacitive touch applications - Google Patents

Circuit for capacitive touch applications Download PDF

Info

Publication number
EP2617132B1
EP2617132B1 EP11705496.5A EP11705496A EP2617132B1 EP 2617132 B1 EP2617132 B1 EP 2617132B1 EP 11705496 A EP11705496 A EP 11705496A EP 2617132 B1 EP2617132 B1 EP 2617132B1
Authority
EP
European Patent Office
Prior art keywords
adc
cds
capacitor
switch
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP11705496.5A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP2617132A1 (en
Inventor
Hussein Ballan
Olivier Nys
Norman Chappatte
François VUADENS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Silicon SA
Original Assignee
Advanced Silicon SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Silicon SA filed Critical Advanced Silicon SA
Publication of EP2617132A1 publication Critical patent/EP2617132A1/en
Application granted granted Critical
Publication of EP2617132B1 publication Critical patent/EP2617132B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/94—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the way in which the control signals are generated
    • H03K17/96—Touch switches
    • H03K17/962—Capacitive touch switches
    • H03K17/9622—Capacitive touch switches using a plurality of detectors, e.g. keyboard
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/1205—Multiplexed conversion systems
    • H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/162—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in a single stage, i.e. recirculation type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters
    • H03M1/168—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters and delivering the same number of bits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
    • H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/94—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00 characterised by the way in which the control signal is generated
    • H03K2217/96—Touch switches
    • H03K2217/9607—Capacitive touch switches
    • H03K2217/960735—Capacitive touch switches characterised by circuit details

Definitions

  • the present invention concerns a circuit with digital output, typically used in capacitive touch applications.
  • Capacitive sensors are used in various application fields in which object presence detections are involved, such as, but not limited to, touch pads, touch panels, touch screens or projective capacitive displays.
  • FIG. 1 describes a possible capacitive sense measurement circuit 10.
  • Each sensing capacitor C sens is connected to the input of the first block 1 - a charge integrator - of the acquisition chain 10. Since the non-inverting input terminal of the charge integrator amplifier is kept to a constant voltage, there is a virtual ground at the inverting input terminal of this amplifier, i.e. also the input voltage of the charge integrator amplifier is kept constant. The charge sensing against a virtual ground allows power supplies noise immunity.
  • a reset phase forces the output voltage V int of the charge integrator 1 to a well defined initialization value. After the reset phase, the initial value of the output voltage V int , i.e. V int_init , of the charge integrator 1 is filtered and sampled by the remaining blocks of the chain 10.
  • V int_final of the charge integrator 1 V int _ init ⁇ Q C int where Q is the transferred charge. Any change in the charges stored into the sensing capacitor C sens , resulting for example from a capacitance change, will be seen as a voltage change at the output of the integrator V int .
  • the second block 2' shown in Figure 1 is a low pass filter. Its purpose is to remove high frequency components from the Vint without significantly attenuating it.
  • a purpose of this low-pass filter is to limit the bandwidth of the signal Vint in function of the sampling rate of the subsequent sampling block 3, taking into account the Nyquist relation. Therefore, the cut-off frequency of this low pass filter, i.e., the point in the filter response where the unaffected low frequency band and the high frequency band meet, for example as defined by a 3 dB corner, is lower than the Nyquist frequency of the sampling block 3.
  • the capacitive sense measurement circuit 10 comprises as a third block 2" a Correlated Double Sampling (CDS) block: its function is to sample twice its input, once in a known condition and once in an unknown condition, for removing an undesired offset or noise.
  • the value measured from the known condition e.g. a reset state, is then subtracted from the unknown condition, e.g. a charge transferring, to generate a differential signal, output of this block 2".
  • CDS Correlated Double Sampling
  • the fourth block 3 is a sampler and holder (S/H). It is required to store the output of the CDS at the end of the charge transfer phase and keep it available for the whole duration of the A/D conversion 4 in order to allow a new charge to be sampled while the current one is being converted into digital by the last block, the ADC 4 itself.
  • S/H sampler and holder
  • the circuit proposed in Figure 1 contains several stages, each of which generates noise, requires area on a silicon slice and is supplied by a current. In a touch panel comprising a large amount of sensing capacitors, the required surface and power consumption become problematic.
  • US5543591 (Synaptics) describes a device in which the charge sensing is performed by the current integration against power supplies. This feature makes the device sensitive to the power supply noise. Even if the low frequency noise is cancelled by a double polarity averaging, the noise rejection efficiency is dependent on the timing sharpness.
  • Four input lines or channels, each line or channel comprising a current integration device, a filter and a sampler and holder (S/H), are multiplexed into one channel which is the input of an analog to digital converter (ADC) not specified.
  • ADC analog to digital converter
  • the ADC sharing between four channels limits the conversion rate and makes worse the spatial non-linearity, i.e. the non-linearity on the difference between adjacent channels.
  • the described device is moreover integrated in a touch panel in which all row electrodes and all row column electrodes are sensed simultaneously.
  • US5790107 (Logitech/Elan) describes a device in which the charge sensing is performed by a frequency measurement between a reference oscillator and an oscillator comprising a sensing capacitor. A voltage signal representing the frequency measurement is then mixed with the voltage reference and the output of the mixer is sent to a low pass filter (LPF) realized with a flip-flop and then used for driving a digital counter, without using ADC.
  • LPF low pass filter
  • the proposed circuit does not perform a low frequency noise cancellation.
  • the charge sensing is sensitive to the reference oscillator accuracy.
  • US7312616 (Cypress) concerns a successive approximated capacitance measurement circuit in which the charge sensing is performed by a measurement of an effective resistor, generated by charging and discharging, with a current source tied to a switch, a sensing capacitor at high frequency (R eff proportional to (f switch ⁇ C sensing ) -1 ).
  • the circuit comprises also an adjustable LPF for voltage averaging. The LPF output voltage is then compared to a voltage reference and sent to a Successive Approximation ADC (SAC).
  • SAC Successive Approximation ADC
  • the chain contains neither CDS nor S/H. Again, the proposed circuit does not perform a low frequency noise cancellation.
  • US7656394 (Apple) concerns a device used in multi-touch panels wherein the charge sensing is performed by sequential charge sharing between a sensing capacitor and an integration capacitor by using three switches and a voltage source. The number of required phases depends on the desired output voltage precision. Before the ADC conversion, the panel image without touches, stored in a memory from a calibration phase, is removed from the output voltage. The ADC topology is not defined and there is neither LPF nor CDS. Charge sensors along with the ADC can be shared or dedicated. Again, the proposed device does not perform a low frequency noise cancellation.
  • US7663607 (Apple) describes a touch panel wherein the charge sensing is performed by charge integration against virtual ground. The device then has a good power supply noise immunity. However a number N of charge sensing channels is multiplexed into only one ADC channel input, whose topology is not defined. Since the use of one ADC for N channels, the conversion rate is low compared to other solutions. Moreover also in this case there is not a low frequency noise cancellation.
  • EP2224596 (General Electric Company) describes a two-gains system for medical applications comprising both "low-gain” (e.g. mammography) and “high-gain” (e.g. fluoroscopy systems) measurements.
  • the initial charge is distributed to two capacitors of the integrator during the "low-gain” measurement.
  • the "high-gain” measurement is performed, during which one capacitor is removed from the feedback loop by coupling it to a reference voltage and the charge is redistributed to the remaining capacitor.
  • US7053806 (General Electric Company) concerns a system and method for calibration of autoranging architectures, comprising the segmentation of a desired relationship between DAC output values and desired ADC input values into a plurality of segments. Each segment includes an offset value and a gain value. It comprises a Low Pass Filter composed by a buffer, a tunable resistor and two tunable capacitors for enabling the Low Pass Filter to be dynamically tuned to the bandwidth of the channel during the A/D conversion.
  • US20080158175 (Apple) describes a circuit for a touch-screen comprising a summing circuit commanded by a look-up table by means of a DAC, an amplifier and a mixer.
  • US20030205660 (Sharp Corporation) describes a charge amount detection circuit for two-dimensional image sensor comprising a multiplexer
  • US 2006/0139198 A1 discloses a signal processing circuit, whereby the signal to be processed is provided by an imaging sensor and the data acquisition chain comprises an integrator, a low-pass filter, a correlating double-sampling amplifier and an A/D converter, all connected in series and forming a signal processing chain.
  • the advantages of the circuit include in particular the possibility of reducing the number of required blocks, by combining several functions within the same block, i.e. by integrating blocks. This results in a reduction of total surface and of power consumption.
  • the input capacitor of the CDS block is combined with a serial resistor for making the Low Pass Filter LPF.
  • a serial resistor for making the Low Pass Filter LPF.
  • the resistance value of this serial resistor allows, along with the capacitance value of the input capacitor, to determine the cut-off frequency of the filtering function performed by the merged block LPF+CDS, depending on the sampling rate of the subsequent sampling block 3 in order to satisfy the Nyquist criteria.
  • one buffer can be avoided, together with its power consumption part and its noise contribution.
  • the LPF and the CDS blocks are integrated in a single block.
  • the expression "integrate two or plus blocks in a single block” means that at least one circuit element is shared between the integrated blocks, and performs a function in each of those blocks. Thus, it is not possible to isolate each block. Therefore, since at least one element is shared between two blocks, the number of elements of the integrated block is lower than the number of elements that would be required in order to build two (or more) equivalent separated blocks without any shared element, allowing to reduce the noise level, the current consumption and the required area on a silicon slice.
  • the ADC of the proposed chain is a switched capacitor ADC, for example a multistage ADC, comprising a first stage and further stages.
  • the first stage can contain a Successive Approximation Register (SAR) and a DAC in feedback.
  • SAR Successive Approximation Register
  • the S/H block and this first stage are integrated in a single block, i.e. an amplifier is shared by the S/H block and the first stage of a switched capacitor ADC.
  • the further stages can comprise a pipeline ADC, an algorithmic ADC or a two or more cascaded component, each component being an algorithmic ADC.
  • the first stage of the ADC including the integrated S/H, can be integrated in a single block along with the LPF+CDS.
  • a capacitor is shared between the LPF+CDS and S/H+ADC blocks, performing the function of the feedback capacitor of the LPF+CDS block and the input capacitor of the S/H+ADC block.
  • the S/H+ADC block comprises an amplifier, not only the mentioned capacitor, performing the function of the feedback capacitor of the LPF+CDS block and the input capacitor of the S/H+ADC block, but also an amplifier, integrating the function of the amplifiers of the LPF+CDS and S/H+ADC blocks, are shared between the two blocks.
  • the DAC's in the feedback loop of the first stage can be realized by selecting tabs from a common resistive divider in order to have a good spatial non-linearity.
  • the resolution of the ADC is improved by generating and evaluating an error or residue, which is defined as the amplification of the difference between the input signal of the LPF+CDS block and its approximation generated by the SAR and the DAC in feedback.
  • the proposed circuit allows the optimization of the CSA and/or the LPF+CDS by offset variation.
  • a capacitive touch device for example a touch panel, comprises an array of sensing capacitors. If an object with good dielectric properties such as a finger is approaching the touch panel, the capacitance value of these capacitors can be changed.
  • the whole array is read out by a capacitive sensor integrated circuit (CSIC) in medium speed, typically 100-1000 fps.
  • CSIC capacitive sensor integrated circuit
  • Figure 2 shows a view of a capacitive touch device with a CSIC. It comprises a first number N of rows of sensing capacitors and a second number M of columns of sensing capacitors.
  • the sensing capacitors are all arranged in a matrix form, like pixels in an image.
  • the capacitive touch device comprises a capacitive sensor array 200 of dimensions N ⁇ M.
  • a voltage 11 of amplitude A is applied as input signal across each row of the sensing capacitors.
  • each row is addressed sequentially by the input signal 11 with a row scan rate 1/N. While a row is being addressed, all M sensors of the selected row are analysed in parallel by M sensing circuits of the invention, during the row scan period.
  • the blocks Charge Sense Amplifiers scale with an appropriate range a detected signal for each column or channel of the capacitive touch device. In other words the charge sense amplification is performed by a dedicated circuitry within each channel of the CSIC, so that all the capacitive sensors of a row are sampled in parallel.
  • Figure 3A shows a CSIC with an ADC in each channel, as for the CSA.
  • the reference 300 indicates a digital interface used for the detection of the change of the sensing capacitor values within each scan.
  • the CSIC illustrated in Figure 3C uses an ADC per group of CSA channels, each group having a multiplexer 500.
  • the CSIC has an analog output which only includes one CSA per channel and a high frequency analog multiplexer 400, the output of which is fed outside the CSIC to a fast and external ADC.
  • the present invention concerns the implementation scheme of an electronic architecture per channel compliant for all the different configurations shown in Figures 3A to 3D .
  • the embodiment of Figure 3A is particularly suited for a parallel sensing capability and fast digital processing.
  • the first block of the circuit according to the invention is the charge sense amplifier shown in Figure 4 : it comprises a low noise inverting sense amplifier that uses the capacitance of the sensor C sens in the gain loop of the amplifier.
  • the sensing capacitor C sens is the equivalent capacitor present between the terminal of the selected row and the terminal of the column under acquisition, as pointed out in the upper part of Figure 4 .
  • the output voltage V csa is then proportional to the scan input voltage amplitude ( V high - V low ).
  • the voltage acquisition cycle sequence of the CSA stage is shown in Figure 5A to 5C .
  • the input voltage V C of the inverting terminal of the CSA connected to the feedback capacitor C int , is initialized to a reference voltage value V b
  • the CSA output is initialized to a reference voltage value V init , by closing the switches S2 and opening switch S1.
  • the noise integration phase can start while an ADC input stage, which belongs to the circuit as it will be shown, is being initialized. This is achieved by closing the switch S1 and opening switches S2. During this phase the scan voltage is maintained high.
  • the column voltage of the sense capacitor terminal V C is maintained to the virtual ground voltage value V b while the output voltage of the CSA V CSA is maintained to the initialization voltage value V init .
  • the voltage sampling is initiated by switching the input voltage from V high to V low .
  • the output voltage of the CSA V CSA will amplify the negative voltage difference of the input row signal proportionally to the ratio between the sense capacitor C sens and the feedback capacitor C int .
  • the value of this negative voltage difference is ⁇ V high ⁇ V low C sens C int
  • this amplified signal is being filtered and processed by the following stages.
  • the left side of Figure 6 shows LPF (Low Pass Filter) 2' and CDS (Correlated Double Sampling) 2" blocks.
  • these two blocks can be integrated in a single block 2 shown in the right part of the Figure 6 , by using directly the input capacitor of the CDS block C CDS and a supplementary serial resistor R LPF+CDS in order to perform the functions of a RC filter.
  • the value of the resistor R LPF+CDS is adapted to the value of the input capacitor C CDS in order to limit the bandwidth of the input signal of the block 2 in function of the sampling rate of the subsequent sampling block, taking into account the Nyquist relation.
  • the integrated block LPF+CDS 2 moreover has only one capacitor (C CDS ) instead of the two capacitors (C LPF and C CDS ) required respectively by the two blocks LPF 2' and CDS 2".
  • the cut off frequency is selected and can be varied by the nominal value of the serial resistor R LPF+CDS .
  • this RC filtering stage can be combined with additional low-pass and/or band-pass filtering means, for example in multi-stage filter.
  • additional low-pass and/or band-pass filtering means for example in multi-stage filter.
  • the use of a single stage low pass filter that comprises only one resistor and one capacitor is however preferred since it reduces the number of components in each channel.
  • the circuit according to the present invention is simpler than non merged solutions, for example the solution illustrated in Figure 1 , because two or more blocks of the circuit shown in Figure 1 are integrated into a single block, i.e. at least one circuit element is shared between the integrated blocks, and performs a function in each of those blocks. Thus, it is not possible to isolate each block. Therefore the number of elements of the integrated block is lower than the number of elements that would be required in order to build two (or more) equivalent separated blocks without any shared element, allowing to reduce the noise level, the current consumption and the required area on a silicon slice.
  • this sampler and holder i.e. the block 3 of Figure 1
  • an ADC 4 can also be integrated. This is in particular possible for switched capacitor implementation of ADC's such as successive approximation, two-steps or multi-step, pipeline and algorithm ADC's.
  • S/H+ADC means the integration of the S/H block 3 of Figure 1 with a switched capacitor ADC, for example the integration of a S/H block with the first stage of a multistage ADC comprising a successive approximation register SAR, i.e. a SAC, and a feedback digital to analog converter DAC.
  • SAR successive approximation register
  • DAC feedback digital to analog converter DAC
  • the analog subtraction between the input signal V inADc and the signal V DAC output by the DAC can be obtained, for example, by a switched capacitor arrangement, although other techniques are also possible.
  • the input capacitor C in is pre-charged to V inADC during a first phase in which the switches 1 are closed, and the switch 2 is open.
  • the error signal or residue will take value V DAC - V inADC .
  • the voltage step applied on bottom electrode of C in will appear attenuated by a factor C in /(C p +C in ), slightly below 1, due to charge redistribution between C in and C p , which can be a problem in the case wherein the residue must be evaluated precisely in the next stage, if C p is not precisely known.
  • FIG. 8 shows another example of switched-capacitor analogue difference input stage, suitable for the present invention.
  • the top electrode 85 of the input capacitor C in is tied to the virtual ground input of an amplifier.
  • the circuit is not sensitive to the value of parasitic capacitor, as the voltage across C p is constant.
  • the input capacitor C in is pre-charged to V inADC while the feedback capacitor C fb is discharged.
  • first the feedback switch 1 shorting C fb opens. From there on the total charge on virtual ground must be conserved.
  • the bottom electrode of C in is switched by 2 from V inADC to V DAC .
  • the capacitor C in is charged to V DAC , and the charge variation C in ⁇ (V DAC - V inADC ) on the input capacitor C in will be taken up by the feedback capacitor C fb .
  • the output voltage of the amplifier will thus vary in the opposite direction and with a gain defined by the capacitor ratio C in /C fb .
  • the solution illustrated in Figure 8 can for example be used within a successive approximation ADC as illustrated in Figure 9 , if the residue must be amplified and outputted for compensation within a next ADC stage.
  • the low pass filter LPF the correlated double sampler CDS
  • the sampler and holder S/H the first stage of a switched capacitors ADC, e.g a successive approximation ADC (SAC).
  • SAC successive approximation ADC
  • a capacitor is shared between the LPF+CDS and S/H+ADC blocks, performing the function of the feedback capacitor of the LPF+CDS block and the input capacitor of the S/H+ADC block.
  • the ADC input stage is based on capacitive coupling between two voltages, VinADC and VDAC, towards a high impedance node 85 as illustrated in Figure 7 .
  • Figure 10 shows a LPF+ CDS block 2 followed by a S/H+ADC 34, e.g. a sampling ADC stage.
  • these two blocks 2 and 34 are separates, i.e. are not integrated in a single block.
  • the different phases for the operations of circuit of Figure 10 illustrated in Figure 12 , are at least three:
  • the numbers 1, 2, 3 and 4 associated to the switches in Figures 10 , 11 , 13 , 15 , 16 , 18 , 20 and 22 indicate that the corresponding switches are closed during the phase with the same number and are opened in the other phases. If two numbers are associated with the same switch, for example "1,2", they indicate that the corresponding switch is closed during phases with the first and second number (in this case during phases 1 and 2) and it is opened at the end of the phase with the second number (in this case at the end of the phase 2).
  • the LPF+CDS block 2 is reset.
  • the input capacitor Cin_cds of Figure 10 corresponding to the capacitor C CDS of Figure 6 , is pre-charged to a voltage Vin_cds1 and the feedback capacitor Cfb_cds is pre-charged to an initialization voltage Vinit_cds.
  • the initialization voltage Vinit_cds in one embodiment can correspond to the analog ground.
  • the block S/H+ADC 34 does not play any role during the initialisation phase 1.
  • phase 2 the reset switches 1 of the LPF+CDS are opened and its switch 2 is closed, so that the total charge on the virtual ground node Vout_cds is kept constant. This total charge corresponds to the sum of the charges on the capacitor Cin_cds and the charges on the capacitor Cfb_cds.
  • Vout_cds Vinit _ cds ⁇ Cin _ cds Cfb _ cds Vin _ cds 2 ⁇ Vin _ cds 1
  • Vout_cds Vin_adc.
  • Vin _ adc Vinit _ cds ⁇ Cin _ cds Cfb _ cds Vin _ cds 2 ⁇ Vin _ cds 1
  • the error voltage Verror i.e. the voltage at the node 85 at the right of the capacitor Cin_adc
  • Verror the voltage at the node 85 at the right of the capacitor Cin_adc
  • the two blocks LPF+CDS 2 and S/H+ADC 34 can be advantageously integrated in a single block as illustrated in Figure 11 .
  • the phases 1 and 2 are identical to the solution of Figure 10 .
  • phase 1 or initialisation phase I During the phase 1 or initialisation phase I:
  • Vin_adc indicates the voltage to be converted, which is proportional to the difference between Vin_cds2 and Vin_cds1.
  • the amplifier 8 in open loop now can be used as the first pre-amplifier stage for the comparator 9, with the advantages that the offset of this first stage will then be compensated and that the gain of the amplifier 8 will be achieved in front of the comparator 9, reducing the sensitivity to its offset.
  • One advantage of the structure of Figure 11 is that the copy of the voltage from feedback capacitor Cfb of the LPF+CDS block to input capacitor Cin_adc of the S/H+ADC block is avoided, and thus also the power consumption required for this operation as well as the corresponding noise involved by this operation.
  • the integration of the low-pass filter LPF, the correlated double sampler CDS, the sample and holder S/H and the first stage of an ADC, for example a SAC, in a single block allows in this case to share the capacitor Cfb of Figure 11 between the two blocks LPF+CDS and S/H+ADC of Figure 10 , avoiding the use of two capacitors Cfb_cds and Cin_adc of Figure 10 and then reducing the number of elements of the integrated block 23 compared to the number of elements required in order to build the two separated blocks of Figure 10 without any shared element, allowing to reduce the noise level, the current consumption and the required area on a silicon slice.
  • the circuit of Figure 11 employs also a reduced number of switches.
  • the charge reading phase (CR) during which two samples are taken from the CSA output corresponds to phases 1 and 2.
  • the input capacitor Cin of Figure 11 is tied to the amplifier 8.
  • the A/D conversion A/D C is inserted between two charge reading phases CR and can limit the frequency at which the different row of the multi-touch device can be read, i.e. the line frequency.
  • two switched capacitor sub-blocks A, B, shown in Figure 13 operated in tandem can be advantageously used.
  • the expression "operated in tandem” means that one sub-block performs the charge reading while the other performs the A/D conversion.
  • Figure 14 shows the different phases for the operations of the circuit of Figure 13 .
  • the filter of Figure 13 comprising the resistor R LPF+CDS and the capacitor Cin, does not need to be duplicated for the two switched capacitor sub-blocks A, B because it is only connected to one sub-block at a time - either the upper (A) or the lower one (B) - the one which is in charge reading mode.
  • the comparator 9, which performs the function of a coarse ADC, and the DAC in the feedback path do not need to be duplicated because they are only used by the switched capacitor sub-block that is in A/D conversion mode.
  • more than two sub-blocks operated in tandem can be used. Two sub-blocks are suitable if the charge reading and A/D conversion have the same duration. If A/D conversion phase is N times longer than charge reading phase, then N+1 sub-blocks operated in tandem can be used, one being in the charge reading mode while the N others performing ADC conversion, the roles of the sub-blocks being cyclically exchanged.
  • the ADC input stage is based on capacitive coupling between VinADC and VDAC towards an inverting amplifier as illustrated in Figure 8 .
  • the S/H+ADC block comprises an amplifier, not only a capacitor, performing the function of the feedback capacitor of the LPF+CDS block and the input capacitor of the S/H+ADC block, but also an amplifier, integrating the function of the amplifiers of the LPF+CDS and S/H+ADC blocks, are shared between the two blocks.
  • FIG. 15 shows a LPF+ CDS 2 followed by a S/H+ADC 34, i.e. a sampling ADC stage. These two blocks 2 and 34 then are not integrated in a same block.
  • This circuit needs at least three operation phases. The operations of LPF+CDS block 2 during the phases 1 and 2 are identical as for the circuit of Figure 10 .
  • the LPF+CDS output voltage Vout_cds is copied to the input capacitor Cin_adc of the S/H+ADC 34, and the feedback capacitor Cfb_adc of S/H+ADC is initialized to Vinit_residue by closing the switch 2 at its right side.
  • the switch 2 in the feedback path of the amplifier of the S/H+ADC block is opened, and the input capacitor Cin_adc is switched to Vdac while the Cfb_adc capacitor is switched in feedback of the amplifier of the block S/H+ADC, both operations being performed by closing the switches 3.
  • Vin_adc is equal to Vout_cds.
  • the two blocks LPF+CDS 2 and S/H+ADC 34 can be advantageously integrated in a single block as illustrated in Figure 16 , wherein Cin plays the role of Cin_cds of Figure 15 , Cfb the role of both Cfb_cds and Cin_adc, and Cresidue plays the role of Cfb_adc. Since Cfb plays the role of both Cfb_cds and Cin_adc, and since the integrated block 23 contains only one amplifier instead of the two amplifiers of Figure 15 , the number of elements of the integrated block 23 is lower than the number of elements that are required for the separated blocks 2 and 34, allowing to reduce the noise level, the current consumption and the required area on a silicon slice.
  • phase 1 i.e., at phase 2 illustrated in Figure 17B , the switch 1 between the input and the output of the amplifier is opened, which corresponds to the first sampling of the correlated double sampling, and consequently the total charges on Cin, Cfb and Cresidue are kept constant.
  • Cfb is switched in feedback of the amplifier, while the voltage on Cin gradually changes from Vin_cds1 to Vin_cds2.
  • the voltage on Cresidue remains unchanged, set to Vinit_residue, so that the charge on Cresidue remains constant.
  • Vfb Vinit _ cds ⁇ Cin Cfb Vin _ cds 2 ⁇ Vin _ cds 1
  • the residue Vresidue is thus amplified by the ratio Cfb/Cresidue and can be used to refine the signal estimation within the same stage by successive approximation or algorithmic ADC conversion, or within a next ADC stage in case of pipeline ADC.
  • Vin_adc can be compared with different levels, simultaneously or sequentially.
  • the quantization is performed on the residue Vresidue, and the result used to update the successive approximation register and the feedback DAC.
  • a first coarse quantization is performed before generating the residue, in order to fasten the extraction of the first bits by reducing slew rate requirements.
  • the first quantization can then be performed based on Vfb while the fine quantization can be performed on Vresidue.
  • the first quantization is performed by comparing Vfb simultaneously with different reference levels (flash ADC conversion), it can occur directly at the end of phase 2. However, if the coarse quantization is performed in several steps (not instantaneous), it cannot be performed during phase 2 because the quantization may only be performed once all the charges have been integrated.
  • a possible embodiment splits the A/D conversion in two phases, i.e. a coarse quantization and a fine quantization or residue amplification, leading to a 4-phases circuit, as illustrated in Figures 18 and 19.
  • Figure 19 shows the four different phases for the operations of the circuit of Figure 18 .
  • the difference with the circuit of Figure 16 is that, after Cin has been disconnected, Cfb still remains in feedback during phase 3 for coarse quantization. Cresidue is put in feedback and Cfb forced to Vdac only in phase 4, which corresponds to phase 3 of the circuit of Figure 16 .
  • the circuit of Figure 18 is thus more general because the phase 3 of coarse quantization may optionally be avoided, leading than to the case of the circuit of Figure 16 . Also the successive approximation register can be reduced to a simple latch in case of a pipeline stage. In this case, Vfb is quantized in the phase 3 and the result latched within phase 4 for DAC conversion, residue generation and amplification.
  • two switched capacitor sub-blocks C and D operated in tandem can be used, such that one performs the charge reading while the other performs the A/D conversion, as illustrated in Figures 20 and 21 .
  • the filter comprising the resistor R LPF+CDS and the capacitor Cin does not need to be duplicated because it is only connected to one switched capacitor sub-block at a time, either the upper or the lower one, that one which is in charge reading mode.
  • the comparator or coarse ADC, successive approximation register and the DAC in the feedback path do not need to be duplicated because they are only used by the sub-clock that is in A/D conversion.
  • Figure 22 illustrates one possible embodiment of a circuit comprising a charge sensing amplifier CSA 1, a single block 23 which integrated the low pass filter LPF, the correlated double sampler CDS, the sampler and holder S/H and the first stage (SAC) of a multi-stage ADC.
  • the single block 23 is the same of Figure 18 .
  • the solution shown in Figure 22 can be implemented for each channel of a multi touch device: in this manner, it is possible to achieve a good conversion speed for the considered touch applications (up to 100 KHz) with a relatively high resolution in each channel (up to 16-bit) and a low differential and spatial non-linearity.
  • the differential non-linearity is defined as a measure describing the deviation between two analog values corresponding to adjacent input digital values.
  • the ADC - which is present in each channel - is formed by a first stage, which is integrated with the LPF, the CDS and the S/H in the block 23, followed by a cascade of M-stages converting the residue of the previous stages.
  • the circuit of the invention can include a multistage ADC or multistep ADC in which the conversion is performed in several steps. It is made of a cascade of several stages 630. In each stage, the input signal is sampled and converted into a digital signal by a coarse ADC (which can also be reduced to a simple comparator). The obtained code is then reconverted back into analogue by a digital to analog converter D/A and the DAC output is subtracted from the input signal. This difference, which is an analogue representation of the quantization error performed in the current stage, is then eventually amplified and finally stored in a capacitor by a sample and hold circuit in order to produce a residue signal which can be further processed.
  • a multistage ADC or multistep ADC in which the conversion is performed in several steps. It is made of a cascade of several stages 630. In each stage, the input signal is sampled and converted into a digital signal by a coarse ADC (which can also be reduced to a simple comparator). The obtained code is then reconverted back into analogue by
  • This residue signal is then fed to the next stage so that this one can give a digital estimate of the error performed in the previous stage.
  • the quantization error related to each stage may then be compensated for by feeding the residue to the next stage, excepted for the last stage.
  • the residue of the last stage is thus an image of the overall conversion error.
  • the output codes from the different stages are then delayed in order to compensate for the propagation time across the cascade, and combined together in an output combinatory 650 in order to obtain a high resolution output code in which all the internal residue errors are compensated, at least ideally.
  • the combination consists into a properly weighted sum of the outputs of the codes from all the stages.
  • the number of bits of ADC and DAC within each stage can be different and the quantization within each stage can also be reduced to a simple comparison.
  • each step of the conversion algorithm is performed by a dedicated stage. In this case, it is called pipeline ADC. But other possibilities exist, and are also enclosed in the scope of the invention.
  • the converter When the different steps are performed by the same analogue stage, sequentially in time, the converter is called an algorithmic ADC, an example being illustrated in Figure 24 .
  • the structure is similar to that of a pipeline stage except that a multiplexer 800 is added at the input of the block so that the effective input of the block is either the real input of the block when the input signal is sampled, or the residue of the stage calculated at the previous step, in order to refine the signal estimation.
  • the different bits or codes obtained successively in the different steps must then be accumulated properly with proper weights in a digital accumulator 502. As these weights generally correspond to powers of 2, the corresponding digital multiplications generally reduce to simple shifts. In fact, the multiplication by the weight in front of the accumulation loop is generally replaced by a multiplication within the accumulation loop.
  • the multiplication factor in this case corresponds to the ratio of weights of two successive codes.
  • the reference 500 in Figure 24 designates the analog part of the algorithmic ADC.
  • each stage being an algorithmic ADC ( Figure 25 ).
  • each stage performs several steps of the conversion and then passes the residue to the next stage for processing of the next steps.
  • a similar process occurs in the digital part.
  • a first accumulator accumulates the bits for the first stage and then transfers the result to the accumulator of the second stage, and so on.
  • the spatial and differential non-linearity can be reduced if N successive approximation ADCs of N channels are in parallel.
  • the feedback DAC in each channel is realized by selecting tabs from a resistive divider or ladder 127 according to Figure 26 . Each channel thus would include its own resistive divider or ladder 127 and multiplexer 128.
  • the resistive DAC in feedback of each DAC has a thermometric principle and thus intrinsically guarantees a monotonic conversion and a very low differential non-linearity.
  • the integral linearity i.e. the measure of the ADC deviation from an ideal behaviour, is not improved by the thermometric principle, it only depends on the matching between resistors, in particular on the matching between resistors in the upper part of the ladder 127 with respect to those in the lower part.
  • the integral non-linearity is generally not a problem because it is a very smooth non linearity, without discontinuities, and thus its effect onto an image in the application is simply to very gradually change the grey scale.
  • a common resistive divider is shared between all channels in order to solve this problem of spatial non-linearity.
  • the corresponding taps of the resistive ladders 127 different channels are interconnected by a low resistance paths 137, so that the same reference levels are seen by all the channels, and in particular by adjacent channels. Doing so, not only the non-linearity of the resistive dividers or ladders 127 of the different channels is averaged but, importantly, the integral non-linearity is the same for all the channels. Therefore the readout system exhibits excellent spatial linearity.
  • a possible embodiment of an ADC suitable for the circuit object of the invention is the combination of the circuit described in Figure 28 with M-stages of cascaded algorithmic ADCs in pipeline described in Figure 22 , as shown in Figures 29a and 29b .
  • Figures 29a and 29b illustrate a row of fast ADC channels operating in parallel.
  • the first stage 23 of each ADC channel is a successive approximation.
  • the feedback DAC within each channel is a multiplexer selecting tabs from a resistive divider or ladder 127 which is common to all the channels for cancelling the effect of the mismatch between resistors within the different channels onto the spatial non-linearity.
  • the successive approximation ADC within the first stage can generate a residue signals which can be exploited by one or several next ADC stages to improve further the resolution, each of the next stage quantifying the residue of the previous stage (500) and adding the corresponding value to the code produced by the previous stage in order to compensate its approximation (502).
  • the advantage of this structure is that the non-linearity of each channel is basically dominated by that one of the resistive divider 127 (feedback path of the first stage), which should be common to all the channels. By this fact, the spatial non-linearity should be significantly improved.
  • the ADC in each channel considered as a whole can be a medium speed (conversion speed corresponding to the line frequency, of the order of 100 KHz typically) and relatively high resolution ADC (the number of bits being up to 16 bits).
  • the DAC in the feedback path of the successive approximation ADC can be a resistive DAC realized by selecting tabs from a resistive divider 127 which is shared by the ADC's of all channels.
  • the circuit comprises means for optimising the range of the charge integrator CSA and/or the correlated double sampler CDS integrated with the low pass filter LPF by offset variation, in order to compensate offsets generated by parasitic charges and then to detect very small charge levels, either positive or negative, even in the presence of these parasitic offsets.
  • a small offset compensation i.e. a compensation enabling to detect very small charge levels, depending on the application, even in the presence of random parasitic offsets, consists of generating an initialisation output voltage of the CSA and/or the LPF+CDS at a medium level, which is between the maximum and minimum reference voltage of the ACD in order to compensate from parasitic charges of opposite signs.
  • this initialisation is achieved by using a DAC 700 after the LPF+CDS which shares the same reference levels V refp and V refn with the ADC.
  • a programmable and systematic offset 702 which is larger than the sum of all maximum expected parasitic offsets, is applied by using this DAC 700.
  • the DAC included in the feedback path is a resistive DAC based on a resistive ladder 127 and a multiplexer 706 in order to select the appropriate taps.
  • the initialization voltage of the LPF+CDS can be derived from the same resistive ladder 127 but with a further multiplexer 708.
  • the initialisation of the previous block i.e. the CSA
  • the initialisation output voltage of the CSA can also be derived from the same resistive ladder 127 by using another multiplexer - not shown - for connecting it to the CSA.
  • This large compensation consists of injecting a compensation charge Q inj , the value of which is opposite to the charge offset, in the CSA or in a later block.
  • the amplitude value of the injected charge Q inj must be at least the minimum total charge to be detected, but not exceed the maximum total charge. In can simply be set as equal but opposite sign of the offset equivalent charge.
  • the injected charge should be proportional to the reference voltage of the DAC, so that V inj1 and V inj2 should best be selected from V refp of V refn or from tabs from a resistive divider between V refp and V refn .
  • the capacitor c inj for charge injection should also be matched with the other capacitors in order also to reduce the drifts and thermal dependency.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)
  • Electronic Switches (AREA)
  • Amplifiers (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
EP11705496.5A 2010-09-14 2011-02-14 Circuit for capacitive touch applications Active EP2617132B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH14752010 2010-09-14
PCT/EP2011/052160 WO2012034714A1 (en) 2010-09-14 2011-02-14 Circuit for capacitive touch applications

Publications (2)

Publication Number Publication Date
EP2617132A1 EP2617132A1 (en) 2013-07-24
EP2617132B1 true EP2617132B1 (en) 2020-12-02

Family

ID=43242635

Family Applications (1)

Application Number Title Priority Date Filing Date
EP11705496.5A Active EP2617132B1 (en) 2010-09-14 2011-02-14 Circuit for capacitive touch applications

Country Status (6)

Country Link
EP (1) EP2617132B1 (ko)
JP (1) JP5563722B2 (ko)
KR (1) KR20130107275A (ko)
CN (1) CN103262417B (ko)
TW (1) TWI385569B (ko)
WO (1) WO2012034714A1 (ko)

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH705869A1 (fr) * 2011-12-02 2013-06-14 Advanced Silicon S A Interface et procédé de lecture de capteur capacitif.
TWI464662B (zh) * 2012-05-30 2014-12-11 適用於電容式觸控面板之雜訊消除電路
US9182432B2 (en) * 2012-07-18 2015-11-10 Synaptics Incorporated Capacitance measurement
US9279874B2 (en) * 2012-08-16 2016-03-08 Microchip Technology Germany Gmbh Signal processing for a capacitive sensor system with robustness to noise
EP3036606B1 (en) 2013-08-20 2018-10-10 Advanced Silicon SA Capacitive touch system
DE202014103396U1 (de) 2013-08-20 2014-08-08 Advanced Silicon Sa Aktiver Eingabestift
US8836669B1 (en) 2013-09-13 2014-09-16 Cypress Semiconductor Corporation High resolution capacitance to code converter
KR101394465B1 (ko) * 2013-10-15 2014-05-13 주식회사 아나패스 터치 감지 장치 구동 방법 및 이를 이용한 터치 감지 장치
CN103714330B (zh) * 2014-01-06 2017-12-19 苏州迈瑞微电子有限公司 电容指纹传感器
KR102182979B1 (ko) * 2014-05-30 2020-11-26 엘지디스플레이 주식회사 센싱 시스템
EP2975770B1 (en) * 2014-07-17 2017-11-01 Semtech Corporation Sampling circuitry and sampling method for a plurality of electrodes
KR102249651B1 (ko) 2014-07-23 2021-05-10 주식회사 실리콘웍스 터치패널 센싱 장치 및 그 제어 장치
CN104219462B (zh) * 2014-08-30 2018-01-05 中国科学院长春光学精密机械与物理研究所 带有电压输出型分段积分读出电路的nmos线阵图像传感器
US9710118B2 (en) 2014-09-04 2017-07-18 Samsung Electronics Co., Ltd. Semiconductor device and semiconductor system for producing noise differences between points of time
KR102243635B1 (ko) 2014-11-21 2021-04-26 엘지디스플레이 주식회사 터치 센싱 회로와 이를 이용한 표시장치 및 터치 센싱 방법
CN113655915A (zh) 2014-12-23 2021-11-16 剑桥触控科技有限公司 压敏触摸面板
GB2533667B (en) 2014-12-23 2017-07-19 Cambridge Touch Tech Ltd Pressure-sensitive touch panel
US9740351B2 (en) * 2015-05-15 2017-08-22 Synaptics Incorporated Multi-step incremental switching scheme
US10151608B2 (en) * 2015-12-22 2018-12-11 Microchip Technology Incorporated System and method for reducing noise in a sensor system
GB2544353B (en) 2015-12-23 2018-02-21 Cambridge Touch Tech Ltd Pressure-sensitive touch panel
US10282046B2 (en) 2015-12-23 2019-05-07 Cambridge Touch Technologies Ltd. Pressure-sensitive touch panel
CN105574520B (zh) * 2016-02-23 2021-09-17 北京集创北方科技股份有限公司 用于指纹传感器的信号处理电路及方法
JP2017168930A (ja) * 2016-03-14 2017-09-21 株式会社東芝 スイッチトキャパシタ回路
EP3242190B1 (en) 2016-05-06 2019-11-06 Advanced Silicon SA System, method and computer program for detecting an object approaching and touching a capacitive touch device
US10031620B2 (en) * 2016-06-30 2018-07-24 Stmicroelectronics Asia Pacific Pte Ltd Self-sensing touch panel
JP2020003211A (ja) * 2016-09-29 2020-01-09 株式会社村田製作所 容量測定回路及び容量測定システム
CN106599769B (zh) * 2016-10-19 2023-08-22 深圳芯启航科技有限公司 一种减base实现触控/指纹类ic高效识别的方法及实现电路
KR102593262B1 (ko) 2016-11-02 2023-10-26 삼성전자주식회사 터치 센서 컨트롤러
DE102017110976B8 (de) * 2017-05-19 2018-12-06 Infineon Technologies Austria Ag Selbstoszillierender Mehrrampen-Umsetzer und Verfahren zum Umsetzen einer Kapazität in ein digitales Signal
CN107332563A (zh) * 2017-05-31 2017-11-07 苏州真感微电子科技有限公司 降低开关电容输入电流的电路及开关电容的采样方法
GB2565305A (en) 2017-08-08 2019-02-13 Cambridge Touch Tech Ltd Device for processing signals from a pressure-sensing touch panel
US11093088B2 (en) 2017-08-08 2021-08-17 Cambridge Touch Technologies Ltd. Device for processing signals from a pressure-sensing touch panel
US10305452B2 (en) * 2017-09-28 2019-05-28 Microchip Technology Incorporated Five-level switched-capacitance DAC using bootstrapped switches
JP6960831B2 (ja) * 2017-11-17 2021-11-05 エイブリック株式会社 センサ装置
KR102398446B1 (ko) * 2017-12-12 2022-05-16 주식회사 디비하이텍 아날로그-디지털 변환기
US10547322B2 (en) * 2018-01-02 2020-01-28 Samsung Electronics Co., Ltd. Analog-digital converter having multiple feedback, and communication device including the analog-digital converter
WO2019142804A1 (ja) * 2018-01-19 2019-07-25 ローム株式会社 抵抗膜タッチパネルの制御回路、タッチ式入力装置
WO2020075552A1 (ja) * 2018-10-10 2020-04-16 ソニーセミコンダクタソリューションズ株式会社 スイッチトキャパシタアンプおよびａｄ変換装置
JP6753972B2 (ja) * 2019-03-07 2020-09-09 株式会社東芝 スイッチトキャパシタ回路
KR102329906B1 (ko) * 2020-06-25 2021-11-23 고려대학교 산학협력단 축차 비교형 정전용량-디지털 변환기 및 그 동작 방법
EP3936983A1 (en) 2020-07-06 2022-01-12 Advanced Silicon SA System for detecting a clicked state and an unclicked state of a button for capacitive touch device
CN113346896B (zh) * 2021-04-27 2022-09-02 北京航空航天大学 电荷积分计数式电路以及模拟存算一体结构
KR20240035588A (ko) * 2021-08-24 2024-03-15 알프스 알파인 가부시키가이샤 고속 스타트업 샘플 앤 홀드 스위치드 커패시터 회로
CN114356135B (zh) * 2021-12-27 2022-07-15 北京奕斯伟计算技术有限公司 采样电路、信号处理电路、显示装置及信号处理方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002051264A (ja) * 2000-08-03 2002-02-15 Sharp Corp 相関２重サンプリング回路
US20060139198A1 (en) * 2004-12-28 2006-06-29 Rao Naresh K Data acquisition system for medical imaging
JP2009294197A (ja) * 2008-05-09 2009-12-17 Panasonic Electric Works Co Ltd センサ装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5543591A (en) 1992-06-08 1996-08-06 Synaptics, Incorporated Object position detector with edge motion feature and gesture recognition
US5790107A (en) 1995-06-07 1998-08-04 Logitech, Inc. Touch sensing method and apparatus
EP1717681B1 (en) 1998-01-26 2015-04-29 Apple Inc. Method for integrating manual input
US7663607B2 (en) 2004-05-06 2010-02-16 Apple Inc. Multipoint touchscreen
JPH11251903A (ja) * 1998-03-05 1999-09-17 Asahi Kasei Micro Syst Co Ltd Ａｄ／ｄａ変換兼用回路
JP3942793B2 (ja) 2000-03-30 2007-07-11 シャープ株式会社 電荷量検出回路
JP4246090B2 (ja) * 2004-03-18 2009-04-02 富士フイルム株式会社 信号検出方法および装置並びに放射線画像信号検出方法およびシステム
US7053806B1 (en) * 2005-03-31 2006-05-30 General Electric Company System and method for calibration of autoranging architectures
US7312616B2 (en) 2006-01-20 2007-12-25 Cypress Semiconductor Corporation Successive approximate capacitance measurement circuit
US8711129B2 (en) 2007-01-03 2014-04-29 Apple Inc. Minimizing mismatch during compensation
US8054090B2 (en) * 2008-10-22 2011-11-08 Atmel Corporation Noise handling in capacitive touch sensors
US8040270B2 (en) * 2009-02-26 2011-10-18 General Electric Company Low-noise data acquisition system for medical imaging
EP2224598B1 (en) 2009-02-27 2013-07-10 Research In Motion Limited Method and apparatus for creating side information from data for use in interactive compression

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002051264A (ja) * 2000-08-03 2002-02-15 Sharp Corp 相関２重サンプリング回路
US20060139198A1 (en) * 2004-12-28 2006-06-29 Rao Naresh K Data acquisition system for medical imaging
JP2009294197A (ja) * 2008-05-09 2009-12-17 Panasonic Electric Works Co Ltd センサ装置

Also Published As

Publication number Publication date
WO2012034714A1 (en) 2012-03-22
KR20130107275A (ko) 2013-10-01
TWI385569B (zh) 2013-02-11
JP2013541272A (ja) 2013-11-07
EP2617132A1 (en) 2013-07-24
JP5563722B2 (ja) 2014-07-30
CN103262417A (zh) 2013-08-21
CN103262417B (zh) 2016-10-19
TW201211870A (en) 2012-03-16

Similar Documents

Publication Publication Date Title
EP2617132B1 (en) Circuit for capacitive touch applications
US8970227B2 (en) Circuit for capacitive touch applications
CN107086868B (zh) 具有电荷重新平衡集成器的模拟/数字转换
RU2430465C2 (ru) Способ оцифровки аналоговой величины, оцифровывающее устройство, осуществляющее указанный способ, и детектор электромагнитного излучения, содержащий такое устройство
EP2876407B1 (en) Capacitive sensing interface for proximity detection
US8358142B2 (en) Methods and circuits for measuring mutual and self capacitance
US10051224B2 (en) Dual sample-and-hold circuit with resistive gain
KR101514533B1 (ko) 호버 센싱을 지원하는 터치 센싱 장치 및 방법
US20150145535A1 (en) Capacitive sensing interface for proximity detection
WO2006092055A1 (en) Circuit calibration using voltage injection
EP2270987B1 (en) Capacitive integrate and fold charge-to-digital converter
US11294504B2 (en) Oversampled high signal to noise ratio analog front end for touch screen controllers
US8416117B2 (en) Analog to digital converter with dual integrating capacitor systems
JP6362915B2 (ja) センサ回路構成
US7538710B2 (en) Device for measuring an electric charge in digitized form
TW201312945A (zh) 具有可調整轉換窗之類比數位轉換器
Petrellis et al. Capacitive sensor estimation based on self-configurable reference capacitance
Sanjurjo et al. A high-sensitivity reconfigurable integrating dual-slope CDC for MEMS capacitive sensors
JP4429796B2 (ja) センサ装置
CN115580287A (zh) 一种基于开关电容的可重构传感器接口电路
Petrellis et al. A digitally configurable reference capacitance with mismatch compensation for biosensor readout circuits
HAZE et al. Errors and Their Cancellation in ADC Using Switched Capacitors Technique
Cui et al. Small-Area and High-Accuracy Calibration Technique for Sensing Capacitor in the Touch Screen Panel

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20130314

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20171115

RIN1 Information on inventor provided before grant (corrected)

Inventor name: CHAPPATTE, NORMAN

Inventor name: VUADENS, FRANCOIS

Inventor name: NYS, OLIVIER

Inventor name: BALLAN, HUSSEIN

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: ADVANCED SILICON SA

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20200622

RIN1 Information on inventor provided before grant (corrected)

Inventor name: BALLAN, HUSSEIN

Inventor name: NYS, OLIVIER

Inventor name: VUADENS, FRANCOIS

Inventor name: CHAPPATTE, NORMAN

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

INTC Intention to grant announced (deleted)
GRAR Information related to intention to grant a patent recorded

Free format text: ORIGINAL CODE: EPIDOSNIGR71

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

INTG Intention to grant announced

Effective date: 20201027

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1342041

Country of ref document: AT

Kind code of ref document: T

Effective date: 20201215

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602011069497

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210302

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20201202

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1342041

Country of ref document: AT

Kind code of ref document: T

Effective date: 20201202

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210302

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210405

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602011069497

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210402

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20210228

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210228

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210228

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210214

26N No opposition filed

Effective date: 20210903

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210214

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210402

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210228

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20230221

Year of fee payment: 13

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20110214

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20201202

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240219

Year of fee payment: 14

Ref country code: GB

Payment date: 20240219

Year of fee payment: 14