EP1741016B1 - Stromspiegelanordnung - Google Patents

Stromspiegelanordnung Download PDF

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Publication number
EP1741016B1
EP1741016B1 EP05742902A EP05742902A EP1741016B1 EP 1741016 B1 EP1741016 B1 EP 1741016B1 EP 05742902 A EP05742902 A EP 05742902A EP 05742902 A EP05742902 A EP 05742902A EP 1741016 B1 EP1741016 B1 EP 1741016B1
Authority
EP
European Patent Office
Prior art keywords
transistor
current
current mirror
controlled
mirror device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
EP05742902A
Other languages
German (de)
English (en)
French (fr)
Other versions
EP1741016A1 (de
Inventor
Jakob Jongsma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram AG
Original Assignee
Austriamicrosystems AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Austriamicrosystems AG filed Critical Austriamicrosystems AG
Priority to EP10184332.4A priority Critical patent/EP2282249B1/de
Publication of EP1741016A1 publication Critical patent/EP1741016A1/de
Application granted granted Critical
Publication of EP1741016B1 publication Critical patent/EP1741016B1/de
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the present invention relates to a current mirror arrangement.
  • Current mirrors can be applied in different circuit techniques or integration techniques, for example in MOS, metal oxide semiconductor, circuit technology.
  • FIG. 1 shows an exemplary, known current mirror, which has two transistors 2, 3 connected to a reference potential terminal 1.
  • the transistors 2, 3 of the current mirror are each of the n-type conductivity and connected directly to each other at their control terminals.
  • the input-side transistor 2 of the current mirror has a controlled path, which is connected with a first terminal to the gate terminal of the transistor 2 and with another terminal to the reference potential terminal 1.
  • the connected to the gate terminal of the transistor 2 terminal of the controlled path of the transistor 2 is further connected via a current source 4 to a supply potential terminal 5.
  • the transistor 3 of FIG. 1 has a controlled path, on the one hand to the reference potential terminal 1 and on the other hand to a terminal of another transistor. 6 connected is.
  • the further transistor 6 is connected to the supply potential connection 5 with a further connection of its controlled path and of the p-conductivity type.
  • the control terminal of the transistor 6 is connected to that terminal of its controlled path, which is connected to the transistor 3.
  • the circuit according to FIG. 1 serves to generate two bias signals, namely on the one hand a bias signal NBIAS for n-MOS devices and on the other hand, a bias signal PBIAS for p-MOS devices.
  • the bias signal NBIAS can be tapped off at the control terminals of the n-channel transistors 2, 3 at an output terminal 7.
  • Another output terminal 8, which is connected to the control terminal of the transistor 6, serves as an output for picking up the PBIAS signal.
  • FIG. 2 shows a development of the circuit of FIG. 1 which largely corresponds to this in the components used and their mode of operation, but is supplemented by a cascode stage 9, 10.
  • the cascode stage 9, 10 comprises two transistors, of which one each is connected in the current paths between the current source 4 and the transistor 2 and between the diode 6 and the transistor 3.
  • the transistors 9, 10 of the cascode stage, of which transistor 9 is connected as a diode in turn together form a current mirror.
  • FIG. 1 Opposite the circuit of FIG. 1 has the current mirror arrangement of FIG. 2 with cascode an improved match of the signals NBIAS and PBIAS with each other. Nevertheless, also in the circuit according to FIG. 2 no exact match of the bias signals for components of the opposite, that is to say complementary, conductivity type ensured.
  • NBIAS and PBIAS signals it is desirable to achieve an exact match between NBIAS and PBIAS signals, for example, to operate transistors of complementary conductivity type in matching operating points and / or to provide circuits with high symmetry and good matching.
  • the object of the present invention is to specify a current mirror arrangement which makes it possible to deliver two bias currents which coincide very precisely with one another and are suitable for driving integrated components of different conductivity types.
  • the proposed principle to provide two transistors of different conductivity type each for delivering a current suitable as a bias signal.
  • the first and the second transistor are driven so that they are not themselves the respective output transistor of a current mirror. Rather, it is according to the invention provided that the output transistor of a current mirror is designed as a controlled current source, which is connected between the first and the second transistor.
  • the proposed current mirror arrangement Due to the interconnection of the proposed current mirror arrangement, it is possible to generate exactly matching currents at the first transistor and the second transistor, which enable the respective activation of complementary components in a highly precise manner. In this case, with additional advantage of the circuit complexity compared to a conventional current mirror arrangement for providing complementary bias signals low. As a result, the proposed principle with relatively small chip area and thus be integrated cost.
  • the controlled current source which forms the output of the current mirror which drives the first and second transistors, is preferably designed as a so-called floating current source, ie for operation with a floating potential.
  • floating potential is sometimes referred to as floating potential.
  • the first transistor, the controlled current source and the second transistor are arranged in a common current path.
  • the controlled current source arranged in the middle between the two transistors, which itself has floating potential, ensures that the currents through the first and second transistors are identical and thus a further improved match between the two emitted bias currents of the current mirror arrangement is present.
  • the two conductivity types of the transistors are preferably a p-conductivity type and an n-conductivity type. This means that the first transistor is preferably a p-channel transistor and the second transistor is a complementary n-channel transistor.
  • the first transistor and the second transistor are preferably each connected as a diode.
  • the first current and the second current are each tapped at the load connection of the first and second transistor connected to the controlled current source.
  • control connection of the respective transistor is connected to this tap node to form a diode.
  • the common current path which comprises the series connection of the first transistor, controlled current source and second transistor, is preferably connected between a supply potential terminal and a reference potential terminal.
  • the controlled current source itself is preferably also designed as a transistor, namely as a current source transistor, whose controlled path forms a series circuit with the controlled paths of the first and second transistors.
  • the controlled current source preferably forms the current mirror with a diode-connected transistor, wherein the diode-connected transistor is further preferably arranged in a further current path, that of an input-side Power source is powered.
  • the current source in the further current path serves as a reference current source.
  • the further current path further preferably includes a further diode, which is connected between the input-side transistor of the current mirror and the reference potential or supply potential connection.
  • a further transistor may be provided, which together with the second transistor forms a feedback current mirror, wherein the second transistor is connected as a diode.
  • the two current mirrors of this further developed current mirror arrangement form together a so-called Wilson current mirror.
  • the current mirror arrangement is preferably produced in integrated circuit construction.
  • the current mirror arrangement is preferably integrated in unipolar circuit technology, for example a metal-insulator-semiconductor structure.
  • the current mirror arrangement is preferably constructed in complementary MOS circuit technology.
  • the proposed current mirror arrangement also works in the complementary circuit variant, which means that all n-channel conductivity type MOS transistors are replaced by p-channel devices and vice versa.
  • FIG. 3 shows a current mirror arrangement according to the proposed principle with a first transistor 11, which is of a p-type conductivity, and with a second transistor 12, which is of an n-type conductivity.
  • the first and the second transistor 11, 12 each have a control terminal and one controlled path each. Between each one terminal of the controlled paths of the transistors 11, 12, a current source 13 is connected.
  • the free connection of the controlled path of the transistor 11 is connected to a supply potential terminal 14 and the free connection of the controlled path of the second transistor 12 to a reference potential terminal 15 interconnected.
  • the connected to the current source 13 terminals of the controlled paths of the transistors 11, 12 are connected to the respective control terminal of the associated transistor 11, 12 to form a diode and at the same time form outputs 16, 17 of the current mirror assembly.
  • the first output 16 is designed to deliver a first current PBIAS, while the second output 17 is designed to deliver a second, the first complementary current NBIAS.
  • First and second currents serve as complementary BIAS signals.
  • the current source 13 is designed as a floating current source, that is to say with a floating potential.
  • a further current path is provided, which is designed to be traversed by a reference current I REF .
  • a reference current I REF To couple these two current paths is a in FIG. 3 not explicitly drawn current mirror provided, which is indicated by the fact that the controlled current source 13 is traversed by the n-times the reference current I REF of the first current path.
  • the letter n represents the mirror ratio of the current mirror.
  • the proposed circuit has a low component cost and is inexpensive to integrate with a small chip area and therefore.
  • FIG. 4 A development of the circuit of FIG. 3 for generating identical n-MOS and p-MOS currents by means of a current mirror arrangement FIG. 4 ,
  • the circuit of FIG. 4 agrees in the components used, their advantageous interconnection and operation largely with that of FIG. 3 and will not be repeated at this point.
  • the floating powered controlled current source 13 is at FIG. 4 is formed as a transistor 13 ', which forms the current mirror 18, 13' with an input transistor 18.
  • the input transistor 18 is connected as a diode.
  • the transistor 18 is of the n-channel type.
  • a current source 19 is provided, which connects a supply potential terminal 14 to a terminal of the controlled path of the diode transistor 18, which is also connected to its gate terminal.
  • Another transistor diode 20, also of the n-conductivity type connects the transistor 18 to the reference potential terminal 15.
  • the reference current source 19, the transistor 18 and the diode 20 together form a series circuit.
  • FIG. 5 shows a further embodiment of a development of a current mirror arrangement according to the proposed Principle.
  • the circuit of FIG. 5 agrees in the components used, their interconnection with each other and their advantageous operation largely with that of FIG. 4 and will not be described again at this point.
  • the transistors 12, 20 ' together form a feedback current mirror, which together with the current mirror 18, 13', which operates in the forward direction, forms a Wilson current mirror.
  • the Wilson current mirror 18, 13 '; 12, 20 ' forms a closed loop.
  • bias signals PBIAS, NBIAS which can be tapped off at the outputs 16, 17 exactly match one another.
EP05742902A 2004-04-30 2005-04-15 Stromspiegelanordnung Expired - Fee Related EP1741016B1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP10184332.4A EP2282249B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102004021232A DE102004021232A1 (de) 2004-04-30 2004-04-30 Stromspiegelanordnung
PCT/EP2005/004038 WO2005109144A1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP10184332.4A Division-Into EP2282249B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung
EP10184332.4A Division EP2282249B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung

Publications (2)

Publication Number Publication Date
EP1741016A1 EP1741016A1 (de) 2007-01-10
EP1741016B1 true EP1741016B1 (de) 2012-09-19

Family

ID=34967876

Family Applications (2)

Application Number Title Priority Date Filing Date
EP05742902A Expired - Fee Related EP1741016B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung
EP10184332.4A Not-in-force EP2282249B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP10184332.4A Not-in-force EP2282249B1 (de) 2004-04-30 2005-04-15 Stromspiegelanordnung

Country Status (5)

Country Link
US (1) US7872463B2 (zh)
EP (2) EP1741016B1 (zh)
JP (1) JP2007535744A (zh)
DE (1) DE102004021232A1 (zh)
WO (1) WO2005109144A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8878511B2 (en) * 2010-02-04 2014-11-04 Semiconductor Components Industries, Llc Current-mode programmable reference circuits and methods therefor
US8680840B2 (en) * 2010-02-11 2014-03-25 Semiconductor Components Industries, Llc Circuits and methods of producing a reference current or voltage
JP5500108B2 (ja) * 2011-03-16 2014-05-21 富士通セミコンダクター株式会社 カレントミラー回路及びそれを有する増幅回路
US9563222B2 (en) * 2014-05-08 2017-02-07 Varian Medical Systems, Inc. Differential reference signal distribution method and system
CN209248374U (zh) * 2018-12-05 2019-08-13 北京矽成半导体有限公司 不受温度电压影响的固定延迟电路

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JPS5652420A (en) * 1979-10-03 1981-05-11 Toshiba Corp Constant-current circuit
US5034626A (en) * 1990-09-17 1991-07-23 Motorola, Inc. BIMOS current bias with low temperature coefficient
KR930010834A (ko) * 1991-11-25 1993-06-23 프레데릭 얀 스미트 기준 전류 루프
GB9223338D0 (en) * 1992-11-06 1992-12-23 Sgs Thomson Microelectronics Low voltage reference current generating circuit
JP3436971B2 (ja) * 1994-06-03 2003-08-18 三菱電機株式会社 電圧制御型電流源およびそれを用いたバイアス発生回路
FR2724025B1 (fr) * 1994-08-31 1997-01-03 Sgs Thomson Microelectronics Circuit integre avec fonction de demarrage rapide de sources de tension ou courant de reference
US5640122A (en) * 1994-12-16 1997-06-17 Sgs-Thomson Microelectronics, Inc. Circuit for providing a bias voltage compensated for p-channel transistor variations
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US5680038A (en) * 1996-06-20 1997-10-21 Lsi Logic Corporation High-swing cascode current mirror
JP3853911B2 (ja) * 1997-06-25 2006-12-06 沖電気工業株式会社 定電流回路及びそれを用いた差動増幅回路
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US6515538B2 (en) * 2000-04-19 2003-02-04 Nec Compound Semiconductor Devices, Ltd. Active bias circuit having wilson and widlar configurations
FR2834396B1 (fr) * 2002-01-03 2004-02-27 Cit Alcatel Pompe a charge a tres large plage de tension de sortie
ITTO20020816A1 (it) * 2002-09-19 2004-03-20 Atmel Corp Specchio di corrente a bassa tensione a dinamica rapida con
JP2004274207A (ja) * 2003-03-06 2004-09-30 Renesas Technology Corp バイアス電圧発生回路および差動増幅器
DE102004042354B4 (de) 2004-09-01 2008-06-19 Austriamicrosystems Ag Stromspiegelanordnung
DE102007007579B4 (de) 2007-02-15 2015-05-21 Infineon Technologies Ag Senderschaltung
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Also Published As

Publication number Publication date
EP2282249A1 (de) 2011-02-09
DE102004021232A1 (de) 2005-11-17
EP1741016A1 (de) 2007-01-10
JP2007535744A (ja) 2007-12-06
US20080018320A1 (en) 2008-01-24
WO2005109144A1 (de) 2005-11-17
US7872463B2 (en) 2011-01-18
EP2282249B1 (de) 2015-10-07

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