WO2005109144A1 - Stromspiegelanordnung - Google Patents
Stromspiegelanordnung Download PDFInfo
- Publication number
- WO2005109144A1 WO2005109144A1 PCT/EP2005/004038 EP2005004038W WO2005109144A1 WO 2005109144 A1 WO2005109144 A1 WO 2005109144A1 EP 2005004038 W EP2005004038 W EP 2005004038W WO 2005109144 A1 WO2005109144 A1 WO 2005109144A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- transistor
- current
- current mirror
- controlled
- mirror arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
Definitions
- the present invention relates to a current mirror arrangement.
- Current mirrors can be used in different circuit techniques or integration techniques, for example in MOS, metal oxide semiconductor, circuit technology.
- FIG. 1 shows an exemplary known current mirror, which has two transistors 2, 3 connected against a reference potential connection 1.
- the transistors 2, 3 of the current mirror are each of the n-conductivity type and connected directly to one another at their control connections.
- the transistor 2 on the input side of the current mirror has a controlled path which is connected with a first connection to the gate connection of the transistor 2 and with a further connection to the reference potential connection 1.
- the connection of the controlled path of transistor 2 connected to the gate connection of transistor 2 is also connected via a current source 4 to a supply potential connection 5.
- the transistor 3 from FIG. 1 also has a controlled path, which on the one hand has the reference potential connection 1 and on the other hand has a connection of a further transistor 6 connected is.
- the further transistor 6 is connected with a further connection of its controlled path to the supply potential connection 5 and is of the p-conductivity type.
- the control connection of transistor 6 is connected to that connection of its controlled path which is connected to transistor 3.
- the circuit according to FIG. 1 serves to generate two bias signals, namely on the one hand a bias signal NBIAS for n-MOS components and on the other hand a bias signal PBIAS for p-MOS components.
- the bias signal NBIAS can be tapped off at the control connections of the n-channel transistors 2, 3 at an output connection 7.
- Another output terminal 8, which is connected to the control terminal of the transistor 6, serves as an output for tapping the PBIAS signal.
- FIG. 2 shows a further development of the circuit from FIG. 1, which largely corresponds to this in the components used and their mode of operation, but is supplemented by a cascode stage 9, 10.
- the cascode stage 9, 10 comprises two transistors, one of which is connected into the current paths between current source 4 and transistor 2 and between diode 6 and transistor 3.
- the current mirror arrangement of FIG. 2 with a cascode has an improved correspondence of the signals NBIAS and PBIAS with one another. Nevertheless, even in the circuit according to FIG. 2, no exact match of the bias signals for components of the opposite, that is to say complementary, conductivity type is guaranteed. Rather, the bias signals in the circuit of FIG. 2 can also differ remarkably from one another.
- NBIAS and PBIAS signals it is desirable to achieve an exact match between the NBIAS and PBIAS signals, for example in order to operate transistors of complementary conductivity type in matching operating points and / or to create circuits with high symmetry and good matching.
- the object of the present invention is to provide a current mirror arrangement which makes it possible to emit two bias currents which correspond very precisely to one another and are suitable for controlling integrated components of different conductivity types.
- a current mirror arrangement comprising:
- a first transistor which is of a first conductivity type, designed to deliver a first current
- a second transistor which is of a second conductivity type, designed to deliver a second current
- a controlled current source which is connected between the first transistor and the second transistor and which forms the output of a current mirror.
- the invention provides that the output transistor of a Current mirror is designed as a controlled current source, which is connected between the first and the second transistor.
- the proposed current mirror arrangement Because of the interconnection of the proposed current mirror arrangement, it is possible to generate currents that exactly match each other on the first transistor and the second transistor, which currents enable the respective control of complementary components in a highly precise manner.
- An additional advantage is that the circuit complexity is low compared to a conventional current mirror arrangement for providing complementary bias signals. As a result, the proposed principle can be integrated with a relatively small chip area and thus cost-effectively.
- the controlled current source which forms the output of the current mirror driving the first and second transistor, is preferably designed as a so-called floating current source, that is to say for operation with a floating potential.
- a floating potential is sometimes referred to as a floating potential.
- the first transistor, the controlled current source and the second transistor are preferably arranged in a common current path.
- the controlled current source arranged in the middle between the two transistors, which itself has floating potential, ensures that the currents through the first and second transistors are of identical size and thus an even better match between the two emitted bias currents of the current mirror arrangement is present.
- the two conductivity types of the transistors are preferably a p-conductivity type and an n-conductivity type. This means that the first transistor is preferably a p-channel transistor and the second transistor is a complementary n-channel transistor.
- the first transistor and the second transistor are preferably each connected as a diode.
- the first current and the second current are tapped in each case at the load connection of the first or second transistor connected to the controlled current source.
- the tap is more preferred
- the common current path which comprises the series connection of the first transistor, controlled current source and second transistor, is preferably connected between a supply potential connection and a reference potential connection.
- the controlled current source itself is preferably also designed as a transistor, namely as a current source transistor, the controlled path of which forms a series circuit with the controlled paths of the first and second transistors.
- the controlled current source preferably forms the current mirror with a transistor connected as a diode, the transistor connected as a diode being further preferably arranged in a further current path which is connected from an input side is fed to the power source.
- the current source in the further current path serves as a reference current source.
- the further current path further preferably comprises a further diode which is connected between the transistor on the input side of the current mirror and the reference potential or supply potential connection.
- a further transistor can be provided which, together with the second transistor, forms a feedback current mirror, the second transistor being connected as a diode.
- the two current mirrors of this further developed current mirror arrangement together form a so-called Wilson current mirror.
- the current mirror arrangement is preferably produced in an integrated circuit design.
- the current mirror arrangement is preferably integrated in unipolar circuit technology, for example a metal-insulator-semiconductor structure.
- the current mirror arrangement is preferably constructed using complementary MOS circuit technology.
- the proposed current mirror arrangement also functions alternatively in the complementary circuit variant, which means that all MOS transistors of the n-channel conductivity type are replaced by components with p-channel and vice versa.
- the invention is explained in more detail below on the basis of several exemplary embodiments in connection with the figures.
- FIG. 1 shows a current mirror arrangement according to the prior art
- FIG. 2 shows a current mirror arrangement according to the prior art with a cascode stage
- FIG. 3 shows the basic principle of the proposed current mirror arrangement using a circuit diagram
- Figure 4 is a further development of the circuit of Figure 3 using a circuit diagram
- Figure 5 is a further development of the circuit of Figure 3 with Wilson current mirror.
- FIG. 3 shows a current mirror arrangement in accordance with the proposed principle with a first transistor 11, which is of a p-conductivity type, and with a second transistor 12, which is of an n-conductivity type.
- the first and the second transistor 11, 12 each have a control connection and a controlled path.
- a current source 13 is connected between one connection each of the controlled sections of the transistors 11, 12.
- the free connection of the controlled path of the transistor 11 is connected to a supply potential connection 14 and the free connection of the controlled path of the second transistor 12 connected to a reference potential connection 15.
- the connections of the controlled paths of the transistors 11, 12 connected to the current source 13 are connected to the respective control connection of the associated transistor 11, 12 to form a diode and at the same time form outputs 16, 17 of the current mirror arrangement.
- the first output 16 is designed to deliver a first current PBIAS, while the second output 17 is designed to deliver a second current NBIAS complementary to the first.
- the first and second stream serve as complementary BIAS signals.
- the current source 13 is designed as a floating current source, that is to say with a floating potential.
- a current mirror which is not explicitly shown in FIG. 3, is provided for coupling these two current paths, which is indicated by the fact that the controlled current source 13 flows through the n-fold reference current I REF of the first current path.
- the letter n represents the mirror ratio of the current mirror.
- the interconnection according to FIG. 3 ensures that the currents in the p-channel transistor 11 and in the n-channel transistor 12 are of identical size and thus also the complementary ones provided by the transistors and tapped at the outputs 16, 17 Bias signals PBIAS, NBIAS are exactly the same size.
- the proposed circuit has a low component cost and can be integrated with a small chip area and therefore inexpensively.
- FIG. 4 A development of the circuit of FIG. 3 for generating identical n-MOS and p-MOS currents by means of a current mirror arrangement is shown in FIG. 4.
- the circuit of FIG. 4 is correct in the components used, their advantageous interconnection and mode of operation largely match that of
- the float-operated, controlled current source 13 is formed in FIG. 4 as a transistor 13 ', which forms the current mirror 18, 13' with an input transistor 18.
- the input transistor 18 is connected as a diode.
- transistor 18 is of the n-channel type.
- a current source 19 is provided, which connects a supply potential connection 14 to a connection of the controlled path of the diode transistor 18, which is also connected to its gate connection.
- the reference current source 19, the transistor 18 and the diode 20 thus form a series circuit with one another.
- FIG. 5 shows a further embodiment of a development of a current mirror arrangement according to the proposed Principle.
- the circuit of FIG. 5 is largely the same as that of FIG. 4 in the components used, their interconnection with one another and their advantageous mode of operation and is not described again in this regard.
- the control connection of the transistor provided with reference numeral 20 ′ in FIG. 5 is connected to the gate connection of the second transistor 12.
- the transistors 12, 20 ' together form a feedback current mirror which, together with the current mirror 18, 13' which operates in the forward direction, forms a Wilson current mirror.
- the Wilson current mirror 18, 13 '; 12, 20 ' forms a closed control loop.
- bias signals PBIAS, NBIAS which can be tapped at the outputs 16, 17 match exactly with one another.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/579,023 US7872463B2 (en) | 2004-04-30 | 2005-04-15 | Current balance arrangement |
EP05742902A EP1741016B1 (de) | 2004-04-30 | 2005-04-15 | Stromspiegelanordnung |
JP2007509920A JP2007535744A (ja) | 2004-04-30 | 2005-04-15 | カレントミラー回路 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102004021232A DE102004021232A1 (de) | 2004-04-30 | 2004-04-30 | Stromspiegelanordnung |
DE102004021232.5 | 2004-04-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2005109144A1 true WO2005109144A1 (de) | 2005-11-17 |
Family
ID=34967876
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2005/004038 WO2005109144A1 (de) | 2004-04-30 | 2005-04-15 | Stromspiegelanordnung |
Country Status (5)
Country | Link |
---|---|
US (1) | US7872463B2 (de) |
EP (2) | EP1741016B1 (de) |
JP (1) | JP2007535744A (de) |
DE (1) | DE102004021232A1 (de) |
WO (1) | WO2005109144A1 (de) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8878511B2 (en) * | 2010-02-04 | 2014-11-04 | Semiconductor Components Industries, Llc | Current-mode programmable reference circuits and methods therefor |
US8680840B2 (en) * | 2010-02-11 | 2014-03-25 | Semiconductor Components Industries, Llc | Circuits and methods of producing a reference current or voltage |
JP5500108B2 (ja) * | 2011-03-16 | 2014-05-21 | 富士通セミコンダクター株式会社 | カレントミラー回路及びそれを有する増幅回路 |
US9563222B2 (en) * | 2014-05-08 | 2017-02-07 | Varian Medical Systems, Inc. | Differential reference signal distribution method and system |
CN209248374U (zh) * | 2018-12-05 | 2019-08-13 | 北京矽成半导体有限公司 | 不受温度电压影响的固定延迟电路 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5034626A (en) * | 1990-09-17 | 1991-07-23 | Motorola, Inc. | BIMOS current bias with low temperature coefficient |
EP0747800A1 (de) * | 1995-06-05 | 1996-12-11 | STMicroelectronics, Inc. | Schaltungsanordnung zum Liefern einer kompensierten Polarisationsspannung für P-Kanal-Transistoren |
US5680038A (en) * | 1996-06-20 | 1997-10-21 | Lsi Logic Corporation | High-swing cascode current mirror |
US5694073A (en) * | 1995-11-21 | 1997-12-02 | Texas Instruments Incorporated | Temperature and supply-voltage sensing circuit |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5652420A (en) * | 1979-10-03 | 1981-05-11 | Toshiba Corp | Constant-current circuit |
KR930010834A (ko) * | 1991-11-25 | 1993-06-23 | 프레데릭 얀 스미트 | 기준 전류 루프 |
GB9223338D0 (en) * | 1992-11-06 | 1992-12-23 | Sgs Thomson Microelectronics | Low voltage reference current generating circuit |
JP3436971B2 (ja) * | 1994-06-03 | 2003-08-18 | 三菱電機株式会社 | 電圧制御型電流源およびそれを用いたバイアス発生回路 |
FR2724025B1 (fr) * | 1994-08-31 | 1997-01-03 | Sgs Thomson Microelectronics | Circuit integre avec fonction de demarrage rapide de sources de tension ou courant de reference |
JP3853911B2 (ja) * | 1997-06-25 | 2006-12-06 | 沖電気工業株式会社 | 定電流回路及びそれを用いた差動増幅回路 |
US6133749A (en) * | 1999-01-04 | 2000-10-17 | International Business Machines Corporation | Variable impedance output driver circuit using analog biases to match driver output impedance to load input impedance |
US6232831B1 (en) * | 1999-12-02 | 2001-05-15 | National Instruments Corporation | Electrical power supply with floating current source suitable for providing bias voltage and current to an amplified transducer |
US6515538B2 (en) * | 2000-04-19 | 2003-02-04 | Nec Compound Semiconductor Devices, Ltd. | Active bias circuit having wilson and widlar configurations |
FR2834396B1 (fr) * | 2002-01-03 | 2004-02-27 | Cit Alcatel | Pompe a charge a tres large plage de tension de sortie |
ITTO20020816A1 (it) * | 2002-09-19 | 2004-03-20 | Atmel Corp | Specchio di corrente a bassa tensione a dinamica rapida con |
JP2004274207A (ja) * | 2003-03-06 | 2004-09-30 | Renesas Technology Corp | バイアス電圧発生回路および差動増幅器 |
DE102004042354B4 (de) | 2004-09-01 | 2008-06-19 | Austriamicrosystems Ag | Stromspiegelanordnung |
DE102007007579B4 (de) | 2007-02-15 | 2015-05-21 | Infineon Technologies Ag | Senderschaltung |
US20090066498A1 (en) | 2007-09-07 | 2009-03-12 | Infineon Technologies Ag | Tire localization systems and methods |
US8077025B2 (en) | 2007-09-18 | 2011-12-13 | Infineon Technologies, Ag | Intelligent tire systems and methods |
-
2004
- 2004-04-30 DE DE102004021232A patent/DE102004021232A1/de not_active Ceased
-
2005
- 2005-04-15 WO PCT/EP2005/004038 patent/WO2005109144A1/de active Application Filing
- 2005-04-15 JP JP2007509920A patent/JP2007535744A/ja not_active Withdrawn
- 2005-04-15 EP EP05742902A patent/EP1741016B1/de not_active Expired - Fee Related
- 2005-04-15 US US11/579,023 patent/US7872463B2/en not_active Expired - Fee Related
- 2005-04-15 EP EP10184332.4A patent/EP2282249B1/de not_active Not-in-force
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5034626A (en) * | 1990-09-17 | 1991-07-23 | Motorola, Inc. | BIMOS current bias with low temperature coefficient |
EP0747800A1 (de) * | 1995-06-05 | 1996-12-11 | STMicroelectronics, Inc. | Schaltungsanordnung zum Liefern einer kompensierten Polarisationsspannung für P-Kanal-Transistoren |
US5694073A (en) * | 1995-11-21 | 1997-12-02 | Texas Instruments Incorporated | Temperature and supply-voltage sensing circuit |
US5680038A (en) * | 1996-06-20 | 1997-10-21 | Lsi Logic Corporation | High-swing cascode current mirror |
Also Published As
Publication number | Publication date |
---|---|
US7872463B2 (en) | 2011-01-18 |
EP1741016A1 (de) | 2007-01-10 |
EP2282249A1 (de) | 2011-02-09 |
EP1741016B1 (de) | 2012-09-19 |
EP2282249B1 (de) | 2015-10-07 |
DE102004021232A1 (de) | 2005-11-17 |
US20080018320A1 (en) | 2008-01-24 |
JP2007535744A (ja) | 2007-12-06 |
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