EP1715485A2 - Appareil et procédé de formation de signaux - Google Patents

Appareil et procédé de formation de signaux Download PDF

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Publication number
EP1715485A2
EP1715485A2 EP06115016A EP06115016A EP1715485A2 EP 1715485 A2 EP1715485 A2 EP 1715485A2 EP 06115016 A EP06115016 A EP 06115016A EP 06115016 A EP06115016 A EP 06115016A EP 1715485 A2 EP1715485 A2 EP 1715485A2
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EP
European Patent Office
Prior art keywords
sync
run length
signal
pattern
frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP06115016A
Other languages
German (de)
English (en)
Other versions
EP1715485B1 (fr
EP1715485A3 (fr
Inventor
Tadashi Kojima
Koichi Hirayama
Hisashi Yamada
Yoshiaki Pioneer Electronic Corp. Moriyama
Fumihiko Pioneer Electronic Corp. Yokogawa
Takao Arai
Toshifumi Takeuchi
Shinichi Tanaka
Akira Kurahashi
Toshiyuki Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Publication of EP1715485A2 publication Critical patent/EP1715485A2/fr
Publication of EP1715485A3 publication Critical patent/EP1715485A3/fr
Application granted granted Critical
Publication of EP1715485B1 publication Critical patent/EP1715485B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal

Definitions

  • the invention relates to a method of transmitting digital data in which digital data is retained in sectors each comprising a plurality of sync frames and sequentially transmitting it (including recording of the digital data).
  • EFM EFM modulation signal
  • connection bits of three bits are added to intervals among the respective converted data, and the resultant data is formed as an EFM modulation signal.
  • a bit train of the connection bits is set so as to satisfy the foregoing run length limitation.
  • a signal obtained by adding a sync signal to the EFM modulation signal has been recorded.
  • the sequence by the EFM modulation signals is constructed in a manner such that a repetitive pattern of maximum interval which corresponds to the maximum run length k, namely, repetitive pattern such as 11T - 11T doesn't exist in the sequence and the repetitive pattern of 11T is used as a sync signal.
  • the sync signal is extracted by detecting the repetitive pattern of 11T from a signal read out from the CD.
  • the invention is made to solve the problems mentioned above and it is an object of the invention to provide a transmitting method of digital data whereby the digital data can be reproduced at a high precision even at the time of a high-density recording or a high-density data transmission.
  • a transmitting method of digital data for retaining digital data in sectors each comprising a plurality of sync frames and sequentially transmitting, wherein the sync frame comprises a sync signal and a run length limited code which corresponds to the digital data and satisfies limitations of a minimum run length and a maximum run length, and the sync signal includes a sync pattern comprising a bit pattern having a run length which is longer than the maximum run length by 3T and addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length.
  • a transmitting method of digital data for storing the digital data into sectors each comprising a plurality of sync frames and sequentially transmitting, wherein the sync frame comprises a sync signal and a run length limited code which corresponds to the digital data and satisfies limitations regarding a minimum run length and a maximum run length, and the sync signal includes a specific code which indicates a position in the sector and which enables a DC control to be performed.
  • the sync frame is comprised of the sync signal and the run length limited code which satisfies the limitations of the minimum run length and the maximum run length
  • the sync signal includes the sync pattern comprising the bit pattern of the run length that is longer than the maximum run length by 3T and the addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length.
  • the sync signal includes the specific code which indicates the position in the sector and which enables the DC control to be performed.
  • Fig. 1 is a diagram showing a construction of a transmission signal forming apparatus for forming a transmission signal by a transmitting method of digital data according to the invention.
  • All of code words obtained by the 8-16 modulator 10 have pattern forms which satisfy any one of the following conditions of Next_State1 to Next_State4.
  • the modulating method has been published by the following paper.
  • a sync signal generating circuit 20 generates 32 sync signals having different bit patterns as shown in Figs. 2 and 3 and transmits them to a synthesizing circuit 30 which preferably includes a CPU and a memory as described later.
  • Fig. 4 is a diagram showing a format of the sync signal.
  • bits 1 to 3 of the sync signal denote connection bits provided so as to satisfy the foregoing limitations of the minimum run length d and the maximum run length k when the sync signal is connected to a code word just before it.
  • a connection bit pattern by bits 1 to 3 indicate any one of ⁇ 000 ⁇ , ⁇ 001 ⁇ , and ⁇ 100 ⁇ .
  • a sync pattern to identify the sync signal is allocated to bits 11 to 32 of the sync signal.
  • the sync pattern is a bit pattern of an arrangement such as (4T or more - 14T - 4T) in which a pattern of 14T that is larger than the maximum interval 11T in the 8-16 modulation signal by 3T is set to a nucleus and a pattern of a fixed length of 4T and a pattern of 4T or more are arranged after and before the pattern of 14T, respectively, namely, bit pattern of ⁇ 0001000000000000010001 ⁇ .
  • the sync pattern is a fixed pattern which is common to all sync signals as shown in Figs. 2 and 3.
  • the sync pattern even when the 11T pattern in the 8-16 modulation signal is edge-shifted due to an influence by an inter-symbol interference and is changed to a pattern of 12T and, further, the sync pattern itself is edge-shifted and is shortened by only 1T, in order enable both of them to be distinguished, the pattern of 14T that is larger than the maximum interval 11T in the 8-16 modulation signal by 3T is used.
  • the 14T pattern denotes a shortest length which can be set when considering the edge-shift.
  • an addition bit pattern of a fixed length of 4T and an addition bit pattern of 4T or more after and before the 14T pattern an interval that is larger than the shortest bits of 3T by at least 1T is provided, thereby reducing an influence by the inter-symbol interference with a neighboring mark.
  • Fig. 5 is a diagram showing a transmission signal waveform by the sync pattern.
  • the edge interval can be stably detected.
  • the selected pattern can be used as a signal for a speed detection of a spindle servo upon starting.
  • mark lengths before and after the 14T pattern By setting mark lengths before and after the 14T pattern to be equal to or larger than 4T in which an amplitude is larger than the shortest mark length, a permissible amplitude is increased for a fluctuation of the slice level.
  • a rear mark length is set to 4T and a front mark length is set to 4T or more.
  • the reason why the rear pattern of the 14T pattern is set to the fixed length of 4T and the front pattern is set to 4T or more is because when a specific code, which will be described hereinafter, is further set before the 14T pattern, a degree of freedom of the front pattern is increased and the number of patterns to be obtained as a specific code is sufficiently assured.
  • the specific code is allocated to bits 4 to 10 of the sync signal.
  • a position in one sector which will be explained hereinafter, can be identified.
  • the synthesizing circuit 30 in Fig. 1 selects any one of the sync signals generated by the sync signal generating circuit 20 every train of the 8-16 modulation signals which are sequentially supplied from the 8-16 modulator 10, namely, every 91 code words and generates a signal obtained by adding the selected sync signal to the head of the 91 code words as a transmission signal corresponding to one sync frame.
  • Fig. 6 is a diagram showing a format of the transmission signal per one sector which is generated by the synthesizing circuit 30.
  • one sector comprises 13 lines. Two sync frames are allocated to each line.
  • the sync signal allocated to each sync frame is selected from the 32 kinds of sync signals shown in Figs. 2 and 3.
  • the sync signal allocated to a front sync frame of the first line corresponds to SY0 selected from the 32 kinds of sync signals.
  • the sync signal which is allocated to the front sync frame is cyclically repeated like SY1 to SY4 in accordance with an increase in number of line. Differences among SY1 to SY4 are decided by the specific code and connection bits.
  • a CPU central processing unit
  • a memory they are not shown
  • the CPU in the synthesizing circuit 30 first sets 1 as an initial address into a built-in register n (step S1).
  • the CPU reads out information corresponding to the address stored in the register n from the memory shown in Fig. 8, respectively and stores the information into registers X and Y (step S2).
  • SY0 and SY5 stored in address 1 in the memory in Fig. 8 are read out and stored into the registers X and Y, respectively.
  • the CPU selects the sync signal corresponding to the storage contents in the register X from the 32 kinds of sync signals shown in Figs. 2 and 3 which are supplied from the sync signal generating circuit 20.
  • SY0 has been stored in the register X
  • the signal corresponding to SY0 is selected from the 32 kinds of sync signals shown in Figs. 2 and 3.
  • the code word existing just before the sync signal is Next_State1 (the number of continuous 0 at the termination is equal to 1 or 0) or Next_State2 (the number of continuous 0 at the termination is equal to 2 to 5)
  • the CPU selects the sync signal in which the connection bit pattern by bits 1 to 3 is set to ⁇ 000 ⁇ from SY0 shown in Figs. 2 and 3.
  • the CPU selects the pattern which is optimum for the DC suppression from the two kinds of patterns and sets the selected pattern to final SY0.
  • the CPU selects the sync signal corresponding to the storage contents in the register Y. For example, when SY5 has been stored in the register Y, the sync signal corresponding to SY5 is selected from the 32 kinds of sync signals shown in Figs. 2 and 3.
  • the code word existing just before the sync signal is Next_State3 (the number of continuous 0 at the termination is equal to 2 to 5) or Next_State4 (the number of continuous 0 at the termination is equal to 6 to 9)
  • the CPU selects the sync signal in which the connection bit pattern by bits 1 to 3 is equal to ⁇ 100 ⁇ from SY5 shown in Figs. 2 and 3.
  • the CPU selects the pattern which is optimum for the DC suppression from the two kinds of patterns and sets the selected pattern to final SY5 (step S3).
  • the CPU generates a pattern obtained by serially connecting the 8-16 modulation signal of 91 code words to each of the sync signals selected on the basis of the storage contents of the registers X and Y as mentioned above as a transmission signal of one line as shown in Fig. 6 (step S4).
  • step S5 The CPU judges whether the contents in the register n are larger than 13 or not (step S5). In step S5, until it is decided that the contents in the register n are larger than 13, the CPU adds 1 to the contents in the register n (step S6) and, after that, repetitively executes the operations in step S2 and subsequent steps.
  • the transmission signals of the first to 13th lines (of one sector) as shown in Fig. 6 are sequentially generated by the repetitive operation.
  • a decoder side which receives the transmission signal with the structure executes an error correcting process by using the transmission signals each of which has the sector structure as shown in Fig. 6 and which are collected by the number as many as 16 sectors as one error-correction block.
  • the decoder it is important that after completion of the reception of the transmission signal, the head of the sector is searched, an address recorded is subsequently immediately read out, and data of the error-correction block is collected.
  • the 32 kinds of sync signals having different bit patterns are prepared and, further, as shown in Fig. 6, the combination pattern of the sync signal to be allocated to each line in one sector is set to a unique pattern every line.
  • the sync signal in the front sync frame existing at the head of each line is cyclically repeated like SY1 to SY4 in accordance with an increase in number of lines.
  • the line in one sector can be specified by recognizing the combination pattern of the sync signals, so that the position of SY0 at the sector head can be predicted.
  • a preventing function can be further raised for a read error of the sync signal by recognizing the repetitive patterns of SY1 to SY4. Since the line is specified on the basis of the combination pattern of the two sync signals existing in one line, it is sufficient to use eight kinds of SY0 to SY7 as kinds of sync signals in one sector.
  • SY0 is selected in a manner such that an inter-code distance between SY0 and the head syncs (SY1 to SY4) of each of the other lines becomes maximum.
  • the inter-code distance denotes a similarity between the sync signals.
  • the sync signal is a signal of the largest distance.
  • the number of shifting times of the position of 1 until the signal coincides with a sync signal is set to the distance with the sync signal.
  • the sync signal which is relatively similar to SY0 is set to the intermediate sync signal (SY5 to SY7) of each line, and a common sync signal is not used in the head and middle portions of each line.
  • the common sync signal is not used in the head and middle portions of the line, there is also an effect such that a probability such that the head and middle portions of each line is erroneously recognized by the read error is reduced.
  • the sync frame comprises the sync signal and the run length limited code which satisfies the limitations of the minimum run length and the maximum run length
  • the sync signal includes the sync pattern comprised of the bit pattern of a run length which is longer than the maximum run length by 3T and the addition bit patterns which are arranged before and after the bit pattern and each of which has a run length that is longer than the minimum run length.
  • the sync signal includes the specific code which indicates the position in the sector and which enables the DC control to be performed.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
EP06115016A 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux Expired - Lifetime EP1715485B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP31642095A JP3394127B2 (ja) 1995-12-05 1995-12-05 ディジタルデータの伝送方法
EP96119545A EP0779623B1 (fr) 1995-12-05 1996-12-05 Méthode de transmission de données digitales
EP03025667A EP1403869B1 (fr) 1995-12-05 1996-12-05 Dispositif et méthode pour constituer un signal

Related Parent Applications (3)

Application Number Title Priority Date Filing Date
EP03025667A Division EP1403869B1 (fr) 1995-12-05 1996-12-05 Dispositif et méthode pour constituer un signal
EP96119545.0 Division 1996-12-05
EP03025667.1 Division 2003-11-07

Publications (3)

Publication Number Publication Date
EP1715485A2 true EP1715485A2 (fr) 2006-10-25
EP1715485A3 EP1715485A3 (fr) 2008-03-05
EP1715485B1 EP1715485B1 (fr) 2010-04-28

Family

ID=18076885

Family Applications (6)

Application Number Title Priority Date Filing Date
EP06115016A Expired - Lifetime EP1715485B1 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux
EP06115028A Withdrawn EP1715487A3 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux
EP06115021A Expired - Lifetime EP1715486B1 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux
EP96119545A Expired - Lifetime EP0779623B1 (fr) 1995-12-05 1996-12-05 Méthode de transmission de données digitales
EP03025667A Expired - Lifetime EP1403869B1 (fr) 1995-12-05 1996-12-05 Dispositif et méthode pour constituer un signal
EP06115012A Withdrawn EP1715484A3 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux

Family Applications After (5)

Application Number Title Priority Date Filing Date
EP06115028A Withdrawn EP1715487A3 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux
EP06115021A Expired - Lifetime EP1715486B1 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux
EP96119545A Expired - Lifetime EP0779623B1 (fr) 1995-12-05 1996-12-05 Méthode de transmission de données digitales
EP03025667A Expired - Lifetime EP1403869B1 (fr) 1995-12-05 1996-12-05 Dispositif et méthode pour constituer un signal
EP06115012A Withdrawn EP1715484A3 (fr) 1995-12-05 1996-12-05 Appareil et procédé de formation de signaux

Country Status (11)

Country Link
US (2) US5987066A (fr)
EP (6) EP1715485B1 (fr)
JP (1) JP3394127B2 (fr)
KR (1) KR100329456B1 (fr)
CN (4) CN100536014C (fr)
DE (4) DE69636916T2 (fr)
HK (1) HK1004500A1 (fr)
MX (1) MX9606099A (fr)
MY (1) MY112856A (fr)
SG (1) SG79210A1 (fr)
TW (1) TW311195B (fr)

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KR20040099945A (ko) * 2003-05-20 2004-12-02 삼성전자주식회사 디스크형 기록 매체로의 기록을 위한, 데이터 변조 방법및 그 장치와, 이에 사용되는 싱크 코드 삽입 방법 및 그장치와, 이를 구현하기 위한 프로그램을 기록한 기록 매체
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KR100749754B1 (ko) 2006-08-01 2007-08-17 삼성전자주식회사 직류 성분을 제어 가능한 인코딩과 디코딩 방법 및 이를이용한 데이터 처리 장치
JP5049870B2 (ja) * 2008-05-16 2012-10-17 株式会社日立製作所 記録方法、再生方法、情報記録媒体及びディジタル信号の生成方法
KR101436506B1 (ko) * 2008-07-23 2014-09-02 삼성전자주식회사 메모리 장치 및 메모리 데이터 프로그래밍 방법
JP5084686B2 (ja) * 2008-09-30 2012-11-28 キヤノン株式会社 画像形成装置、画像形成方法、プログラム及び記憶媒体
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CN1156930A (zh) 1997-08-13
EP1715486A3 (fr) 2008-03-05
EP0779623A3 (fr) 2001-02-28
SG79210A1 (en) 2001-03-20
CN1897142B (zh) 2010-08-11
DE69638200D1 (de) 2010-07-22
DE69636916T2 (de) 2007-10-31
EP1715484A2 (fr) 2006-10-25
DE69638178D1 (de) 2010-06-10
EP1715487A3 (fr) 2008-03-05
JP3394127B2 (ja) 2003-04-07
KR970056160A (ko) 1997-07-31
TW311195B (fr) 1997-07-21
CN1897144A (zh) 2007-01-17
DE69636916D1 (de) 2007-03-29
EP1403869A3 (fr) 2004-05-12
DE69632017D1 (de) 2004-05-06
MX9606099A (es) 1997-08-30
EP1715485B1 (fr) 2010-04-28
CN1897143A (zh) 2007-01-17
KR100329456B1 (ko) 2002-09-04
US5987066A (en) 1999-11-16
CN1897142A (zh) 2007-01-17
EP1715484A3 (fr) 2008-03-05
CN100536014C (zh) 2009-09-02
EP0779623A2 (fr) 1997-06-18
EP1715486A2 (fr) 2006-10-25
JPH09162857A (ja) 1997-06-20
EP1403869B1 (fr) 2007-02-14
EP0779623B1 (fr) 2004-03-31
EP1403869A2 (fr) 2004-03-31
USRE40312E1 (en) 2008-05-13
CN100499449C (zh) 2009-06-10
EP1715486B1 (fr) 2010-06-09
HK1004500A1 (en) 1998-11-27
EP1715485A3 (fr) 2008-03-05
CN1287546C (zh) 2006-11-29
DE69632017T2 (de) 2005-02-24
MY112856A (en) 2001-09-29
EP1715487A2 (fr) 2006-10-25

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