EP1662560A3 - Entfernung der Kanten einer Transferhalbleiterscheibe für Silizium-auf-Isolator - Anwendungen. - Google Patents
Entfernung der Kanten einer Transferhalbleiterscheibe für Silizium-auf-Isolator - Anwendungen. Download PDFInfo
- Publication number
- EP1662560A3 EP1662560A3 EP05257236A EP05257236A EP1662560A3 EP 1662560 A3 EP1662560 A3 EP 1662560A3 EP 05257236 A EP05257236 A EP 05257236A EP 05257236 A EP05257236 A EP 05257236A EP 1662560 A3 EP1662560 A3 EP 1662560A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- circumferential lip
- front surface
- wafer
- silicon
- transfer wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000012212 insulator Substances 0.000 title abstract 2
- 239000011521 glass Substances 0.000 abstract 3
- 239000012530 fluid Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 238000007517 polishing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02032—Preparing bulk and homogeneous wafers by reclaiming or re-processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/974—Substrate surface preparation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Grinding And Polishing Of Tertiary Curved Surfaces And Surfaces With Complex Shapes (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP08022218A EP2048701A3 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/998,289 US7402520B2 (en) | 2004-11-26 | 2004-11-26 | Edge removal of silicon-on-insulator transfer wafer |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08022218A Division-Into EP2048701A3 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
EP08022218A Division EP2048701A3 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
Publications (3)
Publication Number | Publication Date |
---|---|
EP1662560A2 EP1662560A2 (de) | 2006-05-31 |
EP1662560A3 true EP1662560A3 (de) | 2009-07-22 |
EP1662560B1 EP1662560B1 (de) | 2019-06-05 |
Family
ID=36113834
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08022218A Withdrawn EP2048701A3 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
EP05257236.9A Active EP1662560B1 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP08022218A Withdrawn EP2048701A3 (de) | 2004-11-26 | 2005-11-24 | Entfernung einer Kante einer SOI-Transferhalbleiterscheibe |
Country Status (4)
Country | Link |
---|---|
US (3) | US7402520B2 (de) |
EP (2) | EP2048701A3 (de) |
JP (2) | JP5455282B2 (de) |
TW (2) | TWI333259B (de) |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7402520B2 (en) * | 2004-11-26 | 2008-07-22 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
US20070148917A1 (en) * | 2005-12-22 | 2007-06-28 | Sumco Corporation | Process for Regeneration of a Layer Transferred Wafer and Regenerated Layer Transferred Wafer |
JP4913484B2 (ja) * | 2006-06-28 | 2012-04-11 | 株式会社ディスコ | 半導体ウエーハの研磨加工方法 |
KR100839355B1 (ko) * | 2006-11-28 | 2008-06-19 | 삼성전자주식회사 | 기판의 재생 방법 |
EP2015354A1 (de) * | 2007-07-11 | 2009-01-14 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zum Recycling eines Substrats, Herstellungsverfahren für einen beschichteten Wafer und dazu passendes recyceltes Donorsubstrat |
US8089055B2 (en) * | 2008-02-05 | 2012-01-03 | Adam Alexander Brailove | Ion beam processing apparatus |
CN101981664B (zh) * | 2008-03-31 | 2013-08-28 | Memc电子材料有限公司 | 蚀刻硅晶片边缘的方法 |
US7833907B2 (en) * | 2008-04-23 | 2010-11-16 | International Business Machines Corporation | CMP methods avoiding edge erosion and related wafer |
US20100022070A1 (en) * | 2008-07-22 | 2010-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing soi substrate |
JP5478166B2 (ja) * | 2008-09-11 | 2014-04-23 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
EP2359390A1 (de) * | 2008-11-19 | 2011-08-24 | MEMC Electronic Materials, Inc. | Verfahren und system zum entfernen des rands eines halbleiterwafers |
EP2213415A1 (de) | 2009-01-29 | 2010-08-04 | S.O.I. TEC Silicon | Vorrichtung zum Polieren der Kante eines Halbleitersubstrats |
EP2219208B1 (de) * | 2009-02-12 | 2012-08-29 | Soitec | Verfahren zur Rückgewinnung einer Oberfläche eines Substrats |
US8871109B2 (en) * | 2009-04-28 | 2014-10-28 | Gtat Corporation | Method for preparing a donor surface for reuse |
EP2246882B1 (de) | 2009-04-29 | 2015-03-04 | Soitec | Verfahren zur Übertragung einer Schicht von einem Donatorsubstrat auf ein Handhabungssubstrat |
WO2010150671A1 (en) * | 2009-06-24 | 2010-12-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate and method for manufacturing soi substrate |
DE102009030298B4 (de) * | 2009-06-24 | 2012-07-12 | Siltronic Ag | Verfahren zur lokalen Politur einer Halbleiterscheibe |
US8633090B2 (en) * | 2009-07-10 | 2014-01-21 | Shanghai Simgui Technology Co., Ltd. | Method for forming substrate with buried insulating layer |
US8318588B2 (en) * | 2009-08-25 | 2012-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
FR2950733B1 (fr) * | 2009-09-25 | 2012-10-26 | Commissariat Energie Atomique | Procede de planarisation par ultrasons d'un substrat dont une surface a ete liberee par fracture d'une couche enterree fragilisee |
WO2011043178A1 (en) * | 2009-10-09 | 2011-04-14 | Semiconductor Energy Laboratory Co., Ltd. | Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate |
FR2952224B1 (fr) * | 2009-10-30 | 2012-04-20 | Soitec Silicon On Insulator | Procede de controle de la repartition des contraintes dans une structure de type semi-conducteur sur isolant et structure correspondante. |
FR2953988B1 (fr) | 2009-12-11 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Procede de detourage d'un substrat chanfreine. |
FR2956822A1 (fr) | 2010-02-26 | 2011-09-02 | Soitec Silicon On Insulator Technologies | Procede d'elimination de fragments de materiau presents sur la surface d'une structure multicouche |
US9123529B2 (en) | 2011-06-21 | 2015-09-01 | Semiconductor Energy Laboratory Co., Ltd. | Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate |
JP5799740B2 (ja) | 2011-10-17 | 2015-10-28 | 信越半導体株式会社 | 剥離ウェーハの再生加工方法 |
JP2013115307A (ja) * | 2011-11-30 | 2013-06-10 | Sumitomo Electric Ind Ltd | Iii族窒化物複合基板の製造方法 |
US8853054B2 (en) | 2012-03-06 | 2014-10-07 | Sunedison Semiconductor Limited | Method of manufacturing silicon-on-insulator wafers |
JP2016046341A (ja) * | 2014-08-21 | 2016-04-04 | 株式会社荏原製作所 | 研磨方法 |
JP6086754B2 (ja) * | 2013-02-25 | 2017-03-01 | 株式会社ディスコ | ウェーハの加工方法 |
JP2014167996A (ja) * | 2013-02-28 | 2014-09-11 | Ebara Corp | 研磨装置および研磨方法 |
JP6214901B2 (ja) * | 2013-04-04 | 2017-10-18 | 株式会社ディスコ | 切削装置 |
US10464184B2 (en) * | 2014-05-07 | 2019-11-05 | Applied Materials, Inc. | Modifying substrate thickness profiles |
US20180033609A1 (en) * | 2016-07-28 | 2018-02-01 | QMAT, Inc. | Removal of non-cleaved/non-transferred material from donor substrate |
JP6723892B2 (ja) * | 2016-10-03 | 2020-07-15 | 株式会社ディスコ | ウエーハの加工方法 |
FR3074608B1 (fr) | 2017-12-05 | 2019-12-06 | Soitec | Procede de preparation d'un residu de substrat donneur, substrat obtenu a l'issu de ce procede, et utilisation d'un tel susbtrat |
TWI735275B (zh) * | 2020-07-03 | 2021-08-01 | 聯華電子股份有限公司 | 半導體結構的製作方法 |
CN112959211B (zh) * | 2021-02-22 | 2021-12-31 | 长江存储科技有限责任公司 | 晶圆处理装置和处理方法 |
FR3120159B1 (fr) | 2021-02-23 | 2023-06-23 | Soitec Silicon On Insulator | Procédé de préparation du résidu d’un substrat donneur ayant subi un prélèvement d’une couche par délamination |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5770465A (en) * | 1995-06-23 | 1998-06-23 | Cornell Research Foundation, Inc. | Trench-filling etch-masking microfabrication technique |
US20010029072A1 (en) * | 1998-04-23 | 2001-10-11 | Shin-Etsu Handotai Co., Ltd. | Method of recycling a delaminated wafer and a silicon wafer used for the recycling |
US6337241B1 (en) * | 1997-03-06 | 2002-01-08 | Kabushiki Kaisha Toshiba | Manufacturing method of a semiconductor memory device |
US20030219957A1 (en) * | 1999-11-29 | 2003-11-27 | Shin-Etsu Handotai Co., Ltd. | Method for reclaiming delaminated wafer and reclaimed delaminated wafer |
EP1427001A1 (de) * | 2002-12-06 | 2004-06-09 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Verfahren zum Recyceln einer Substratoberfläche mittels lokales Abdünnen |
US20040112866A1 (en) * | 2002-12-06 | 2004-06-17 | Christophe Maleville | Method for recycling a substrate |
Family Cites Families (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US616275A (en) * | 1898-12-20 | Reciprocating valve | ||
US5000113A (en) * | 1986-12-19 | 1991-03-19 | Applied Materials, Inc. | Thermal CVD/PECVD reactor and use for thermal chemical vapor deposition of silicon dioxide and in-situ multi-step planarized process |
US4721548A (en) * | 1987-05-13 | 1988-01-26 | Intel Corporation | Semiconductor planarization process |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP2839801B2 (ja) | 1992-09-18 | 1998-12-16 | 三菱マテリアル株式会社 | ウェーハの製造方法 |
JP3352340B2 (ja) | 1995-10-06 | 2002-12-03 | キヤノン株式会社 | 半導体基体とその製造方法 |
KR100227924B1 (ko) | 1995-07-28 | 1999-11-01 | 가이데 히사오 | 반도체 웨이퍼 제조방법, 그 방법에 사용되는 연삭방법 및 이에 사용되는 장치 |
JPH09270400A (ja) | 1996-01-31 | 1997-10-14 | Shin Etsu Handotai Co Ltd | 半導体ウェーハの製造方法 |
JPH09270401A (ja) | 1996-01-31 | 1997-10-14 | Shin Etsu Handotai Co Ltd | 半導体ウェーハの研磨方法 |
JP3620554B2 (ja) | 1996-03-25 | 2005-02-16 | 信越半導体株式会社 | 半導体ウェーハ製造方法 |
JP3321527B2 (ja) * | 1996-07-22 | 2002-09-03 | シャープ株式会社 | 半導体装置の製造方法 |
SG65697A1 (en) | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
US6054363A (en) | 1996-11-15 | 2000-04-25 | Canon Kabushiki Kaisha | Method of manufacturing semiconductor article |
US5821166A (en) | 1996-12-12 | 1998-10-13 | Komatsu Electronic Metals Co., Ltd. | Method of manufacturing semiconductor wafers |
US6033974A (en) | 1997-05-12 | 2000-03-07 | Silicon Genesis Corporation | Method for controlled cleaving process |
US6146979A (en) | 1997-05-12 | 2000-11-14 | Silicon Genesis Corporation | Pressurized microbubble thin film separation process using a reusable substrate |
US5920764A (en) | 1997-09-30 | 1999-07-06 | International Business Machines Corporation | Process for restoring rejected wafers in line for reuse as new |
SG71903A1 (en) | 1998-01-30 | 2000-04-18 | Canon Kk | Process of reclamation of soi substrate and reproduced substrate |
JP3271658B2 (ja) | 1998-03-23 | 2002-04-02 | 信越半導体株式会社 | 半導体シリコン単結晶ウェーハのラップ又は研磨方法 |
US6200199B1 (en) | 1998-03-31 | 2001-03-13 | Applied Materials, Inc. | Chemical mechanical polishing conditioner |
JP3932369B2 (ja) | 1998-04-09 | 2007-06-20 | 信越半導体株式会社 | 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ |
US6221774B1 (en) | 1998-04-10 | 2001-04-24 | Silicon Genesis Corporation | Method for surface treatment of substrates |
JP3358550B2 (ja) | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US6246667B1 (en) | 1998-09-02 | 2001-06-12 | Lucent Technologies Inc. | Backwards-compatible failure restoration in bidirectional multiplex section-switched ring transmission systems |
JP2000124092A (ja) | 1998-10-16 | 2000-04-28 | Shin Etsu Handotai Co Ltd | 水素イオン注入剥離法によってsoiウエーハを製造する方法およびこの方法で製造されたsoiウエーハ |
US6276997B1 (en) | 1998-12-23 | 2001-08-21 | Shinhwa Li | Use of chemical mechanical polishing and/or poly-vinyl-acetate scrubbing to restore quality of used semiconductor wafers |
JP2000223682A (ja) | 1999-02-02 | 2000-08-11 | Canon Inc | 基体の処理方法及び半導体基板の製造方法 |
DE19905737C2 (de) * | 1999-02-11 | 2000-12-14 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung einer Halbleiterscheibe mit verbesserter Ebenheit |
KR100343136B1 (ko) | 1999-03-18 | 2002-07-05 | 윤종용 | 이중 연마저지층을 이용한 화학기계적 연마방법 |
US6468923B1 (en) | 1999-03-26 | 2002-10-22 | Canon Kabushiki Kaisha | Method of producing semiconductor member |
FR2794891A1 (fr) | 1999-06-14 | 2000-12-15 | Lionel Girardie | Preparation de substrats aux techniques de collage direct |
US6376378B1 (en) | 1999-10-08 | 2002-04-23 | Chartered Semiconductor Manufacturing, Ltd. | Polishing apparatus and method for forming an integrated circuit |
US6566233B2 (en) * | 1999-12-24 | 2003-05-20 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing bonded wafer |
US20010039101A1 (en) * | 2000-04-13 | 2001-11-08 | Wacker Siltronic Gesellschaft Fur Halbleitermaterialien Ag | Method for converting a reclaim wafer into a semiconductor wafer |
US20020164876A1 (en) * | 2000-04-25 | 2002-11-07 | Walitzki Hans S. | Method for finishing polysilicon or amorphous substrate structures |
JP3991300B2 (ja) * | 2000-04-28 | 2007-10-17 | 株式会社Sumco | 張り合わせ誘電体分離ウェーハの製造方法 |
DE10058305A1 (de) | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Verfahren zur Oberflächenpolitur von Siliciumscheiben |
JP4156200B2 (ja) * | 2001-01-09 | 2008-09-24 | 株式会社荏原製作所 | 研磨装置及び研磨方法 |
US6448152B1 (en) | 2001-02-20 | 2002-09-10 | Silicon Genesis Corporation | Method and system for generating a plurality of donor wafers and handle wafers prior to an order being placed by a customer |
US6699356B2 (en) * | 2001-08-17 | 2004-03-02 | Applied Materials, Inc. | Method and apparatus for chemical-mechanical jet etching of semiconductor structures |
JP2003209075A (ja) * | 2002-01-15 | 2003-07-25 | Speedfam Co Ltd | ウェハエッジ研磨システム及びウェハエッジ研磨制御方法 |
JP3911174B2 (ja) * | 2002-03-01 | 2007-05-09 | シャープ株式会社 | 半導体素子の製造方法および半導体素子 |
FR2842648B1 (fr) | 2002-07-18 | 2005-01-14 | Commissariat Energie Atomique | Procede de transfert d'une couche mince electriquement active |
JP2004087522A (ja) * | 2002-08-22 | 2004-03-18 | Sumitomo Mitsubishi Silicon Corp | 半導体ウェーハの製造方法 |
JP4125148B2 (ja) * | 2003-02-03 | 2008-07-30 | 株式会社荏原製作所 | 基板処理装置 |
JP3534115B1 (ja) * | 2003-04-02 | 2004-06-07 | 住友電気工業株式会社 | エッジ研磨した窒化物半導体基板とエッジ研磨したGaN自立基板及び窒化物半導体基板のエッジ加工方法 |
JP4492054B2 (ja) | 2003-08-28 | 2010-06-30 | 株式会社Sumco | 剥離ウェーハの再生処理方法及び再生されたウェーハ |
JP2005072070A (ja) | 2003-08-28 | 2005-03-17 | Sumitomo Mitsubishi Silicon Corp | 剥離ウェーハの再生処理方法及び再生されたウェーハ |
US7276787B2 (en) * | 2003-12-05 | 2007-10-02 | International Business Machines Corporation | Silicon chip carrier with conductive through-vias and method for fabricating same |
US7402520B2 (en) | 2004-11-26 | 2008-07-22 | Applied Materials, Inc. | Edge removal of silicon-on-insulator transfer wafer |
JP2007019323A (ja) | 2005-07-08 | 2007-01-25 | Shin Etsu Handotai Co Ltd | ボンドウエーハの再生方法及びボンドウエーハ並びにssoiウエーハの製造方法 |
JP4715470B2 (ja) | 2005-11-28 | 2011-07-06 | 株式会社Sumco | 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ |
JP5314838B2 (ja) | 2006-07-14 | 2013-10-16 | 信越半導体株式会社 | 剥離ウェーハを再利用する方法 |
KR100839355B1 (ko) | 2006-11-28 | 2008-06-19 | 삼성전자주식회사 | 기판의 재생 방법 |
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2004
- 2004-11-26 US US10/998,289 patent/US7402520B2/en active Active
-
2005
- 2005-11-23 TW TW097114902A patent/TWI333259B/zh active
- 2005-11-23 TW TW094141169A patent/TWI364814B/zh active
- 2005-11-24 EP EP08022218A patent/EP2048701A3/de not_active Withdrawn
- 2005-11-24 EP EP05257236.9A patent/EP1662560B1/de active Active
- 2005-11-28 JP JP2005342585A patent/JP5455282B2/ja active Active
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2008
- 2008-02-19 US US12/033,727 patent/US7951718B2/en active Active
- 2008-07-22 US US12/177,752 patent/US7749908B2/en active Active
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2009
- 2009-07-22 JP JP2009171458A patent/JP2009283964A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5770465A (en) * | 1995-06-23 | 1998-06-23 | Cornell Research Foundation, Inc. | Trench-filling etch-masking microfabrication technique |
US6337241B1 (en) * | 1997-03-06 | 2002-01-08 | Kabushiki Kaisha Toshiba | Manufacturing method of a semiconductor memory device |
US20010029072A1 (en) * | 1998-04-23 | 2001-10-11 | Shin-Etsu Handotai Co., Ltd. | Method of recycling a delaminated wafer and a silicon wafer used for the recycling |
US20030219957A1 (en) * | 1999-11-29 | 2003-11-27 | Shin-Etsu Handotai Co., Ltd. | Method for reclaiming delaminated wafer and reclaimed delaminated wafer |
EP1427001A1 (de) * | 2002-12-06 | 2004-06-09 | S.O.I. Tec Silicon on Insulator Technologies S.A. | Verfahren zum Recyceln einer Substratoberfläche mittels lokales Abdünnen |
US20040112866A1 (en) * | 2002-12-06 | 2004-06-17 | Christophe Maleville | Method for recycling a substrate |
Also Published As
Publication number | Publication date |
---|---|
US20080138987A1 (en) | 2008-06-12 |
TWI333259B (en) | 2010-11-11 |
EP1662560B1 (de) | 2019-06-05 |
JP2009283964A (ja) | 2009-12-03 |
TWI364814B (en) | 2012-05-21 |
JP2006179887A (ja) | 2006-07-06 |
US7951718B2 (en) | 2011-05-31 |
US20060115986A1 (en) | 2006-06-01 |
EP2048701A3 (de) | 2009-04-29 |
TW200915477A (en) | 2009-04-01 |
US7749908B2 (en) | 2010-07-06 |
EP1662560A2 (de) | 2006-05-31 |
TW200629469A (en) | 2006-08-16 |
EP2048701A2 (de) | 2009-04-15 |
JP5455282B2 (ja) | 2014-03-26 |
US7402520B2 (en) | 2008-07-22 |
US20090061545A1 (en) | 2009-03-05 |
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