EP1656005A2 - Substrat avec via traversant et cablage connecté à ce via, et son procédé de fabrication - Google Patents

Substrat avec via traversant et cablage connecté à ce via, et son procédé de fabrication Download PDF

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Publication number
EP1656005A2
EP1656005A2 EP05256300A EP05256300A EP1656005A2 EP 1656005 A2 EP1656005 A2 EP 1656005A2 EP 05256300 A EP05256300 A EP 05256300A EP 05256300 A EP05256300 A EP 05256300A EP 1656005 A2 EP1656005 A2 EP 1656005A2
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EP
European Patent Office
Prior art keywords
hole
layer
penetrating
substrate
penetrating via
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP05256300A
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German (de)
English (en)
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EP1656005A3 (fr
Inventor
Takaharu c/o Shinko Electric Ind. Co. Ltd Yamano
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Publication of EP1656005A2 publication Critical patent/EP1656005A2/fr
Publication of EP1656005A3 publication Critical patent/EP1656005A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4608—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated comprising an electrically conductive base or core
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10287—Metal wires as connectors or conductors
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Definitions

  • the present invention generally relates to a substrate and a method for manufacturing the same, and particularly relates to a substrate having a penetrating via penetrating the base member and wiring connected to the penetrating via, and a method for manufacturing the same.
  • MEMS Micro Electro Mechanical Systems
  • a substrate such as an interposer mounting a semiconductor device therein.
  • the above described substrate adopts a configuration wherein a penetrating via is formed in a through-hole penetrating a base member so as to electrically connect wirings formed on corresponding sides of the base member.
  • Fig.1 is a cross-sectional view showing a substrate.
  • the substrate 10 comprises a silicon member 11, an insulating layer 13, penetrating vias 15, wirings 17 and 21, and solder resists 19 and 24.
  • the silicon member 11 through-holes 12 penetrating the silicon member 11 are formed.
  • the insulating layer 13 is formed so as to cover the surface of the silicon member 11 where the through-holes 12 are formed.
  • the insulating layer 13 is provided for insulating the penetrating via 15 and the wirings 17 and 21 from the silicon member.
  • the penetrating via 15 is provided in the through-hole 12 where the insulating layer 13 is formed.
  • the penetrating via 15 has a cylindrical shape and an end part 15a of the penetrating via 15 and a surface 13a of the insulating layer 13 are to be coplanar and another end part 15b of the penetrating via 15 and another surface 13b of the insulating layer 13 are also to be coplanar.
  • the penetrating via 15 is connected to the wirings 17 and 21 provided on corresponding sides of the silicon member 11.
  • the penetrating via 15 is provided for electrically connecting the wirings 17 and 21 formed on corresponding sides of the silicon member 11.
  • the penetrating via 15 is provided by the following steps of: forming a seed layer by a spattering method on an upper surface of the silicon member 11 where the insulating layer 13 is formed and depositing a conductive metal layer on the seed layer by the electrolytic plating method (See Patent Document 1, for example).
  • the wiring 17 which is connected to the edge part 15a of the penetrating via 15 comprises an external connection terminal 18.
  • the external connection terminal 18 is connected to another substrate such as a motherboard 26.
  • a solder resist layer 19 exposing the external connection terminal 18 is formed on the upper surface of the base member 11 so as to cover the wiring 17 except the external connection terminal 18.
  • the wiring 21 connected to the edge part 15b of the penetrating via 15 includes an external connection terminal 22.
  • MEMS or a semiconductor device 25 are mounted on the external connection terminal 22.
  • the solder resist 24 exposing the external connection terminal 22 is provided on an undersurface of the silicon member 11 so as to cover the wiring 21 except the external connection terminal 22.
  • the shape of the conventional penetrating via 15 is cylindrical, so that water infiltrates into a gap between the insulating layer 13 facing the penetrating via 15 and the penetrating via 15, and thereby, the penetrating via 15 is degraded and electrical connection reliability between the wirings 17, 21 and the penetrating via 15 is reduced.
  • a separat conductive metal layer on a surface of a seed layer is formed on inside edges of the through-hole 12 and the conductive metal layer is grown along the inside edges of the through-hole 12, and thus, a void (cavity) remains near the center of the penetrating via 15. Therefore, the electrical connection reliability of the penetrating via 15 connected to the wirings 17 and 21 is degraded.
  • the present invention provides a substrate having a penetrating via and wiring connected to the penetrating via, that substantially obviates one or more of the above problems.
  • an embodiment of the invention provides a substrate comprising a base member having a through-hole and a conductive metal filling the through-hole so as to form a penetrating via, wherein the penetrating via contains a conductive core member therein, and the conductive core member is disposed substantially at a central axis of the through-hole.
  • the conductive core member is disposed substantially at a central axis of the through-hole where the conductive core member is used as an electrode, and thereby, the conductive metal is grown from the conductive core member to the surface of the base member forming the through-hole; and thus a void (cavity) is prevented from remaining in the penetrating via.
  • a substrate which is composed of a base member having a through-hole; and conductive metal filling the through-hole so as to form a penetrating via, wherein the penetrating via includes a penetrating part provided in the through-hole; and protrusions protruding from the base member, which protrusions are connected to corresponding ends of the penetrating part, wherein the penetrating part contains a conductive core member therein, and the conductive core member is disposed substantially at a central axis of the through-hole.
  • the conductive core member which is disposed substantially at a central axis of the through-hole is used as an electrode, and thereby, the conductive metal is grown from the conductive core member to the surface of the base member forming the through-hole.
  • a void (cavity) is prevented from remaining in the penetrating via.
  • protrusions which are wider than the diameter of the penetrating part, are disposed on each end of the penetrating part, and thereby, water is prevented from infiltrating the gap between the base member facing the penetrating part and the base member.
  • the penetrating via is protected from being degraded.
  • a method for manufacturing a substrate comprises a base member having a through-hole, a conductive metal filling in the through-hole, and a penetrating via containing a conductive core member therein, the conductive core member being disposed substantially at a central axis of the through-hole, the method including the steps of disposing the conductive core member substantially at a central axis of the through-hole, and filling the through-hole with the conductive metal according to an electrolytic plating method by using the conductive member as an electrode.
  • the conductive core member is used as an electrode, the conductive metal is separated and grown from the conductive core member to the surface of the base member forming the through-hole by the electrolytic plating method so as to prevent a void (cavity) from remaining in the penetrating via.
  • Fig.2 is a cross-sectional view of the substrate according to the first embodiment of the present invention
  • Fig.3 is a cross-sectional view of the substrate shown in Fig.2 along the line C-C.
  • the Y ⁇ Y direction is a lengthwise direction of a conductive core member 58
  • the X ⁇ X direction in a direction perpendicular to the Y ⁇ Y is a transverse direction of a base member 51.
  • the substrate 50 is composed of a base member 51, insulating layers 53 and 65, a penetrating via 55, wiring 68, diffusion protecting layers 61 and 71, and a solder resist layer 75.
  • the substrate 50 is an interposer. As shown in Fig.2, for example, MEMS (Micro Electro Mechanical Systems) where a fine processing technology of manufacturing a semiconductor is used and a semiconductor device are mounted on the undersurface of the substrate 50, and another substrate such as a motherboard is mounted on the upper surface of the substrate 50 (the side on which the wiring 68 is formed).
  • MEMS Micro Electro Mechanical Systems
  • the base member 51 comprises a silicon member which is composed of silicon.
  • the thickness M1 of the base member 51 is, for example, 100 through 200 ⁇ m.
  • plural through-holes 52 are formed in the base member 51.
  • the diameter R2 of the through-hole 52 is, for example, more than 80 ⁇ m.
  • members other than the silicon member such as a glass member can be used.
  • an insulating member such as a glass member is used, it is not necessary to form the insulating layer 53.
  • the insulating layer 53 is formed so as to cover the surface of the base member 51 including through-holes 52.
  • the insulating layer 53 is provided for insulating the base member which is composed of silicon from the penetrating via 55.
  • the penetrating via 55 is composed of a penetrating part 57, a first protrusion i.e. a connection pad 59, a second protrusion, i.e., a wiring connecting part 56, and a conductive core member 58.
  • the penetrating via 55 is formed by separating a conductive metal and growing the penetrating via using the conductive core member 58 as an electrode.
  • a conductive metal for example, a Ni-Co alloy can be used as the conductive metal.
  • the penetrating part 57 having a cylindrical shape is formed in the through-hole 52 where the insulating layer 53 is formed.
  • the diameter of the penetrating part 57 is R1 (hereinafter, the diameter of the penetrating part 57 is referred to as "Diameter R1").
  • the Diameter R1 of the penetrating part 57 is substantially equal to the diameter R2 of the through-hole 52.
  • the wiring connecting part 56 is provided on the upper end of the penetrating part 57.
  • the wiring connecting part 56 protruding from the upper surface 51a of the base member 51 is wider than the diameter R1 of the penetrating part 57.
  • the width W1 of the wiring connecting part 56 is larger than the diameter R1 of the penetrating part 57 (W1 > R1).
  • the wiring connecting part 56 is unified with the penetrating part 57.
  • the wiring connecting part 56 is connected to the wiring 68 having an external connection terminal 69.
  • connection pad 59 is formed on the lower end of the penetrating part 57.
  • the connection pad 59 protruding from the undersurface 51b of the base member 51 is wider than the diameter R1 of the penetrating part 57.
  • the width W2 of the connection pad 59 is larger than the diameter R1 of the penetrating part 57 (W2 > R1).
  • the connection pad 59 is provided for mounting the MEMS and the semiconductor device.
  • the penetrating part 57, the wiring connecting part 56 and connection pad 59 are unified by the conductive metal.
  • the wiring connecting part 56 which is wider than the diameter R1 of the penetrating part 57 and protrudes from the surface 51a of the base member 51, is disposed on one end of the penetrating part 57, and the connection pad 59 which is wider than the diameter R1 of the penetrating part 57 and protrudes from the surface 51b of the base member 51, is disposed on the other end of the penetrating part 57, and thus, the insulating layer 53 is formed and water is prevented from infiltrating the gap between the base member 51 facing the penetrating part 57 and the penetrating part 57, and accordingly, the penetrating via 55 (especially penetrating part 57) is protected from being degraded.
  • the conductive core member 58 is a conductive linear material.
  • the conductive core member 58 is supported to be substantially coincident with the central axis D of the through-hole 52 by the diffusion protecting layer 61 which is a conductive member.
  • As the conductive core member 58 for example, gold wire formed by a wire bonding method can be used. When gold wire is used as the conductive core member 58, the diameter of the gold wire is, for example, 20 through 30 ⁇ m (25 ⁇ m is preferable).
  • the wire bonding method can be applied to the case where, for example, the diameter R2 of the through-hole 52 is more than 80 ⁇ m, and the depth of the through-hole 52 is 100 through 200 ⁇ m. It should be noted that the shape of the through-hole 52 to which the wire bonding method can be applied depends on the shape of the capillary tip of the wire bonding machine.
  • the length L2 of the conductive core member 58 should be shorter than the length L1 of the penetrating via 55 (L2 ⁇ L1). Accordingly, by setting the length L2 of the conductive core member 58 shorter than the length L1 of the penetrating via 55, the wiring 68 can be connected to the wiring connecting part 56 without being disturbed by the conductive core member 58 when the wiring 68 is disposed on the wiring connecting part 56. It should be noticed that the length L1 of the penetrating via 55 is the length from the end of the wiring connecting part 56 connected to the wiring 68 to the end of the connection pad 59 connected to the diffusion protecting layer 61.
  • the length L2 of the conductive core member 58 can be longer than the length L3 of the penetrating part 57, and the length L2 of the conductive core member 58 can be shorter than the length L1 of the penetrating via 55 (L3 ⁇ L2 ⁇ L1) and the conductive core member 58 can be disposed so as to penetrate the penetrating part 57.
  • the conductive core member 58 penetrating the penetrating part 57 is formed so as to be used as an electrode, and a conductive metal is grown from the conductive core member 58 to the surface of the base member 51 having the through-hole 52, and thus a void is prevented from remaining in the penetrating via 55 (especially, the penetrating part 57).
  • the diffusion protecting layer 61 is a conductive member formed on an end of the connection pad 59.
  • the diffusion protecting layer 61 is provided for improving the wettability of the solder and for preventing Cu contained in the penetrating via 55 from diffusing into the solder (drawing is omitted) connected to the connection pad 59.
  • the conductive core member 58 is connected to the diffusion protecting layer 61. Accordingly, the conductive core member 58 is connected to the diffusion protecting layer 61 so as to support the conductive core member 58 being kept substantially coincident with the central axis D of the through-hole 52.
  • the diffusion protecting layer 61 is used as a conductive member so that the penetrating via 55 can be connected to a semiconductor and another substrate via the diffusion protecting layer 61.
  • an Au/Ni/Au layer which is composed of an Au layer 62, a Ni layer 63, and an Au layer 64 can be used.
  • the Au layer 64 is a layer for connecting the conductive core member 58.
  • the Au layer 64 is formed on the part to be connected to the conductive core member 58 so as to obtain enough bonding strength between the diffusion protecting layer 61 and the gold wire.
  • the thickness of the Au layers 62 and 64 is, for example, 0.2 through 0.5 ⁇ m
  • the thickness of the Ni layer 63 is, for example, 2 through 5 ⁇ m.
  • a Pd/Ni/Pd layer and an Au/Pd/Ni/Pd/Au layer can be used as the diffusion protecting layer 61.
  • the insulating layer 65 is formed on the upper surface 51a of the base member 51 so as to expose the wiring connecting part 56.
  • a resin containing metal particles diffused and a resin containing metal compound particles diffused can be used as the insulating layer 65.
  • the resin for example, an epoxy resin and a polyimide resin can be used.
  • the metal for a catalyst of plating for example, palladium and platinum can be used. Especially, palladium is preferable.
  • the metal compound for example, palladium chloride and palladium sulfate can be used. It should be noted that, in the present embodiment, an epoxy resin containing the palladium particles diffused is used as the insulating layer 65.
  • an electroless plated layer (a seed layer 66 which will be described below)
  • an electroless plated layer (a seed layer 66 which is described below) can be formed directly on the insulating layer 65 according to an electroless plating method (see Fig.19). Accordingly, the manufacturing steps of the substrate 50 can be simplified.
  • the thickness M2 of the insulating layer 65 is, for example, 5 ⁇ m.
  • the wiring 68 is formed on the insulating layer 65 so as to be connected to the wiring connecting part 56.
  • the wiring 68 having an external connection terminal 69 is composed of a conductive metal part 67 and a seed layer 66.
  • the external connection terminal 69 is provided for being connected to a substrate such as a motherboard. Accordingly, by providing the external connection terminal 69 on the wiring 68, the external connection terminal 69 can be disposed corresponding to the external connection terminal disposed on the substrate such as a motherboard.
  • the conductive metal part 67 for example, Cu can be used. When Cu is used as the conductive metal part 67, the thickness M3 of the conductive metal part 67 is, for example, 3 through 10 ⁇ m.
  • the seed layer 66 for example, a Ni layer can be used. The thickness of the seed layer 66 is, for example, about 0.1 ⁇ m.
  • the solder resist layer 75 exposing the external connection terminal 69 is formed so as to cover the wiring 68 and the insulating layer 65 except the external connection terminal 69.
  • the solder resist layer 75 has an open part 76 exposing the external connection terminal 69.
  • the solder resist layer 75 is provided for protecting the wiring 68.
  • the diffusion protecting layer 71 is formed on the external connection terminal 69.
  • the diffusion protecting layer 71 is provided for improving wettability of the solder and protecting Cu contained in the wiring 68 form diffusing into the solder (drawing is omitted) connected to the external connection terminal 69.
  • the diffusion protecting layer 71 can be composed of, for example, a lamination layer including a Ni layer 72 and an Au layer 73.
  • the thickness of the Ni layer 72 is, for example, 2 through 5 ⁇ m, and the thickness of the Au layer 73 is, for example, 0.2 through 0.5 ⁇ m.
  • the diffusion protecting layer 71 a Ni/Pd layer and a Ni/Pd/Au layer (the Ni layer is the side to be connected to the external connection terminal) can be used.
  • Fig.4 is a plan view of the base member 51 used for manufacturing the substrate according to the present embodiment. It should be noted that "A" as shown in Fig.4 shows an area where the substrate 50 is formed (hereinafter, "A" is referred to as "Substrate Forming Area A"). As shown in Fig.4, in the present embodiment, a cylindrical silicon member having a plurality of the Substrate Forming Areas A is used as the base member 51 when the substrate 50 is formed. Accordingly, a silicon member having the Substrate Forming Areas A is used, the substrate 50 according to a manufacturing method which is described below is manufactured, and the base member 51 is diced so as to provide plural substrates 50 all at once; therefore, the productivity of manufacturing the substrate 50 can be improved.
  • an adhesive tape 92 is attached on a support board 91.
  • the support board 91 is provided for supporting the base member 51 so as to protect the base member 51 from being warped.
  • a glass member and a silicon member (more specifically a silicon wafer) can be used.
  • the thickness M4 of the support board is, for example, 725 ⁇ m.
  • the adhesive tape 92 is provided for bonding a metal foil 93 which is described below to the support board 91.
  • a thermo peal tape which loses adhesion when being heated can be used.
  • a thermal ablation agent can be used.
  • the metal foil 93 such as Cu is bonded on the support board 91 via the adhesive tape 92.
  • a dry film resist layer 94 having an open part 95 is formed on the metal foil 93.
  • the area on the metal foil 93 where the diffusion protecting layer 61 is formed is exposed from the open part 95 of the dry film resist layer 94.
  • an Au layer 62, a Ni layer 63 and an Au layer 64 are formed in turn on the metal foil 93 exposed from the open part 95 so as to form the diffusion protecting layer 61 according to the electrolytic plating method.
  • the thickness of the Au layers 62 and 64 are, for example, 0.2 through 0.5 ⁇ m, and the thickness of the Ni layer 63 is, for example, 2 through 5 ⁇ m. Accordingly, by the electrolytic plating method, a diffusion protecting layer superior to a layer formed by an electroless plating method can be formed. Then, as shown in Fig. 9, the dry film resist layer 94 is removed by the resist stripper.
  • a resist layer 96 which is not in the exposure state is formed so as to cover the diffusion protecting layer 61 and the metal foil 93.
  • the resist layer 96 contains a resist material having adhesion, and for example, a photosensitive dry film resist and a liquid resist can be used as the resist layer 96.
  • the base member 51 where the through-hole 52 is formed can be fixed on the support board 91 via the resist layer 96 (as shown in Fig.11).
  • the thickness of the resist layer 96 is, for example, 10 through 15 ⁇ m.
  • an epoxy adhesive and a polyimide adhesive can be used if the adhesives can be dissolved by some treatment liquid.
  • the through-hole 52 having a diameter R2 of an aperture is formed in the base member 51 and the insulating layer 53 is formed so as to cover the surface (including a part of the base member 51 corresponding to the through-hole 52) of the base member 51 , the base member 51 being disposed on the resist layer 96 having adhesion and fixed on the support board 91 via the resist layer 96.
  • the through-hole 52 can be formed, for example, by one of drill processing, laser processing, and anisotropic etching.
  • the diameter R2 of the aperture of the through-hole 52 is, for example, more than 80 ⁇ m.
  • the insulating layer 53 for example, an oxidized layer (SiO 2 ) formed by a CVD method and a thermal oxidized layer (SiO 2 ) formed by an oxidizing furnace can be used.
  • the thickness M1 of the base member 51 is, for example, 150 ⁇ m.
  • the resist layer 96 exposed on the through-hole 52 is dissolved so as to form a space 97.
  • the space 97 is wider than the diameter of the aperture of the through-hole 52; thus the width W4 of the space 97 is greater than the diameter R2 of the aperture of the through-hole 52 (W4 > R2).
  • the width W4 of the space 97 is substantially equal to the width W2 of the connection pad 59.
  • the diffusion protecting layer 61 is exposed from the space 97.
  • a dip development wherein the structure as shown in Fig.12 is dipped in the developer and a spray development wherein the developer is sprayed onto the through-hole 52 like a shower can be used.
  • the wetting time of the developer is controlled so as to form the space 97.
  • the spraying pressure is 2.0 kgf/cm 2
  • the temperature is in the range 25 through 30 °C
  • the spraying time is 6 min. (when the thickness of the resist layer 96 is in the range 10 through 15 ⁇ m).
  • a thermal treatment is performed on the structure shown in Fig.12, and a polymerization reaction is carried out on the resist layer 96 which is not in the exposure state so as to harden the resist layer 96 (the first resist layer hardening step). Accordingly, the resist layer 96 is hardened so as to have tolerance for the plating solution.
  • a dry film resist layer 101 having an open part 102 exposing the through-hole 52 is formed on the insulating layer 53 provided on the upper surface 51a of the base member 51.
  • the diameter W5 of the aperture of the open part 102 is wider than the diameter R2 of the aperture of the through-hole 52 (W5 > R2).
  • the diameter W5 of the aperture of the open part 102 is substantially equal to the width W1 of the wiring connecting part 56.
  • a gold wire used as the conductive core member 58 is connected to the Au layer 64 so as to be positioned substantially at the central axis D of the through-hole 52 (the conductive core member disposing step) .
  • Fig.33 is a diagram showing a growth process of the conductive metal.
  • the Y ⁇ Y direction is a longitudinal direction of the conductive core member 58
  • the X ⁇ X direction is a horizontal direction perpendicular to the Y ⁇ Y direction.
  • F ⁇ F is a direction in which the conductive metal grows (hereinafter, F ⁇ F is referred to as "Direction F").
  • Electric current is passed through the metal foil 93, and by using the conductive core member 58 as an electrode, according to the electrolytic plating method, the conductive metal 104 is separated and grown so as to fill the space 97, through-hole 52, and the open part 102 (the conductive metal filling step).
  • the conductive metal grows from the conductive core member 58 to the surface 51c of the base member 51 corresponding to the through-hole 52; thus a void (cavity) is prevented from remaining in the penetrating part 57 (corresponding to the conventional cylindrical penetrating via 15).
  • a Ni-Co alloy can be used as the conductive metal 104.
  • the Ni-Co alloy is separated and grown so as to fill the space 97, through-hole 52, and the open part 102, and accordingly, the penetrating via 55 is formed. And thus, the penetrating via 55 is formed in a shorter time than the time the penetrating via 55 is formed by filling the space 97, through-hole 52, and the open part 102 with Cu. Accordingly, the productivity of manufacturing the substrate 50 can be improved.
  • the conductive metal 104 can also be formed by the following steps: in the conductive metal filling step, Ni is separated on the surface of the conductive core member 58 by the electrolytic plating method so as to cover the surface of the conductive core member 58 and the surface of the diffusion protecting layer 61, and then, Cu is separated so as to fill the space 97, through-hole 52 and the open part 102.
  • the conductive metal 104 protruding from the dry film resist layer 101 is removed by grinding so that the conductive metal 104 and the surface of the dry film resist layer 104 are coplanar. Accordingly, the following components are formed all at once: the connection pad 59 (the first protrusion) having a width W2 in the space 97, the penetrating part 57 having a diameter R1 in the through-hole 52, and the wiring connecting part 56 (the second protrusion) having a width W1 in the open part 102; thus the penetrating via 55 containing the conductive core member 58 therein is formed. It should be noted that the width W1 of the wiring connecting part 56 and the width W2 of the connection pad 59 are greater than the diameter R1 of the penetrating part 57 (W1 > R1, W2 > R1).
  • connection pad 59 and the wiring connecting part 56 which are wider than the diameter R1 of the penetrating part 57, are connected to the penetrating part 57, and thereby, water is prevented from infiltrating a gap between the base member 51 facing the penetrating part 57 and the penetrating part 57; therefore, the penetrating via 55 is prevented from being degraded.
  • the dry film resist layer 101 is removed by the resist stripper. And then, as shown in Fig.18, an insulating layer 65 having an open part 103 exposing the wiring connecting part 56 is formed on the upper surface 51a of the base member 51.
  • the insulating layer 65 for example, a resin material containing palladium therein can be used.
  • the thickness M2 of the insulating layer 65 is, for example, 5 ⁇ m.
  • a seed layer 66 is formed on an upper surface 65a of the insulating layer 65 and on lateral sides 65b of the insulating layer 65.
  • a desmear treatment is performed on the surface of the resin (the insulating layer) in advance so as to roughen the surface, and then a palladium activation treatment is performed on the surface of the resin.
  • the palladium activation treatment is dipping a sample to be plated in one of a catalyzing treatment solution and an accelerating treatment solution, and the palladium to be a core of the electroless plating is separated on the surface of the resin.
  • the plated layer cannot be formed by the electroless plating method until the palladium activation treatment is performed. Therefore, in the conventional technology, the manufacturing step is very troublesome.
  • an epoxy resin material is applied to the insulating layer 65; thus it is not necessary to perform the desmear treatment and the palladium activation treatment in advance on the insulating layer 65, and accordingly, the seed layer 66 can be formed directly on the insulating layer 65 by the electroless plating method.
  • the manufacturing steps of the substrate 50 can be simplified.
  • a Ni layer can be used as the seed layer 66.
  • a Ni-B layer can be formed.
  • a dry film resist layer 105 having an open part 106 is formed on the seed layer 66.
  • the open part 106 corresponds to the area where the wiring 68 is formed.
  • the thickness of the dry film resist layer 105 is, for example, 10 through 15 ⁇ m.
  • the wiring connecting part 56 and the seed layer 66 are used as an electrode, and according to the electrolytic plating method, the conductive metal part 67 is formed so as to fill the open parts 103 and 106. Accordingly, the conductive metal part 67 and the penetrating via 55 are electrically connected.
  • the conductive metal part 67 for example, Cu can be used.
  • the dry film resist layer 105 is removed by the resist stripper after the conductive metal part 67 is formed.
  • a dry film resist layer 108 is formed on the structure shown in Fig. 21 so as to expose the conductive metal part 67 corresponding to the area B where the external connection terminal is formed.
  • the dry film resist layer 108 has an open part 109 exposing the conductive metal part 67 corresponding to the area B.
  • a Ni layer 72 and an Au layer 73 are separated and grown in turn on the conductive metal part 67 exposed from the open part 109 so as to form a diffusion protecting layer 71.
  • the thickness of the Ni layer 72 is, for example, 2 through 5 ⁇ m
  • the thickness of the Au layer 73 is, for example, 0.2 through 0.5 ⁇ m. Accordingly, the diffusion protecting layer 71 is formed by the electrolytic plating method; thus the diffusion protecting layer having a layer superior to the layer formed by the electroless plating method can be formed.
  • the dry film resist layer 108 is removed after the second diffusion protecting layer 71 is formed.
  • a dry film resist layer 111 is formed so as to cover the conductive metal part 67 and the diffusion protecting layer 71. Then, as shown in Fig.25, the seed layer 66 exposed on the insulating layer 65 is removed by etching. Accordingly, the wiring 68 having the external connection terminal 69, which wiring is composed of the seed layer 66 and the conductive metal part 67, is formed. As shown in Fig.26, the dry film resist layer 111 is removed by the resist stripper.
  • a heat-resistant tape 114 is attached so as to cover the upper surface 65a of the insulating layer 65, the wiring 68, and the diffusion protecting layer 71.
  • the heat-resistant tape 114 has tolerance for the etchant. Accordingly, the heat-resistant tape 114 is provided so as to cover the upper surface 65a of the insulating layer 65, wiring 68, and the diffusion protecting layer 71, and thereby, the wiring 68 and the diffusion protecting layer 71 are protected from the thermal treatment (see Fig.28) performed in removing the support board 91 from the base member 51. Moreover, the wiring 68 is protected from being etched when the metal foil 93 is removed by etching (see Fig.29).
  • a PET and a PEN which are flame retardant can be used. It should be noted that the heat-resistant tape 114 is only provided so as to cover at least the wiring 68 and the diffusion protecting layer 71.
  • the adhesive tape 92 and the support board 91 are removed from the base member 51 by heating (the thermal treatment) the structure shown in Fig.27.
  • the adhesive tape 92 a thermo peal tape is used which loses adhesion when being heated.
  • the heating temperature is 150 °C, and the heating time is 30 min.
  • the metal foil 93 is removed by etching. Accordingly, the resist layer 94 and the diffusion protecting layer 61 are exposed.
  • the wiring 68 is covered by the heat-resistant tape 114 having tolerance for the etchant, and thereby, the wiring 68 is not etched when removing the metal foil 93.
  • the resist layer 94 is removed.
  • the heat-resistant tape 114 is removed.
  • a solder resist layer 75 is formed so as to expose the diffusion protecting layer 71 and to cover the wiring 68 and the insulating layer 65.
  • the solder resist layer 75 has an open part 76 exposing the diffusion protecting layer 71.
  • the conductive metal 104 is grown from the conductive core member 58 to the surface 51c of the base member 51 having through-hole 52, to be the penetrating via 55. Accordingly, the void is prevented from remaining in the penetrating via 55; thus the electric connection reliability between the wiring 68 and the penetrating via 55 can be improved.
  • the wiring connecting part 56 which is wider than the diameter R1 of the penetrating part, is connected to one end of the penetrating part 57, and the connection pad 59 which is wider than the diameter R1 of the penetrating part 57 is connected to the other end of the penetrating part 57, and thereby, water is prevented from infiltrating the gap between the base member 51 facing the penetrating part 57 and the penetrating part 57; thus the penetrating via 55 is protected from being degraded, and accordingly, the electric connection reliability between the wiring 68 and the penetrating via 55 can be improved.
  • the wiring 68 is connected to the wirings connecting part 56 which is wider than the diameter R1 of the penetrating part 57; thus the wiring 68 is easily connected to the wirings connecting part 56.
  • FIG.34 is a cross-sectional view showing the substrate 120 according to the second embodiment of the present invention.
  • G is a central axis of a through-hole 122 (hereinafter the central axis is referred to as "Central Axis G").
  • the substrate 120 includes a base member 51, an insulating layer 53, diffusion protecting layers 61 and 71, penetrating vias 125, wirings 127, and a solder resist layer 131.
  • the base member 51 has plural through-holes 122. Further, on the surface of the base member 51 including the through-holes 122, the insulating layer 53 is formed.
  • the penetrating via 125 disposed in the through-hole 122 is composed of a conductive metal part 124 and a conductive core member 123. The shape of the penetrating via 125 is to be cylindrical.
  • the conductive core member 123 is disposed in a position substantially coinciding with Central Axis G of the through-hole 122 by the diffusion protecting layer 61.
  • the length L4 of the conductive core member 123 is to be substantially equal to the depth N of the through-hole 122.
  • the length L4 of the conductive core member is set substantially equal to the depth N of the thorough-hole 122; and by using the conductive core member 123 as an electrode, the conductive metal part 124 is grown from the conductive core member 123 to the surface of the base member 51 having the through-holes 122 so as to fill the through-hole 122, and thereby, a void is prevented from remaining in the penetrating via 125. Accordingly, the electric connection reliability between the wiring 127 and the penetrating via 125 can be improved.
  • the conductive core member for example, a gold wire formed by the wire bonding method can be used.
  • the thickness of the gold wire can be, for example, 20 through 30 ⁇ m (preferably, 25 ⁇ m).
  • the conductive metal part 124 is provided so as to fill the thorough-hole 122 where the conductive core member 123 is disposed.
  • a Ni-Co alloy can be used as for the conductive metal part 124.
  • the diffusion protecting layer 61 is provided on the lower end of the penetrating via 125.
  • the diffusion protecting layer 61 is composed of an Au layer 62, a Ni layer 63, and an Au layer 64.
  • the conductive metal part 124 and the conductive core member 123 are connected to the Au layer 64.
  • the wiring 127 is provided on the surface 51a of the base member 51 where the insulating layer 53 is formed.
  • the wiring 127 having an external connection terminal 128 is connected to the upper end of the penetrating via 125.
  • the diffusion protecting layer 71 is formed on the external connection terminal 128.
  • the diffusion protecting layer 71 is composed of a Ni layer 72 and an Au layer 73.
  • the solder resist layer 131 is formed so as to expose the diffusion protecting layer 71 and to cover the upper surface 51a of the base member 51 on which the insulating layer 53 is formed and the wiring 127.
  • the solder resist layer 131 has an open part 132 exposing the external connection terminal 128.
  • the conductive metal is separated and the conductive metal part 124 is grown from the conductive core member 123 to the surface of the base member 51 including the through-hole 122; thus a void is prevented from remaining in the penetrating via 125, and accordingly, the electric connection reliability between the wiring 127 and the penetrating via 125 can be improved.
  • the present invention can be applied to a substrate wherein a void is prevented from remaining in the penetrating via, and thereby, the penetrating via is protected from being degraded, and thus, the electric connection reliability of the penetrating via connected to the wiring can be improved; and can be applied to the method for manufacturing the same.
  • the conductive core member is supported by the diffusion protecting layer so as to set the conductive core member substantially at a central axis of the through-hole.
  • the length of the conductive core member is substantially equal to the depth of the through-hole, and the through-hole is filled with the conductive metal so as to prevent a void (cavity) from remaining in the penetrating via.
  • the substrate as above described includes wiring having an external connection terminal connected to an end of the penetrating via.
  • the wiring is connected to the penetrating via wherein the void is prevented from remaining inside the penetrating via, so that the electric connection reliability between the wiring and the penetrating via can be improved.
  • the length of the conductive core member is shorter than the length of the penetrating via; thus the wiring is easily connected to the penetrating via without being obstructed by the conductive core member.
  • a conductive member is provided for supporting the conductive core member so as to set the conductive core member substantially at a central axis of the through-hole.
  • the diffusion protecting layer is used as the conductive member, so that a semiconductor device and another substrate can be connected to the penetrating via through the diffusion protecting layer.
  • the second protrusion is connected to wiring having an external connection terminal.
  • the wiring is connected to the penetrating via wherein the void is prevented from remaining inside the penetrating via, and the electric connection reliability between the wiring and the penetrating via can be improved.

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EP05256300A 2004-11-08 2005-10-10 Substrat avec via traversant et cablage connecté à ce via, et son procédé de fabrication Withdrawn EP1656005A3 (fr)

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KR20060053282A (ko) 2006-05-19
US20060097378A1 (en) 2006-05-11
US7365436B2 (en) 2008-04-29
JP2006135175A (ja) 2006-05-25
CN100517679C (zh) 2009-07-22
JP4369348B2 (ja) 2009-11-18
CN1779964A (zh) 2006-05-31
EP1656005A3 (fr) 2007-11-14
TWI384604B (zh) 2013-02-01

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