EP1631983A1 - Verfahren zur gleichzeitigen herstellung eines mit einer nutzschicht bedeckten substratpaars. - Google Patents
Verfahren zur gleichzeitigen herstellung eines mit einer nutzschicht bedeckten substratpaars.Info
- Publication number
- EP1631983A1 EP1631983A1 EP04767237A EP04767237A EP1631983A1 EP 1631983 A1 EP1631983 A1 EP 1631983A1 EP 04767237 A EP04767237 A EP 04767237A EP 04767237 A EP04767237 A EP 04767237A EP 1631983 A1 EP1631983 A1 EP 1631983A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- useful layer
- silicon
- useful
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 131
- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000005693 optoelectronics Effects 0.000 claims abstract description 5
- 238000002513 implantation Methods 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 21
- 239000010703 silicon Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 19
- 230000003313 weakening effect Effects 0.000 claims description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000010432 diamond Substances 0.000 claims description 14
- 229910003460 diamond Inorganic materials 0.000 claims description 13
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 10
- 150000001875 compounds Chemical class 0.000 claims description 9
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 230000010070 molecular adhesion Effects 0.000 claims description 8
- 229910052594 sapphire Inorganic materials 0.000 claims description 8
- 239000010980 sapphire Substances 0.000 claims description 8
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000010453 quartz Substances 0.000 claims description 5
- 229910052727 yttrium Inorganic materials 0.000 claims description 5
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910000676 Si alloy Inorganic materials 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910002076 stabilized zirconia Inorganic materials 0.000 claims description 3
- 238000004026 adhesive bonding Methods 0.000 claims description 2
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 159
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 17
- 239000003351 stiffener Substances 0.000 description 17
- 230000007547 defect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 238000004064 recycling Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 3
- MARUHZGHZWCEQU-UHFFFAOYSA-N 5-phenyl-2h-tetrazole Chemical compound C1=CC=CC=C1C1=NNN=N1 MARUHZGHZWCEQU-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000032798 delamination Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910017214 AsGa Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000007872 degassing Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000010849 ion bombardment Methods 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Definitions
- the present invention relates to a process for the concomitant production of at least two structures, each comprising at least one useful layer transferred onto a substrate for applications in the fields of electronics, optoelectronics or optics.
- Several methods of layer transfer are known from the state of the art. One of them consists in implanting atomic species under the surface of a source substrate, so as to create there a weakening zone which delimits a thin layer. Next, the free face of this thin layer is brought into contact with a support substrate, then detachment of said thin layer from the rest of the source substrate and its transfer to said support substrate.
- Smart Cut For the description of this process, reference may be made to the literature concerning the process known under the trademark "Smart Cut".
- This type of process generates a residue of source substrate which must be recycled so that it can be reused during a new layer transfer. This involves polishing and finishing operations that can be long and costly, both • the price of the equipment used to perform by the time spent achieving them. In addition, for certain extremely hard materials such as silicon carbide, the above-mentioned recycling steps can prove to be very long and tedious.
- the object of the present invention is to solve the aforementioned drawbacks and to provide an economical layer transfer method, limiting the number of source substrates to be recycled.
- the invention relates to a process for the concomitant production of at least one pair of structures, each comprising at least one useful layer transferred onto a substrate, for applications in the fields of electronics, optoelectronics or 1 Optical.
- this method comprises the following stages consisting in: a) preparing a structure known as of row 1, comprising a useful layer transferred onto a support substrate, b) forming a weakening zone inside said useful layer of the rank 1 structure, by implantation of atomic species, so as to define there two layers, called “useful front layer” and “rear useful layer", the rear useful layer being located between, said useful layer, before and said support substrate, c) adhering a stiffening substrate to the free surface of said useful front layer, d) detaching the stack of layers obtained in step c), along said embrittlement zone, by applications constraints, so as to obtain two so-called rank 2 structures, the first comprising at least said support substrate and said rear working layer and the second comprising at least said stiffening substrate and said useful layer the front.
- the cycle of the operations described in steps b) to d) is repeated, using as starting structure at least one of the structures of rank 2 and using stiffening substrates and it is repeated, where appropriate, this cycle of operations at least once, from at least one of the structures of the following row (s).
- the transfer operation from step a) comprises a bonding step, the useful layer coming directly into contact with the support substrate, or one or more intermediate layers being inserted between the useful layer and the support substrate.
- the adhesion operation of step c) is carried out by bonding, the stiffening substrate coming directly into contact with the free surface of the useful front layer, or else at least one intermediate layer being inserted between the substrate.
- the intermediate layer is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity, diamonds and constrained silicon;
- the intermediate layer is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity, diamond;
- At least one of the elements among the support substrate, the stiffening substrate and the useful layer is made of a semiconductor material;
- the support substrate comprises at least one layer of a material chosen from silicon, silicon carbide, sapphire, diamond, germanium, quartz, stabilized zircane yttrium and an alloy of silicon carbide;
- the stiffening substrate comprises at least one layer of a material chosen from silicon,
- the support substrate is made of monocrystalline or polycrystalline silicon, the useful layer of monocrystalline silicon, the stiffening substrate of silicon, mono or polycrystalline ⁇ lin, the intermediate layer and the intermediate layer of silicon oxide; the useful layer of the rank 1 structure is obtained by forming an initial weakening zone inside a source substrate, this initial weakening zone separating said useful layer from the rest of the source substrate, by applying this source substrate on said support substrate then by detachment of said remainder along the initial embrittlement zone; - The initial embrittlement zone is formed by implantation of atomic species or is a porous zone.
- FIGS. 1A to 1C are diagrams illustrating the different stages of a process obtaining a structure comprising a useful layer transferred onto a support substrate
- FIGS. 2A to 2C are diagrams illustrating an alternative embodiment of the method shown in FIGS. 1A to IC according to which a structure is obtained comprising a useful layer transferred onto a substrate using an intermediate layer
- FIGS. 1A to 1C are diagrams illustrating the different stages of a process obtaining a structure comprising a useful layer transferred onto a support substrate
- FIGS. 2A to 2C are diagrams illustrating an alternative embodiment of the method shown in FIGS. 1A to IC according to which a structure is obtained comprising a useful layer transferred onto a substrate using an intermediate layer
- FIGS. 3A to 3F are diagrams illustrating the different stages of a first embodiment of the method for the concomitant production of at least one pair of structures according to the invention
- Figures 4A to 4F are diagrams illustrating an alternative embodiment of the method shown in Figures 3A to 3F
- - And Figures 5A to 5F are diagrams illustrating the different stages of a second embodiment of the method according to the invention.
- the process according to the invention is carried out using a first structure 5 or 5 ′, called a row
- a source substrate 1 internally having a weakening zone 4 delimiting two parts, namely a useful layer 11 and the rest 12 of this source substrate or rear part.
- this weakening zone 4 is called “initial weakening zone”.
- the source substrate 1 has a face 13, called “front face”, intended to come into contact with a support substrate 2 which will be described later.
- the source substrate 1 is chosen from semiconductor materials, in particular those commonly used for applications in the fields of electronics, optoelectronics or optics.
- it may be silicon, silicon carbide, sapphire, diamond, germanium, silicon-germanium, compounds III-V and compounds II-VI.
- Compounds III-V are compounds of which one of the elements belongs to column III of the periodic table and the other to column V, such as for example, gallium nitride (GaN), gallium arsenide (AsGa) or indium phosphide (InP).
- Compounds II-VI are compounds of which one of the elements belongs to column II of the periodic table and the other to column VI, such as for example, cadmium telluride (CdTe).
- the source substrate 1 can also be a composite substrate, that is to say a substrate composed of a solid part, for example made of silicon, on which rests a buffer layer, for example made of silicon-germanium (SiGe).
- the initial embrittlement zone 4 can be obtained by implantation of atomic species.
- implantation of atomic species we mean any bombardment of atomic species, molecular or ionic, capable of introducing these species into a material, with a maximum concentration of these species located at a determined depth relative to the bombarded surface 13.
- the implantation of the atomic species in said source substrate 1 can be carried out by for example, using an ion beam implanter or a plasma immersion implanter.
- this implantation is carried out by ion bombardment.
- the implanted ionic species is hydrogen.
- Other ionic species can advantageously be used alone or in combination with hydrogen, such as rare gases (helium for example).
- the effect of this implantation is to create in the volume of the source substrate 1 and at an average depth of ion penetration, the initial weakening zone 4 which extends substantially parallel to the plane of the front face 13.
- the useful layer 11 s' extends between the front face 13 and this weakening zone 4.
- the initial embrittlement zone 4 can also consist of a porous layer obtained for example as described in document EP-0 849 788.
- the support substrate 2 has a role of mechanical support and therefore generally has a thickness of at least about 300 micrometers. It preferably consists of any mono or polycrystalline semiconductor material commonly used in the aforementioned applications.
- This support substrate 2 can be a solid monolayer substrate chosen for example from silicon, silicon carbide, sapphire, diamond, germanium, quartz, stabilized zircane yttrium (Zr0 2 (Y0 3 )) or an alloy of silicon carbide.
- the support substrate 2 has a face 20, called "front face" because it is intended to receive the front face 13 of the source substrate 1. Then, as shown in FIG.
- the front face 13 of the useful layer 11 is bonded directly to the support substrate 2, that is to say without an intermediate layer.
- this bonding is carried out by molecular adhesion.
- the remainder 12 is detached along the initial embrittlement zone 4 by application of stresses (see FIG. IC).
- One of the following techniques is used for this purpose: application of constraints of mechanical or electrical origin, chemical etching or supply of energy, for example the use of a laser, of microwaves , inductive heating, heat treatment in an oven.
- FIGS. 2A to 2C illustrate an alternative embodiment of the method which has just been described in conjunction with FIGS. 1A to IC but which differs from this in that at least one intermediate layer 3 is inserted between the useful layer 11 and the support substrate 2.
- a single intermediate layer 3 has been shown in FIGS. 2A to 2C and in FIGS. 5A to 5F.
- each of these intermediate layers 3 is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity and diamond.
- This intermediate layer 3 can be obtained by chemical vapor deposition techniques or any other technique known to those skilled in the art, carried out either on the front face 20 of the support substrate 2, or on the front face 13 of the source substrate 1 , either on these two front faces and this, before these two substrates are applied one against the other.
- this intermediate layer 3 is an oxide layer, it can also be obtained by thermal oxidation of one or the other of the two substrates 1 or 2.
- a first structure of rank 1, referenced 5 ′ is obtained, comprising the source substrate 2, the useful layer 11 and the intermediate layer 3 inserted between them.
- postponed for a rank 1 structure means that a cc ⁇ iche. useful layer is transferred onto a support substrate by a process comprising at least one bonding step, in the presence or absence of at least one intermediate layer 3.
- the useful layer 11 can be transferred on the support substrate 2 by the BESOI technique mentioned above, in the presence or absence of the intermediate layer 3.
- FIGS. 3A to 3C illustrate a complete cycle of steps of a first embodiment of the method in accordance with invention allowing the concomitant production of a pair of structures each comprising a useful layer transferred onto a substrate.
- a weakening zone 6 is formed inside the useful layer 11 of the structure 5 of rank 1 obtained previously, by implantation of atomic species according to the technique described above for the obtaining the initial embrittlement zone 4.
- the next step illustrated in FIG. 3B consists in making a stiffening substrate 71 adhere to the free surface 130 of said front useful layer 110, by bonding, preferably by direct bonding by molecular adhesion.
- the last step of the cycle illustrated in FIG. 3C consists in detaching the stack of layers obtained in the previous step, along the said .fragi area 1 s-ati on 6, by applying constraints, according to techniques known to a person skilled in the art and described previously together with FIGS. IC and 2C. Two structures 51 and 52 are thus obtained, called row 2 structures.
- the first structure 51 comprises the support substrate 2 and the rear useful layer 120 and the second structure 52 comprises the stiffening substrate 71 and the front useful layer 110.
- the layer useful 11 must have a sufficient thickness so that after the detachment step the two useful layers 110 and 120 obtained do not exhibit any defects or blisters.
- the thicknesses of the two useful layers 110 and 120 can be identical or different depending on the implantation depth of the atomic species and therefore on the location of the embrittlement zone 6.
- the two structures 521 and 522 of rank 3 resulting from the structure 52 of rank 2 respectively comprise the stiffener 71 and the layer u rear tile 111 for the first and the stiffener 72 and the front useful layer 112 for the second, while the two structures 511 and 512 of rank 3 resulting from the structure 51 of rank 2 respectively comprise the stiffener 73 and the useful front layer 122 for the first and the support substrate 2 and the rear useful layer 121 for the second.
- Figures _4A to 4F illustrate an alternative embodiment of the method which differs from that described jointly with Figures 3A to 3F in that at least one intermediate layer 8, respectively 8 ", are inserted between the stiffening substrates 71, respectively 73 and the useful layer opposite. It will be noted that in the figures, a single 8.8 "intermediate layer has been shown for simplification purposes.
- This intermediate layer 8 or 8 can be produced for example by chemical vapor deposition or by any other layer deposition technique known to those skilled in the art.
- the intermediate layers 8, respectively 8 can also be obtained by oxidation of the stiffener substrate 71, respectively 73. This deposition can be carried out either on the stiffener before its application on the useful layer, or on the latter, preferably before the step of implantation of atomic species aimed at forming the embrittlement zone 6.
- the intermediate layer 8 or 8 is then bonded to the facing layer, preferably by bonding by molecular adhesion.
- the intermediate layers 8, 8" are made of a material chosen from silicon oxide ( Si0 2 ), silicon nitride (Si 3 N), insulating materials with high permittivity and diamond.
- FIGS. 5A to 5F illustrate a second mode of construction. embodiment of the method of the invention which differs from that described jointly with FIGS.
- the expression "causing a stiffening substrate to adhere to a useful layer” includes the case where there is intimate contact between the stiffener and the useful layer and the case where at least one layer interlayer 8, 8 'or 8 "is present between them.
- stiffening substrate is understood to mean any type of substrate having a role of mechanical support and making it possible to take off the useful layer from the substrate from which it comes.
- the choice of the nature of the stiffener 71, 72, 73 depends on the final application targeted for the structure obtained.
- the stiffening substrates 71, 72 and 73 can be chosen from the examples given for the support substrate 2.
- the various methods which have just been described and their variants make it possible to obtain at least one pair of structures at the end of each cycle. of the method for a single source substrate 1 to be recycled, so that they are more economical and more profitable than the known methods of the prior art which required the recycling of the source substrate for each structure formed.
- the operator can choose to apply stiffeners of the same type or of different types and with or without an intermediate layer 8, 8 ', 8 ". This results in the possibility of concomitantly obtaining structures comprising stacks of different layers.
- the embrittlement zone 6 it is also possible to form the embrittlement zone 6 so that the rear useful layers 120, 111 or 121 are very thin, for example of a thickness less than 50 nm, while the ui- il-as. before neighbors, respectively referenced 110, 112 or 122, are much thicker.
- the thickness of the useful front layer associated with that of the stiffener which is applied against allows the subsequent annealing heat treatment to be carried out without deformation or appearance of blisters at the rear useful layer. This gives a postponed rear useful layer much thinner than what could be obtained until now.
- implantation processes such as the Smart Cut process.
- the stages of implantation of atomic species carried out on substrates of rank 1 or higher concentrate the defects in the useful layers before 110 or 122, while the rear useful layers 120 or 121 which will not have directly undergone the 'implantation will present an area with defects related to implantation and detachment extending over a thickness less significant at the detachment zone than that of the front layer.
- Example 1 A 5 ′ structure of SOI substrate type comprising a support substrate 2 made of monocrystalline silicon, an intermediate layer 3 made of silicon oxide Si0 2 with a thickness of 20 nm and a useful layer 11 is used as the rank 1 structure. made of 1 in single crystal silicon with a thickness and thickness of 1.5 ⁇ m.
- the embrittlement zone 6 is formed by implantation of hydrogen ions according to an implantation energy of the order of 150 keV and an implantation dose of the order of 6.10 16 H + / cm 2 .
- a rear useful layer 120 with a thickness of 20 nm is thus formed.
- a stiffener 71 is then applied in monocrystalline silicon covered with an intermediate layer 8 of silicon oxide Si0 2 with a thickness of 20 nm and
- the SOI rank 2 substrate referenced 52 ′ After preparation of the surfaces, the useful front layer 112 has a thickness of the order of 0.6 microns and the rear useful layer 111 a thickness of the order of 0.6 microns.
- a stiffener 72 is used in monocrystalline silicon covered with an oxide layer 8 'silicon with a thickness of 20 nm (20 nanometers) and two rank 3 SOI substrates are obtained, referenced
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0306845A FR2855909B1 (fr) | 2003-06-06 | 2003-06-06 | Procede d'obtention concomitante d'au moins une paire de structures comprenant au moins une couche utile reportee sur un substrat |
PCT/FR2004/001368 WO2005004232A1 (fr) | 2003-06-06 | 2004-06-03 | Procede d'obtention concomitante d'une paire de substrats recouverts d'une couche utile |
Publications (1)
Publication Number | Publication Date |
---|---|
EP1631983A1 true EP1631983A1 (de) | 2006-03-08 |
Family
ID=33443190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04767237A Withdrawn EP1631983A1 (de) | 2003-06-06 | 2004-06-03 | Verfahren zur gleichzeitigen herstellung eines mit einer nutzschicht bedeckten substratpaars. |
Country Status (7)
Country | Link |
---|---|
US (2) | US7115481B2 (de) |
EP (1) | EP1631983A1 (de) |
JP (1) | JP4625913B2 (de) |
KR (1) | KR100751150B1 (de) |
CN (1) | CN100358124C (de) |
FR (1) | FR2855909B1 (de) |
WO (1) | WO2005004232A1 (de) |
Families Citing this family (49)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2892228B1 (fr) * | 2005-10-18 | 2008-01-25 | Soitec Silicon On Insulator | Procede de recyclage d'une plaquette donneuse epitaxiee |
US20090325362A1 (en) * | 2003-01-07 | 2009-12-31 | Nabil Chhaimi | Method of recycling an epitaxied donor wafer |
FR2855910B1 (fr) * | 2003-06-06 | 2005-07-15 | Commissariat Energie Atomique | Procede d'obtention d'une couche tres mince par amincissement par auto-portage provoque |
US20060194400A1 (en) * | 2005-01-21 | 2006-08-31 | Cooper James A | Method for fabricating a semiconductor device |
JP2006210660A (ja) * | 2005-01-28 | 2006-08-10 | Hitachi Cable Ltd | 半導体基板の製造方法 |
US7262112B2 (en) * | 2005-06-27 | 2007-08-28 | The Regents Of The University Of California | Method for producing dislocation-free strained crystalline films |
EP1777735A3 (de) * | 2005-10-18 | 2009-08-19 | S.O.I.Tec Silicon on Insulator Technologies | Verfahren zur Wiederverwendung eines temporären epitaxialen Substrates |
FR2896619B1 (fr) * | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite a proprietes electriques ameliorees |
FR2896618B1 (fr) | 2006-01-23 | 2008-05-23 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat composite |
IL174844A (en) | 2006-04-06 | 2011-02-28 | Semi Conductor Devices An Elbit Systems Rafael Partnership | Unipolar semiconductor photodetector with suppressed dark current and method for producing the same |
EP2264755A3 (de) | 2007-01-24 | 2011-11-23 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Herstellungsverfahren für Wafer aus Silizium auf Isolator und entsprechender Wafer |
EP1986229A1 (de) * | 2007-04-27 | 2008-10-29 | S.O.I.T.E.C. Silicon on Insulator Technologies | Herstellungsverfahren für Wafer aus Verbundmaterial und entsprechender Wafer aus Verbundmaterial |
US7795114B2 (en) * | 2007-08-10 | 2010-09-14 | Semiconductor Energy Laboratory Co., Ltd. | Manufacturing methods of SOI substrate and semiconductor device |
US7781308B2 (en) * | 2007-12-03 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing SOI substrate |
US7820527B2 (en) * | 2008-02-20 | 2010-10-26 | Varian Semiconductor Equipment Associates, Inc. | Cleave initiation using varying ion implant dose |
JP2009212387A (ja) * | 2008-03-05 | 2009-09-17 | Semiconductor Energy Lab Co Ltd | 半導体基板の製造方法 |
FR2929758B1 (fr) * | 2008-04-07 | 2011-02-11 | Commissariat Energie Atomique | Procede de transfert a l'aide d'un substrat ferroelectrique |
FR2934924B1 (fr) * | 2008-08-06 | 2011-04-22 | Soitec Silicon On Insulator | Procede de multi implantation dans un substrat. |
EP2157602A1 (de) * | 2008-08-20 | 2010-02-24 | Max-Planck-Gesellschaft zur Förderung der Wissenschaften e.V. | Verfahren zur Herstellung einer Vielzahl von Herstellungs-Wafern |
JP5611571B2 (ja) * | 2008-11-27 | 2014-10-22 | 株式会社半導体エネルギー研究所 | 半導体基板の作製方法及び半導体装置の作製方法 |
JP5404135B2 (ja) * | 2009-03-31 | 2014-01-29 | 株式会社ブリヂストン | 支持基板、貼り合わせ基板、支持基板の製造方法、及び貼り合わせ基板の製造方法 |
FR2944914B1 (fr) * | 2009-04-22 | 2011-05-20 | Commissariat Energie Atomique | Procede de transfert d'au moins une couche micro-technologique |
FR2940852A1 (fr) * | 2009-04-22 | 2010-07-09 | Commissariat Energie Atomique | Procede de transfert d'une couche depuis un substrat de depart vers un substrat final, par double fragilisation |
US8546238B2 (en) | 2009-04-22 | 2013-10-01 | Commissariat A L'energie Atomique Et Aux Energies | Method for transferring at least one micro-technological layer |
US8513090B2 (en) | 2009-07-16 | 2013-08-20 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor substrate, and semiconductor device |
US20110108854A1 (en) * | 2009-11-10 | 2011-05-12 | Chien-Min Sung | Substantially lattice matched semiconductor materials and associated methods |
CN102652354B (zh) * | 2009-12-15 | 2015-02-18 | 索泰克公司 | 用于重复利用衬底的处理 |
CN102194827A (zh) * | 2010-03-16 | 2011-09-21 | 北京大学 | 一种基于高介电常数材料的抗辐照soi器件及制备方法 |
CN102820251A (zh) * | 2011-06-08 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | 一种基于键合工艺的高k介质埋层的soi材料制备方法 |
FR2977069B1 (fr) | 2011-06-23 | 2014-02-07 | Soitec Silicon On Insulator | Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire |
US10103021B2 (en) * | 2012-01-12 | 2018-10-16 | Shin-Etsu Chemical Co., Ltd. | Thermally oxidized heterogeneous composite substrate and method for manufacturing same |
US10543662B2 (en) | 2012-02-08 | 2020-01-28 | Corning Incorporated | Device modified substrate article and methods for making |
FR2992464B1 (fr) * | 2012-06-26 | 2015-04-03 | Soitec Silicon On Insulator | Procede de transfert d'une couche |
US9340443B2 (en) | 2012-12-13 | 2016-05-17 | Corning Incorporated | Bulk annealing of glass sheets |
US10086584B2 (en) | 2012-12-13 | 2018-10-02 | Corning Incorporated | Glass articles and methods for controlled bonding of glass sheets with carriers |
US10014177B2 (en) | 2012-12-13 | 2018-07-03 | Corning Incorporated | Methods for processing electronic devices |
TWI617437B (zh) | 2012-12-13 | 2018-03-11 | 康寧公司 | 促進控制薄片與載體間接合之處理 |
US10510576B2 (en) | 2013-10-14 | 2019-12-17 | Corning Incorporated | Carrier-bonding methods and articles for semiconductor and interposer processing |
CN106132688B (zh) | 2014-01-27 | 2020-07-14 | 康宁股份有限公司 | 用于薄片与载体的受控粘结的制品和方法 |
JP2017518954A (ja) | 2014-04-09 | 2017-07-13 | コーニング インコーポレイテッド | デバイスで改質された基体物品、およびそれを製造する方法 |
FR3029538B1 (fr) * | 2014-12-04 | 2019-04-26 | Soitec | Procede de transfert de couche |
CN107635769B (zh) | 2015-05-19 | 2020-09-15 | 康宁股份有限公司 | 使片材与载体粘结的制品和方法 |
KR102524620B1 (ko) | 2015-06-26 | 2023-04-21 | 코닝 인코포레이티드 | 시트 및 캐리어를 포함하는 방법들 및 물품들 |
FR3051979B1 (fr) * | 2016-05-25 | 2018-05-18 | Soitec | Procede de guerison de defauts dans une couche obtenue par implantation puis detachement d'un substrat |
TW201825623A (zh) | 2016-08-30 | 2018-07-16 | 美商康寧公司 | 用於片材接合的矽氧烷電漿聚合物 |
TWI821867B (zh) | 2016-08-31 | 2023-11-11 | 美商康寧公司 | 具以可控制式黏結的薄片之製品及製作其之方法 |
JP7260523B2 (ja) | 2017-08-18 | 2023-04-18 | コーニング インコーポレイテッド | ポリカチオン性高分子を使用した一時的結合 |
US11331692B2 (en) | 2017-12-15 | 2022-05-17 | Corning Incorporated | Methods for treating a substrate and method for making articles comprising bonded sheets |
CN110078017B (zh) * | 2018-01-26 | 2021-11-05 | 沈阳硅基科技有限公司 | 一种贯穿空腔结构硅片的加工方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6107213A (en) * | 1996-02-01 | 2000-08-22 | Sony Corporation | Method for making thin film semiconductor |
JPH10135500A (ja) * | 1996-03-18 | 1998-05-22 | Sony Corp | 薄膜半導体、太陽電池および発光素子の製造方法 |
SG67458A1 (en) | 1996-12-18 | 1999-09-21 | Canon Kk | Process for producing semiconductor article |
SG63832A1 (en) | 1997-03-26 | 1999-03-30 | Canon Kk | Substrate and production method thereof |
JP3697052B2 (ja) * | 1997-03-26 | 2005-09-21 | キヤノン株式会社 | 基板の製造方法及び半導体膜の製造方法 |
US6150239A (en) * | 1997-05-31 | 2000-11-21 | Max Planck Society | Method for the transfer of thin layers monocrystalline material onto a desirable substrate |
JP3324469B2 (ja) * | 1997-09-26 | 2002-09-17 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
FR2777115B1 (fr) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | Procede de traitement de substrats semi-conducteurs et structures obtenues par ce procede |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3358550B2 (ja) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Soiウエーハの製造方法ならびにこの方法で製造されるsoiウエーハ |
US20020089016A1 (en) * | 1998-07-10 | 2002-07-11 | Jean-Pierre Joly | Thin layer semi-conductor structure comprising a heat distribution layer |
AU2481101A (en) | 1999-07-19 | 2001-02-05 | Maschinenfabrik Bernard Krone Gmbh | Harvesting equipment for stalk plants |
FR2797714B1 (fr) | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | Procede de traitement de substrats pour la microelectronique et substrats obtenus par ce procede |
JP3975634B2 (ja) | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | 半導体ウェハの製作法 |
FR2817394B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
FR2840731B3 (fr) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat comportant une couche utile en materiau semi-conducteur monocristallin de proprietes ameliorees |
FR2817395B1 (fr) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede |
US6420243B1 (en) * | 2000-12-04 | 2002-07-16 | Motorola, Inc. | Method for producing SOI wafers by delamination |
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2003
- 2003-06-06 FR FR0306845A patent/FR2855909B1/fr not_active Expired - Fee Related
- 2003-10-14 US US10/686,084 patent/US7115481B2/en not_active Expired - Fee Related
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2004
- 2004-06-03 JP JP2006508351A patent/JP4625913B2/ja not_active Expired - Fee Related
- 2004-06-03 KR KR1020057022437A patent/KR100751150B1/ko not_active IP Right Cessation
- 2004-06-03 CN CNB2004800118243A patent/CN100358124C/zh not_active Expired - Fee Related
- 2004-06-03 EP EP04767237A patent/EP1631983A1/de not_active Withdrawn
- 2004-06-03 WO PCT/FR2004/001368 patent/WO2005004232A1/fr active Application Filing
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2006
- 2006-08-24 US US11/509,047 patent/US7407867B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
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See references of WO2005004232A1 * |
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JP4625913B2 (ja) | 2011-02-02 |
US20040248378A1 (en) | 2004-12-09 |
KR20060017615A (ko) | 2006-02-24 |
US7407867B2 (en) | 2008-08-05 |
CN1781188A (zh) | 2006-05-31 |
US20060286770A1 (en) | 2006-12-21 |
CN100358124C (zh) | 2007-12-26 |
FR2855909B1 (fr) | 2005-08-26 |
KR100751150B1 (ko) | 2007-08-22 |
JP2006527478A (ja) | 2006-11-30 |
FR2855909A1 (fr) | 2004-12-10 |
WO2005004232A1 (fr) | 2005-01-13 |
US7115481B2 (en) | 2006-10-03 |
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