EP1631983A1 - Method for simultaneously obtaining a pair of substrates covered by a useful layer - Google Patents
Method for simultaneously obtaining a pair of substrates covered by a useful layerInfo
- Publication number
- EP1631983A1 EP1631983A1 EP04767237A EP04767237A EP1631983A1 EP 1631983 A1 EP1631983 A1 EP 1631983A1 EP 04767237 A EP04767237 A EP 04767237A EP 04767237 A EP04767237 A EP 04767237A EP 1631983 A1 EP1631983 A1 EP 1631983A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- substrate
- useful layer
- silicon
- useful
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/977—Thinning or removal of substrate
Definitions
- the present invention relates to a process for the concomitant production of at least two structures, each comprising at least one useful layer transferred onto a substrate for applications in the fields of electronics, optoelectronics or optics.
- Several methods of layer transfer are known from the state of the art. One of them consists in implanting atomic species under the surface of a source substrate, so as to create there a weakening zone which delimits a thin layer. Next, the free face of this thin layer is brought into contact with a support substrate, then detachment of said thin layer from the rest of the source substrate and its transfer to said support substrate.
- Smart Cut For the description of this process, reference may be made to the literature concerning the process known under the trademark "Smart Cut".
- This type of process generates a residue of source substrate which must be recycled so that it can be reused during a new layer transfer. This involves polishing and finishing operations that can be long and costly, both • the price of the equipment used to perform by the time spent achieving them. In addition, for certain extremely hard materials such as silicon carbide, the above-mentioned recycling steps can prove to be very long and tedious.
- the object of the present invention is to solve the aforementioned drawbacks and to provide an economical layer transfer method, limiting the number of source substrates to be recycled.
- the invention relates to a process for the concomitant production of at least one pair of structures, each comprising at least one useful layer transferred onto a substrate, for applications in the fields of electronics, optoelectronics or 1 Optical.
- this method comprises the following stages consisting in: a) preparing a structure known as of row 1, comprising a useful layer transferred onto a support substrate, b) forming a weakening zone inside said useful layer of the rank 1 structure, by implantation of atomic species, so as to define there two layers, called “useful front layer” and “rear useful layer", the rear useful layer being located between, said useful layer, before and said support substrate, c) adhering a stiffening substrate to the free surface of said useful front layer, d) detaching the stack of layers obtained in step c), along said embrittlement zone, by applications constraints, so as to obtain two so-called rank 2 structures, the first comprising at least said support substrate and said rear working layer and the second comprising at least said stiffening substrate and said useful layer the front.
- the cycle of the operations described in steps b) to d) is repeated, using as starting structure at least one of the structures of rank 2 and using stiffening substrates and it is repeated, where appropriate, this cycle of operations at least once, from at least one of the structures of the following row (s).
- the transfer operation from step a) comprises a bonding step, the useful layer coming directly into contact with the support substrate, or one or more intermediate layers being inserted between the useful layer and the support substrate.
- the adhesion operation of step c) is carried out by bonding, the stiffening substrate coming directly into contact with the free surface of the useful front layer, or else at least one intermediate layer being inserted between the substrate.
- the intermediate layer is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity, diamonds and constrained silicon;
- the intermediate layer is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity, diamond;
- At least one of the elements among the support substrate, the stiffening substrate and the useful layer is made of a semiconductor material;
- the support substrate comprises at least one layer of a material chosen from silicon, silicon carbide, sapphire, diamond, germanium, quartz, stabilized zircane yttrium and an alloy of silicon carbide;
- the stiffening substrate comprises at least one layer of a material chosen from silicon,
- the support substrate is made of monocrystalline or polycrystalline silicon, the useful layer of monocrystalline silicon, the stiffening substrate of silicon, mono or polycrystalline ⁇ lin, the intermediate layer and the intermediate layer of silicon oxide; the useful layer of the rank 1 structure is obtained by forming an initial weakening zone inside a source substrate, this initial weakening zone separating said useful layer from the rest of the source substrate, by applying this source substrate on said support substrate then by detachment of said remainder along the initial embrittlement zone; - The initial embrittlement zone is formed by implantation of atomic species or is a porous zone.
- FIGS. 1A to 1C are diagrams illustrating the different stages of a process obtaining a structure comprising a useful layer transferred onto a support substrate
- FIGS. 2A to 2C are diagrams illustrating an alternative embodiment of the method shown in FIGS. 1A to IC according to which a structure is obtained comprising a useful layer transferred onto a substrate using an intermediate layer
- FIGS. 1A to 1C are diagrams illustrating the different stages of a process obtaining a structure comprising a useful layer transferred onto a support substrate
- FIGS. 2A to 2C are diagrams illustrating an alternative embodiment of the method shown in FIGS. 1A to IC according to which a structure is obtained comprising a useful layer transferred onto a substrate using an intermediate layer
- FIGS. 3A to 3F are diagrams illustrating the different stages of a first embodiment of the method for the concomitant production of at least one pair of structures according to the invention
- Figures 4A to 4F are diagrams illustrating an alternative embodiment of the method shown in Figures 3A to 3F
- - And Figures 5A to 5F are diagrams illustrating the different stages of a second embodiment of the method according to the invention.
- the process according to the invention is carried out using a first structure 5 or 5 ′, called a row
- a source substrate 1 internally having a weakening zone 4 delimiting two parts, namely a useful layer 11 and the rest 12 of this source substrate or rear part.
- this weakening zone 4 is called “initial weakening zone”.
- the source substrate 1 has a face 13, called “front face”, intended to come into contact with a support substrate 2 which will be described later.
- the source substrate 1 is chosen from semiconductor materials, in particular those commonly used for applications in the fields of electronics, optoelectronics or optics.
- it may be silicon, silicon carbide, sapphire, diamond, germanium, silicon-germanium, compounds III-V and compounds II-VI.
- Compounds III-V are compounds of which one of the elements belongs to column III of the periodic table and the other to column V, such as for example, gallium nitride (GaN), gallium arsenide (AsGa) or indium phosphide (InP).
- Compounds II-VI are compounds of which one of the elements belongs to column II of the periodic table and the other to column VI, such as for example, cadmium telluride (CdTe).
- the source substrate 1 can also be a composite substrate, that is to say a substrate composed of a solid part, for example made of silicon, on which rests a buffer layer, for example made of silicon-germanium (SiGe).
- the initial embrittlement zone 4 can be obtained by implantation of atomic species.
- implantation of atomic species we mean any bombardment of atomic species, molecular or ionic, capable of introducing these species into a material, with a maximum concentration of these species located at a determined depth relative to the bombarded surface 13.
- the implantation of the atomic species in said source substrate 1 can be carried out by for example, using an ion beam implanter or a plasma immersion implanter.
- this implantation is carried out by ion bombardment.
- the implanted ionic species is hydrogen.
- Other ionic species can advantageously be used alone or in combination with hydrogen, such as rare gases (helium for example).
- the effect of this implantation is to create in the volume of the source substrate 1 and at an average depth of ion penetration, the initial weakening zone 4 which extends substantially parallel to the plane of the front face 13.
- the useful layer 11 s' extends between the front face 13 and this weakening zone 4.
- the initial embrittlement zone 4 can also consist of a porous layer obtained for example as described in document EP-0 849 788.
- the support substrate 2 has a role of mechanical support and therefore generally has a thickness of at least about 300 micrometers. It preferably consists of any mono or polycrystalline semiconductor material commonly used in the aforementioned applications.
- This support substrate 2 can be a solid monolayer substrate chosen for example from silicon, silicon carbide, sapphire, diamond, germanium, quartz, stabilized zircane yttrium (Zr0 2 (Y0 3 )) or an alloy of silicon carbide.
- the support substrate 2 has a face 20, called "front face" because it is intended to receive the front face 13 of the source substrate 1. Then, as shown in FIG.
- the front face 13 of the useful layer 11 is bonded directly to the support substrate 2, that is to say without an intermediate layer.
- this bonding is carried out by molecular adhesion.
- the remainder 12 is detached along the initial embrittlement zone 4 by application of stresses (see FIG. IC).
- One of the following techniques is used for this purpose: application of constraints of mechanical or electrical origin, chemical etching or supply of energy, for example the use of a laser, of microwaves , inductive heating, heat treatment in an oven.
- FIGS. 2A to 2C illustrate an alternative embodiment of the method which has just been described in conjunction with FIGS. 1A to IC but which differs from this in that at least one intermediate layer 3 is inserted between the useful layer 11 and the support substrate 2.
- a single intermediate layer 3 has been shown in FIGS. 2A to 2C and in FIGS. 5A to 5F.
- each of these intermediate layers 3 is made of a material chosen from silicon oxide (Si0 2 ), silicon nitride (Si 3 N 4 ), insulating materials with high permittivity and diamond.
- This intermediate layer 3 can be obtained by chemical vapor deposition techniques or any other technique known to those skilled in the art, carried out either on the front face 20 of the support substrate 2, or on the front face 13 of the source substrate 1 , either on these two front faces and this, before these two substrates are applied one against the other.
- this intermediate layer 3 is an oxide layer, it can also be obtained by thermal oxidation of one or the other of the two substrates 1 or 2.
- a first structure of rank 1, referenced 5 ′ is obtained, comprising the source substrate 2, the useful layer 11 and the intermediate layer 3 inserted between them.
- postponed for a rank 1 structure means that a cc ⁇ iche. useful layer is transferred onto a support substrate by a process comprising at least one bonding step, in the presence or absence of at least one intermediate layer 3.
- the useful layer 11 can be transferred on the support substrate 2 by the BESOI technique mentioned above, in the presence or absence of the intermediate layer 3.
- FIGS. 3A to 3C illustrate a complete cycle of steps of a first embodiment of the method in accordance with invention allowing the concomitant production of a pair of structures each comprising a useful layer transferred onto a substrate.
- a weakening zone 6 is formed inside the useful layer 11 of the structure 5 of rank 1 obtained previously, by implantation of atomic species according to the technique described above for the obtaining the initial embrittlement zone 4.
- the next step illustrated in FIG. 3B consists in making a stiffening substrate 71 adhere to the free surface 130 of said front useful layer 110, by bonding, preferably by direct bonding by molecular adhesion.
- the last step of the cycle illustrated in FIG. 3C consists in detaching the stack of layers obtained in the previous step, along the said .fragi area 1 s-ati on 6, by applying constraints, according to techniques known to a person skilled in the art and described previously together with FIGS. IC and 2C. Two structures 51 and 52 are thus obtained, called row 2 structures.
- the first structure 51 comprises the support substrate 2 and the rear useful layer 120 and the second structure 52 comprises the stiffening substrate 71 and the front useful layer 110.
- the layer useful 11 must have a sufficient thickness so that after the detachment step the two useful layers 110 and 120 obtained do not exhibit any defects or blisters.
- the thicknesses of the two useful layers 110 and 120 can be identical or different depending on the implantation depth of the atomic species and therefore on the location of the embrittlement zone 6.
- the two structures 521 and 522 of rank 3 resulting from the structure 52 of rank 2 respectively comprise the stiffener 71 and the layer u rear tile 111 for the first and the stiffener 72 and the front useful layer 112 for the second, while the two structures 511 and 512 of rank 3 resulting from the structure 51 of rank 2 respectively comprise the stiffener 73 and the useful front layer 122 for the first and the support substrate 2 and the rear useful layer 121 for the second.
- Figures _4A to 4F illustrate an alternative embodiment of the method which differs from that described jointly with Figures 3A to 3F in that at least one intermediate layer 8, respectively 8 ", are inserted between the stiffening substrates 71, respectively 73 and the useful layer opposite. It will be noted that in the figures, a single 8.8 "intermediate layer has been shown for simplification purposes.
- This intermediate layer 8 or 8 can be produced for example by chemical vapor deposition or by any other layer deposition technique known to those skilled in the art.
- the intermediate layers 8, respectively 8 can also be obtained by oxidation of the stiffener substrate 71, respectively 73. This deposition can be carried out either on the stiffener before its application on the useful layer, or on the latter, preferably before the step of implantation of atomic species aimed at forming the embrittlement zone 6.
- the intermediate layer 8 or 8 is then bonded to the facing layer, preferably by bonding by molecular adhesion.
- the intermediate layers 8, 8" are made of a material chosen from silicon oxide ( Si0 2 ), silicon nitride (Si 3 N), insulating materials with high permittivity and diamond.
- FIGS. 5A to 5F illustrate a second mode of construction. embodiment of the method of the invention which differs from that described jointly with FIGS.
- the expression "causing a stiffening substrate to adhere to a useful layer” includes the case where there is intimate contact between the stiffener and the useful layer and the case where at least one layer interlayer 8, 8 'or 8 "is present between them.
- stiffening substrate is understood to mean any type of substrate having a role of mechanical support and making it possible to take off the useful layer from the substrate from which it comes.
- the choice of the nature of the stiffener 71, 72, 73 depends on the final application targeted for the structure obtained.
- the stiffening substrates 71, 72 and 73 can be chosen from the examples given for the support substrate 2.
- the various methods which have just been described and their variants make it possible to obtain at least one pair of structures at the end of each cycle. of the method for a single source substrate 1 to be recycled, so that they are more economical and more profitable than the known methods of the prior art which required the recycling of the source substrate for each structure formed.
- the operator can choose to apply stiffeners of the same type or of different types and with or without an intermediate layer 8, 8 ', 8 ". This results in the possibility of concomitantly obtaining structures comprising stacks of different layers.
- the embrittlement zone 6 it is also possible to form the embrittlement zone 6 so that the rear useful layers 120, 111 or 121 are very thin, for example of a thickness less than 50 nm, while the ui- il-as. before neighbors, respectively referenced 110, 112 or 122, are much thicker.
- the thickness of the useful front layer associated with that of the stiffener which is applied against allows the subsequent annealing heat treatment to be carried out without deformation or appearance of blisters at the rear useful layer. This gives a postponed rear useful layer much thinner than what could be obtained until now.
- implantation processes such as the Smart Cut process.
- the stages of implantation of atomic species carried out on substrates of rank 1 or higher concentrate the defects in the useful layers before 110 or 122, while the rear useful layers 120 or 121 which will not have directly undergone the 'implantation will present an area with defects related to implantation and detachment extending over a thickness less significant at the detachment zone than that of the front layer.
- Example 1 A 5 ′ structure of SOI substrate type comprising a support substrate 2 made of monocrystalline silicon, an intermediate layer 3 made of silicon oxide Si0 2 with a thickness of 20 nm and a useful layer 11 is used as the rank 1 structure. made of 1 in single crystal silicon with a thickness and thickness of 1.5 ⁇ m.
- the embrittlement zone 6 is formed by implantation of hydrogen ions according to an implantation energy of the order of 150 keV and an implantation dose of the order of 6.10 16 H + / cm 2 .
- a rear useful layer 120 with a thickness of 20 nm is thus formed.
- a stiffener 71 is then applied in monocrystalline silicon covered with an intermediate layer 8 of silicon oxide Si0 2 with a thickness of 20 nm and
- the SOI rank 2 substrate referenced 52 ′ After preparation of the surfaces, the useful front layer 112 has a thickness of the order of 0.6 microns and the rear useful layer 111 a thickness of the order of 0.6 microns.
- a stiffener 72 is used in monocrystalline silicon covered with an oxide layer 8 'silicon with a thickness of 20 nm (20 nanometers) and two rank 3 SOI substrates are obtained, referenced
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0306845A FR2855909B1 (en) | 2003-06-06 | 2003-06-06 | PROCESS FOR THE CONCURRENT PRODUCTION OF AT LEAST ONE PAIR OF STRUCTURES COMPRISING AT LEAST ONE USEFUL LAYER REPORTED ON A SUBSTRATE |
PCT/FR2004/001368 WO2005004232A1 (en) | 2003-06-06 | 2004-06-03 | Method for simultaneously obtaining a pair of substrates covered by a useful layer |
Publications (1)
Publication Number | Publication Date |
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EP1631983A1 true EP1631983A1 (en) | 2006-03-08 |
Family
ID=33443190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP04767237A Withdrawn EP1631983A1 (en) | 2003-06-06 | 2004-06-03 | Method for simultaneously obtaining a pair of substrates covered by a useful layer |
Country Status (7)
Country | Link |
---|---|
US (2) | US7115481B2 (en) |
EP (1) | EP1631983A1 (en) |
JP (1) | JP4625913B2 (en) |
KR (1) | KR100751150B1 (en) |
CN (1) | CN100358124C (en) |
FR (1) | FR2855909B1 (en) |
WO (1) | WO2005004232A1 (en) |
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FR2777115B1 (en) * | 1998-04-07 | 2001-07-13 | Commissariat Energie Atomique | PROCESS FOR TREATING SEMICONDUCTOR SUBSTRATES AND STRUCTURES OBTAINED BY THIS PROCESS |
JP3697106B2 (en) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | Method for manufacturing semiconductor substrate and method for manufacturing semiconductor thin film |
JP3358550B2 (en) * | 1998-07-07 | 2002-12-24 | 信越半導体株式会社 | Method for producing SOI wafer and SOI wafer produced by this method |
US20020089016A1 (en) * | 1998-07-10 | 2002-07-11 | Jean-Pierre Joly | Thin layer semi-conductor structure comprising a heat distribution layer |
WO2001005218A1 (en) | 1999-07-19 | 2001-01-25 | Maschinenfabrik Bernard Krone Gmbh | Harvesting equipment for stalk plants |
FR2797714B1 (en) | 1999-08-20 | 2001-10-26 | Soitec Silicon On Insulator | PROCESS FOR PROCESSING SUBSTRATES FOR MICROELECTRONICS AND SUBSTRATES OBTAINED BY THIS PROCESS |
JP3975634B2 (en) * | 2000-01-25 | 2007-09-12 | 信越半導体株式会社 | Manufacturing method of semiconductor wafer |
FR2840731B3 (en) * | 2002-06-11 | 2004-07-30 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SUBSTRATE HAVING A USEFUL LAYER OF SINGLE-CRYSTAL SEMICONDUCTOR MATERIAL OF IMPROVED PROPERTIES |
FR2817395B1 (en) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY |
FR2817394B1 (en) * | 2000-11-27 | 2003-10-31 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A SUBSTRATE, IN PARTICULAR FOR OPTICS, ELECTRONICS OR OPTOELECTRONICS AND SUBSTRATE OBTAINED THEREBY |
US6420243B1 (en) * | 2000-12-04 | 2002-07-16 | Motorola, Inc. | Method for producing SOI wafers by delamination |
-
2003
- 2003-06-06 FR FR0306845A patent/FR2855909B1/en not_active Expired - Fee Related
- 2003-10-14 US US10/686,084 patent/US7115481B2/en not_active Expired - Fee Related
-
2004
- 2004-06-03 JP JP2006508351A patent/JP4625913B2/en not_active Expired - Fee Related
- 2004-06-03 CN CNB2004800118243A patent/CN100358124C/en not_active Expired - Fee Related
- 2004-06-03 EP EP04767237A patent/EP1631983A1/en not_active Withdrawn
- 2004-06-03 KR KR1020057022437A patent/KR100751150B1/en not_active IP Right Cessation
- 2004-06-03 WO PCT/FR2004/001368 patent/WO2005004232A1/en active Application Filing
-
2006
- 2006-08-24 US US11/509,047 patent/US7407867B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
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See references of WO2005004232A1 * |
Also Published As
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CN100358124C (en) | 2007-12-26 |
KR100751150B1 (en) | 2007-08-22 |
JP2006527478A (en) | 2006-11-30 |
US20060286770A1 (en) | 2006-12-21 |
US20040248378A1 (en) | 2004-12-09 |
US7115481B2 (en) | 2006-10-03 |
CN1781188A (en) | 2006-05-31 |
US7407867B2 (en) | 2008-08-05 |
KR20060017615A (en) | 2006-02-24 |
WO2005004232A1 (en) | 2005-01-13 |
JP4625913B2 (en) | 2011-02-02 |
FR2855909B1 (en) | 2005-08-26 |
FR2855909A1 (en) | 2004-12-10 |
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