JP2009212387A - Method of manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor substrate increasing the number of semiconductor substrates to be taken from one bond substrate, and maintaining the quality of a semiconductor layer. <P>SOLUTION: The semiconductor substrate which has a thicker semiconductor layer to be separated from a bond substrate is produced. Then, a plurality of semiconductor substrates is produced using the semiconductor substrate. By making thicker the semiconductor layer to be separated once from the bond substrate, the number of polishing process and heat treatment for the bond substrate can be reduced, so that it is suitable for reuse of the bond substrate. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate.

  In recent years, integrated circuits using an SOI (Silicon On Insulator) substrate instead of a bulk silicon substrate have been developed. By taking advantage of the features of the thin single crystal silicon layer formed on the insulating layer, the transistors in the integrated circuit can be formed completely separated from each other, and the transistors can be made fully depleted, High-value-added semiconductor integrated circuits such as high integration, high speed drive, and low power consumption can be realized.

  As one of methods for manufacturing an SOI substrate, a so-called hydrogen ion implantation separation method using hydrogen ion implantation is known. A typical process of the hydrogen ion implantation separation method is shown below.

  First, hydrogen ions are implanted into a silicon substrate to be a bond substrate, thereby forming an ion implantation region at a predetermined depth from the bond substrate surface. Next, another silicon substrate serving as a base substrate is oxidized to form a silicon oxide film. Thereafter, the bond substrate into which hydrogen ions are implanted and the silicon oxide film of the base substrate are brought into close contact with each other, and the two silicon substrates are bonded to each other. Then, heat treatment is performed to separate the bond substrate with the ion implantation region as a boundary. Thereby, a thin film semiconductor layer separated from the silicon oxide film and the bond substrate is formed on the base substrate.

  Here, although the bond substrate after separation becomes thinner by the thickness of the thin-film semiconductor layer (about 500 nm or less), it can be reused by removing defects or irregularities near the surface. Considering that the thickness of an unused bond substrate is about 0.5 mm or more and 1 mm or less, it can be said that the above process can be repeated 100 times or more using one bond substrate under ideal conditions.

Various techniques have been proposed so far for methods of reusing bond substrates. As an example, a method of removing the residue remaining in the periphery of the bond substrate after separation of the thin film semiconductor layer and then polishing to remove the unevenness in the peripheral portion (for example, Patent Document 1) There is a method (for example, Patent Document 2) in which polishing for removal and heat treatment in a reducing atmosphere containing hydrogen are performed together. In any of the above methods, polishing treatment or heat treatment is performed in order to sufficiently reduce unevenness and defects formed on the surface of the bond substrate.
JP 11-297583 A Japanese Patent Laid-Open No. 11-307413

  Heat treatment and planarization treatment are necessary to reduce defects formed near the bond substrate surface and reduce surface irregularities. However, these treatments cause multiple problems on the bond substrate. sell. For example, a large scratch may be formed on the surface of the bond substrate due to the polishing process during the planarization. Further, the bond substrate may be cracked by repeating the heat treatment. Furthermore, when heat treatment is performed on a bond substrate on which scratches or the like due to polishing treatment or the like are formed, the probability of occurrence of cracks is significantly increased.

  There are also several heat treatment steps in the manufacturing process of the semiconductor substrate. As the number of times of reuse of the bond substrate increases, the number of heat treatments inevitably applied to the bond substrate increases, increasing the possibility of problems such as damage to the bond substrate.

  It is difficult to reuse a bond substrate having problems such as damage as described above. If the above problems occur, even if the bond substrate remains in a sufficient thickness, it must be discarded after all. For this reason, in reality, it is extremely difficult to achieve the ideal number of reuses as described above, and it has been impossible to sufficiently increase the number of pieces taken from one bond substrate.

  Further, when the number of reuses of the bond substrate is increased, there is a problem that the quality of a semiconductor layer manufactured using the bond substrate is deteriorated.

  In view of the above problems, an object of the present invention is to increase the number of semiconductor substrates obtained from one bond substrate. Another object is to provide a semiconductor substrate in which the quality of the semiconductor layer is maintained.

  In the present invention, a semiconductor substrate having a thick semiconductor layer separated from a bond substrate is manufactured, and then a plurality of semiconductor substrates are manufactured using the semiconductor substrate. By increasing the thickness of the semiconductor layer that is separated from the bond substrate at a time, the number of polishing and heating processes of the bond substrate can be reduced, which is suitable for reuse of the bond substrate.

  According to the method for manufacturing a semiconductor substrate of the present invention, a surface of a bond substrate is irradiated with ions to form a first damaged region, a first insulating layer is formed on the surface of the bond substrate, and a first base is formed. The substrate is brought into contact with the surface of the first insulating layer, the first base substrate and the bond substrate are bonded to each other, and the first heat treatment is performed to separate the bond substrate in the first damaged region and Forming a first semiconductor layer over one base substrate, planarizing the surface of the first semiconductor layer, irradiating one surface of the first semiconductor layer with a second damaged region, A second insulating layer is formed on one surface of the first semiconductor layer, the second base substrate and the surface of the second insulating layer are brought into contact with each other, and the second base substrate and the first semiconductor layer are attached. In addition, a second heat treatment is performed to separate the first semiconductor layer in the second damaged region. A second semiconductor layer formed on the first base substrate, and forming a third semiconductor layer on the second base substrate.

  In the above, the bond substrate can be reused by planarizing the surface of the separated bond substrate. Note that planarization of the surface of the first semiconductor layer and planarization of the separated bond substrate surface can be performed using any one or more of an etching process, a laser light irradiation process, and a polishing process.

Further, a protective insulating layer may be formed over one surface of the bond substrate before ion irradiation, or a protective insulating layer may be formed over one surface of the first semiconductor layer before ion irradiation. May be. The ions irradiated to the bond substrate can contain H ⁺ as a main component. Further, the ions irradiated to the first semiconductor layer can contain H ₃ ⁺ as a main component. Here, “including as a main component” means that the number of target ions occupies 50% or more of the total number of ions.

  Note that a plurality of semiconductor substrates can be manufactured using either one or both of the second semiconductor layer and the third semiconductor layer. In this case, the above method (after the planarization of the surface of the first semiconductor layer) may be applied by regarding the second semiconductor layer or the third semiconductor layer as the first semiconductor layer.

  Various semiconductor devices can be manufactured using the semiconductor substrate manufactured by the above method. In addition, various electronic devices can be manufactured using the semiconductor device.

  In the present invention, by increasing the thickness of the semiconductor layer separated from the bond substrate at one time, the number of polishing treatments and heat treatments on the bond substrate can be reduced, and damage and cracking of the bond substrate can be reduced. That is, it is possible to suppress damage to the bond substrate when the bond substrate remains sufficiently thick. Thus, the number of semiconductor substrates that can be manufactured from one bond substrate can be increased. That is, since the bond substrate can be effectively used, the manufacturing cost is reduced.

  In addition, since the number of regeneration processes applied to the bond substrate can be reduced, an increase in defects in the bond substrate can be suppressed to the minimum, and a semiconductor substrate with the quality of the semiconductor layer maintained can be provided. .

  Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the present invention described below, the same reference numerals are used in different drawings. In this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

(Embodiment 1)
In this embodiment mode, a method for manufacturing a semiconductor substrate of the present invention will be described with reference to FIGS.

  First, the first base substrate 100 is prepared (see FIG. 1A). As the first base substrate 100, for example, a glass substrate having visible light transparency used for a liquid crystal display device or the like can be used. A glass substrate having a strain point of 580 ° C. or higher and 680 ° C. or lower (preferably 600 ° C. or higher and 680 ° C. or lower) may be used. The glass substrate is preferably an alkali-free glass substrate. For the alkali-free glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used, for example.

  Note that the first base substrate 100 includes a glass substrate, an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon, or a conductive material such as metal or stainless steel. A conductive substrate made of a body can also be used.

  Although not shown in this embodiment mode, an insulating layer may be formed on the surface of the first base substrate 100. When the insulating layer is provided, the first base substrate 100 contains an element that contaminates the semiconductor (for example, an alkali metal or an alkaline earth metal; hereinafter simply referred to as an “impurity”). Even so, the impurities can be prevented from diffusing into the semiconductor layer. The insulating layer may have a single layer structure or a laminated structure. Examples of the material forming the insulating layer include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, and aluminum nitride oxide.

  Note that in this specification, an oxynitride is a substance having a higher oxygen content than nitrogen as a composition, and a nitride oxide is a composition having a nitrogen content higher than oxygen as a composition. Many substances. For example, silicon oxynitride refers to oxygen of 50 atomic% to 70 atomic%, nitrogen of 0.5 atomic% to 15 atomic%, silicon of 25 atomic% to 35 atomic%, and hydrogen of 0.1 atomic% The substance can be contained in the range of 10 atomic% or less. In addition, silicon nitride oxide means oxygen of 5 atomic% to 30 atomic%, nitrogen of 20 atomic% to 55 atomic%, silicon of 25 atomic% to 35 atomic%, and hydrogen of 10 atomic% to 25 atomic%. The substance can be included in the following ranges. However, the range of the said composition is a thing when it measures using Rutherford backscattering method (RBS: Rutherford Backscattering Spectrometry) and the hydrogen forward scattering method (HFS: Hydrogen Forward Scattering). Further, the content ratio of the constituent elements takes a value that the total does not exceed 100 atomic%.

  Next, a bond substrate 110 is prepared (see FIG. 1B). As the bond substrate 110, for example, a semiconductor substrate made of a Group 4 element such as silicon, germanium, silicon germanium, or silicon carbide can be used. Of course, a substrate made of a compound semiconductor such as gallium arsenide or indium phosphide may be used. In this embodiment, a single crystal silicon substrate is used as the bond substrate 110. Although there is no restriction | limiting in the size and shape of the bond board | substrate 110, For example, it is good to process circular semiconductor substrates, such as 8 inches (200 mm), 12 inches (300 mm), and 18 inches (450 mm), into a rectangle. Note that in this specification, a single crystal means that the crystal structure is formed with a certain regularity and the crystal axes are in the same direction in any part. That is, it does not matter about the number of defects.

  After the bond substrate 110 is cleaned, an insulating layer 112 is formed on the surface of the bond substrate 110. The insulating layer 112 may be omitted. However, in order to prevent contamination of the bond substrate 110, damage to the surface of the bond substrate 110, etching of the surface of the bond substrate 110, and the like during subsequent ion irradiation, the insulating layer 112 may be formed. It is preferable to provide it. The thickness of the insulating layer 112 is preferably about 1 nm to 400 nm.

  As a material for forming the insulating layer 112, an insulating material containing silicon or germanium in its composition, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, germanium oxide, germanium nitride, germanium oxynitride, germanium nitride oxide, or the like is used. Can be mentioned. Also, metal oxides such as aluminum oxide, tantalum oxide, and hafnium oxide, metal nitrides such as aluminum nitride, metal oxynitrides such as aluminum oxynitride, and metal nitride oxides such as aluminum nitride oxide are used. Also good. As a method for forming the insulating layer 112, a CVD method, a sputtering method, a method using oxidation (or nitridation) of the bond substrate 110, and the like can be given.

  Next, the insulating layer 112 is irradiated with an ion beam 150 including ions accelerated by an electric field, so that a damaged region 114 is formed in a region having a predetermined depth from the surface of the bond substrate 110 (see FIG. 1C). ). The depth of the region where the damaged region 114 is formed can be controlled by the energy applied to the ions and the incident angle of the ion beam 150. Here, the damaged region 114 is formed in a region having a depth similar to the average penetration depth of ions.

  The thickness of the semiconductor layer separated from the bond substrate 110 is determined by the depth at which the damaged region 114 is formed. In the present invention, in order to reduce the number of times the semiconductor layer is separated from the bond substrate 110, the semiconductor layer needs to be formed thick. Specifically, the damaged region 114 is formed so that a plurality of semiconductor layers can be further separated from the separated semiconductor layers. That is, the thickness of the semiconductor layer separated in the damaged region 114 is sufficiently larger than the finally required thickness of the semiconductor layer. More specifically, the depth of the damaged region 114 is 400 nm or more from the surface of the bond substrate 110, preferably 0.5 μm or more and 50 μm or less, more preferably 1 μm or more and 10 μm or less. Note that the depth of the damaged region 114 can be set as appropriate in consideration of the number of times the bond substrate 110 can be regenerated and the reduction in thickness in the planarization treatment of the bond substrate 110 and the semiconductor layer after separation. . In this embodiment mode, ions are irradiated so that the depth of the damaged region 114 is about 1.2 μm.

  Note that increasing the thickness of the semiconductor layer to be separated has an effect of suppressing generation of voids (also referred to as voids) due to poor bonding.

  When irradiating the bond substrate 110 with ions, for example, an ion implantation apparatus or an ion doping apparatus can be used. In the ion implantation apparatus, a source gas is excited to generate ions, the generated ions are mass-separated, and ions to be processed are irradiated with ions having a predetermined mass. The ion doping apparatus generates ions by exciting a process gas, and irradiates the object to be processed without mass separation of the generated ions. Note that an ion doping apparatus including a mass separation apparatus can perform ion irradiation with mass separation in the same manner as the ion implantation apparatus.

  Note that it is preferable to use an ion doping apparatus from the viewpoint of productivity. This is because the ion doping apparatus does not involve mass separation, so that it is possible to irradiate all of the generated ions, and by not involving mass separation, it becomes possible to irradiate ions in a planar shape. Because.

A gas containing hydrogen can be used as a source gas in the ion irradiation step. By using the gas, ions such as H ⁺ , H ₂ ⁺ , H ₃ ⁺ can be generated. Here, since the damaged region 114 must be formed at a certain depth from the surface of the bond substrate, it is required that the ions reach deep into the bond substrate. Since H ₂ ⁺ and H ₃ ⁺ have a feature of being separated into H and H ⁺ by collision with the bond substrate surface, when the gas is used as a source gas, the ratio of H ⁺ is increased. Can be said to be preferable. In H ₂ ⁺ and H ₃ ^+, will be the kinetic energy when separating the H and H ⁺ is distributed to each particle (H or H ^+), since the tendency of damaged region 114 is formed shallower It is. Of course, if the ions can be implanted deeply, it is not necessary to specifically limit the interpretation to increase the H ⁺ ratio.

As a source gas in the ion irradiation process, in addition to a gas containing hydrogen, a rare gas such as helium or argon, a halogen gas typified by fluorine gas or chlorine gas, or a halogen compound gas such as fluorine compound gas (for example, BF ₃ ) One or more kinds of gases selected from the above can be used. When helium is used as the source gas, the ion beam 150 having a high He ⁺ ratio can be created. By using such an ion beam 150, the damaged region 114 can be efficiently formed.

  Further, the damaged region 114 can be formed by performing the ion irradiation process a plurality of times. In this case, the source gas may be different for each ion irradiation step, or the same source gas may be used. For example, after ion irradiation is performed using a rare gas as a source gas, ions can be irradiated using a gas containing hydrogen as a source gas. Alternatively, ion irradiation can be performed first using a halogen gas or a halogen compound gas, and then ion irradiation can be performed using a gas containing hydrogen gas.

  After the damaged region 114 is formed, the insulating layer 112 is removed and a new insulating layer 116 is formed (see FIG. 1D). Here, the insulating layer 112 is removed because the insulating layer 112 is highly likely to be damaged during the ion irradiation. Note that it is not necessary to remove the insulating layer 112 when damage to the insulating layer 112 does not cause a problem. In this case, a new insulating layer 116 may be formed over the insulating layer 112, or the insulating layer 116 may not be formed.

  As a material for forming the insulating layer 116, an insulating material containing silicon or germanium in its composition, such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, germanium oxide, germanium nitride, germanium oxynitride, germanium nitride oxide, or the like is used. Can be mentioned. Also, metal oxides such as aluminum oxide, tantalum oxide, and hafnium oxide, metal nitrides such as aluminum nitride, metal oxynitrides such as aluminum oxynitride, and metal nitride oxides such as aluminum nitride oxide are used. Also good. As a method for forming the insulating layer 116, there are a CVD method, a sputtering method, a method by oxidation (or nitridation) of the bond substrate 110, and the like. Note that although the insulating layer 116 has a single-layer structure in this embodiment, the present invention is not construed as being limited thereto. A laminated structure of two or more layers can also be used.

  Since the insulating layer 116 is a layer related to bonding, the surface thereof preferably has high flatness. For example, a layer having a surface arithmetic average roughness of 0.6 nm or less (preferably 0.3 nm or less) and a root mean square roughness of 0.7 nm or less (preferably 0.4 nm or less) is formed. As such an insulating layer 116, for example, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas can be used.

  Hereinafter, for convenience of description, the structure illustrated in FIG.

  After that, the first base substrate 100 and the substrate 140 are attached to each other (see FIG. 1E). Specifically, for example, the surfaces of the first base substrate 100 and the substrate 140 are cleaned by a method such as ultrasonic cleaning (including so-called megasonic cleaning having a frequency of 50 kHz to 5 MHz), and a hydrophilic group is added. After processing using a chemical solution (such as ozone water, a mixed solution of ammonia water and hydrogen peroxide water (and water), or other oxidizing agent), the surface of the first base substrate 100 and the substrate 140 Pressure is applied by bringing the surface (more specifically, the surface of the insulating layer 116) into close contact. In addition, as a process performed to the surface of the 1st base substrate 100 and the board | substrate 140, oxygen plasma processing etc. can be mentioned other than a chemical | medical solution process, for example.

  In addition, since it is thought that Van der Waals force, hydrogen bond, etc. are concerned in bonding, it is preferable to use the method of utilizing these bonding mechanisms to the maximum. For example, as described above, before bonding, the surfaces of the first base substrate 100 and the substrate 140 are subjected to a treatment using a chemical solution that adds a hydrophilic group, an oxygen plasma treatment, or the like. There is a method to make it hydrophilic. By this treatment, hydrophilic groups are added to the surfaces of the first base substrate 100 and the substrate 140, so that a large number of hydrogen bonds can be formed at the bonding interface. That is, the bonding strength can be improved.

  Note that the atmosphere at the time of bonding can be an air atmosphere, an inert atmosphere such as a nitrogen atmosphere, an atmosphere containing oxygen or ozone, or a reduced pressure atmosphere. By bonding in an inert atmosphere or in an atmosphere containing oxygen or ozone, it is possible to bond effectively using hydrophilic groups added to the surfaces of the first base substrate 100 and the substrate 140. On the other hand, it is also possible to perform bonding in a reduced pressure atmosphere. In this case, since the influence of contaminants in the atmosphere can be reduced, the interface for bonding can be kept clean. In addition, air confinement at the time of bonding can be reduced.

  Next, heat treatment is performed on the first base substrate 100 and the substrate 140 that are bonded together, thereby strengthening the bonding. The heat treatment is performed as much as possible immediately after bonding (before substrate conveyance). This is because in the case where the substrate is transported after bonding and before the heat treatment, the substrate 140 is likely to be peeled off due to bending of the first base substrate 100 or the like.

  The heating temperature needs to be equal to or lower than the heat resistant temperature of the first base substrate and does not cause separation in the damaged region. For example, the temperature can be 150 ° C. or higher and 450 ° C. or lower, preferably 200 ° C. or higher and 400 ° C. or lower. The treatment time is preferably 1 minute or more and 10 hours or less (more preferably 3 minutes or more and 3 hours or less), but optimum conditions can be appropriately set from the relationship between the treatment speed and the bonding strength. In this embodiment mode, heat treatment is performed at 200 ° C. for 2 hours. Note that it is also possible to heat locally by irradiating the microwave only to the region related to the bonding of the substrates.

  Next, the substrate 140 is separated into the insulating layer 116, the semiconductor layer 118, and the substrate 120 (see FIG. 1F). The substrate 140 is separated by heat treatment. The heat treatment temperature can be based on the heat-resistant temperature of the first base substrate 100. For example, when a glass substrate is used as the first base substrate 100, the heating temperature is preferably 400 ° C. or higher and 650 ° C. or lower. Note that heat treatment may be performed at 400 ° C to 700 ° C for a short time. Note that in this embodiment, heat treatment is performed at 600 ° C. for 2 hours.

  By performing the heat treatment as described above, a volume change of minute holes formed in the damaged region 114 occurs, and a crack occurs in the damaged region 114. As a result, the substrate 140 is separated along the damaged region 114. Since the insulating layer 116 is bonded to the first base substrate 100, the separated semiconductor layer 118 remains on the first base substrate 100. In this embodiment mode, since the damaged region 114 is formed to a depth of about 1.2 μm, the thickness of the semiconductor layer 118 is about 1.2 μm or less at this stage. Further, since the bonding interface between the first base substrate 100 and the insulating layer 116 is heated by this heat treatment, a covalent bond is formed at the bonding interface, and the bonding force between the first base substrate 100 and the insulating layer 116 is further increased. improves.

  The surface of the semiconductor layer 118 formed as described above has defects due to the ion irradiation process and the separation process, and the flatness thereof is impaired. As described above, in a state where there are many defects in the semiconductor layer 118, the characteristics are deteriorated, and it is difficult to perform pasting which is characteristic of the present invention. Therefore, defect reduction processing and planarization processing of the semiconductor layer 118 are performed.

  In this embodiment, defect reduction and planarity improvement of the semiconductor layer 118 are realized by using any one or more of etching treatment, laser light irradiation treatment, heat treatment, and polishing treatment. For example, a configuration in which polishing treatment is performed after heat treatment and laser light irradiation treatment may be employed.

  The etching process may be a dry etching process or a wet etching process. The flatness of the semiconductor layer 118 can be improved by the etching treatment.

For the laser light irradiation treatment, for example, a continuous wave laser (CW laser), a pseudo CW laser (a pulsed laser having an oscillation frequency of 10 MHz or more, preferably 80 MHz or more), or the like can be used. Specifically, as a continuous wave laser, Ar laser, Kr laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser Ti: sapphire laser, helium cadmium laser, or the like can be used. As pseudo CW lasers, Ar laser, Kr laser, excimer laser, CO ₂ laser, YAG laser, YVO ₄ laser, YLF laser, YAlO ₃ laser, GdVO ₄ laser, Y ₂ O ₃ laser, ruby laser, alexandrite laser , A pulsed laser such as a Ti: sapphire laser, a copper vapor laser, or a gold vapor laser can be used. Such a pulsed laser can be handled in the same manner as a continuous wave laser when the oscillation frequency is increased. By the laser light irradiation treatment, defects in the semiconductor layer 118 can be reduced and planarity can be improved.

  The heat treatment is not particularly limited as long as the heat treatment is performed within the heat resistant temperature of the first base substrate 100. For example, when a glass substrate is used as in the present embodiment, it is preferably performed at a temperature condition of 650 ° C. or lower. By the heat treatment, defects in the semiconductor layer 118 can be reduced. Note that in the case where a substrate with high heat resistance (eg, a single crystal silicon substrate) is used as the first base substrate 100, the planarity of the semiconductor layer 118 is increased by high-temperature heat treatment (eg, about 800 ° C. to 1200 ° C.). Can be improved.

  In the above polishing treatment, for example, the arithmetic average roughness of the surface of the semiconductor layer 118 is 1 nm or less (preferably 0.5 nm or less) and the root mean square roughness is 1.5 nm or less (preferably 1 nm or less). Good to do. Note that when only the polishing process is used, the polishing amount (thickness) tends to be as large as several μm, and therefore, it is preferable to use in combination with any of the above processes. As a result, the polishing amount can be reduced to about 0.5 μm.

  In this embodiment mode, a laser light irradiation process is performed after the etching process, and then a polishing process is performed. Thus, a semiconductor layer 122 with reduced defects and improved surface flatness is formed over the first base substrate 100 (see FIG. 1G). Note that in this embodiment mode, the thickness of the semiconductor layer 122 is about 0.5 μm.

  For the separated substrate 120, the same process as the process for the semiconductor layer 118 is performed. Thus, a regenerated bond substrate 160 with reduced defects and improved flatness is formed (see FIG. 1H). The recycled bond substrate 160 can be repeatedly used as the bond substrate 110 in the above process.

  Next, a process for forming a plurality of semiconductor substrates using the semiconductor layer 122 will be described. First, after the surface of the semiconductor layer 122 and the like are washed, an insulating layer 124 is formed on the surface of the semiconductor layer 122 (see FIG. 2A). The insulating layer 124 may be omitted. However, in order to prevent contamination of the semiconductor layer 122, damage to the surface of the semiconductor layer 122, etching of the surface of the semiconductor layer 122, and the like during subsequent ion irradiation, the insulating layer 124 may be formed. It is preferable to provide it. Note that the insulating layer 124 can be formed in a manner similar to that of the insulating layer 112;

  Next, the insulating layer 124 is irradiated with an ion beam 152 including ions accelerated by an electric field, so that a damaged region 126 is formed in a region having a predetermined depth from the surface of the semiconductor layer 122 (see FIG. 2B). ). Details of the irradiation with the ion beam 152 are the same as in the case of irradiation with the ion beam 150, and are omitted here. Here, the ions are irradiated so that the depth of the damaged region 126 is about 250 nm.

When a gas containing hydrogen is used as a source gas in the ion irradiation process, ions such as H ⁺ , H ₂ ⁺ , and H ₃ ⁺ are generated. Here, considering the characteristics of a semiconductor element formed later, it can be said that the semiconductor layer formed separately from the semiconductor layer 122 is preferably thin. That is, the damaged region 126 is preferably formed at a shallow position from the surface of the semiconductor layer 122. In this case, it is preferable to increase the ratio of H ₂ ⁺ or H ₃ ⁺ (particularly H ₃ ⁺ ). Of course, as long as ions can be implanted shallowly, it is not necessary to specifically limit the interpretation to increase the ratio of H ₂ ⁺ or H ₃ ⁺ .

  After the damaged region 126 is formed, the insulating layer 124 is removed and a new insulating layer 128 is formed (see FIG. 2C). Here, the insulating layer 124 is removed because the insulating layer 124 is highly likely to be damaged during the ion irradiation. Note that it is not necessary to remove the insulating layer 124 when damage to the insulating layer 124 does not cause a problem. In this case, a new insulating layer 128 may be formed over the insulating layer 124, or the insulating layer 128 may not be formed.

  The structure, material, formation method, and the like of the insulating layer 128 are the same as those of the insulating layer 116, and thus are omitted here. Since the insulating layer 128 is also a layer for bonding, the surface thereof preferably has high flatness. As the insulating layer 128 having such high flatness, for example, a silicon oxide film formed by a chemical vapor deposition method using an organosilane gas can be used.

  Hereinafter, for convenience of description, the structure illustrated in FIG.

  Next, a second base substrate 102 is prepared (see FIG. 2D). Since the same thing as the 1st base substrate 100 can be used as the 2nd base substrate 102, it abbreviate | omits for details. Needless to say, the second substrate 102 is not necessarily limited to the same substrate as the first base substrate 100.

  After that, the second base substrate 102 and the substrate 142 are attached to each other (see FIG. 2E). The details of the bonding are the same as the bonding of the first base substrate 100 and the substrate 140, and thus are omitted here.

  Next, heat treatment is performed on the second base substrate 102 and the substrate 142 which are bonded together, so that the bonding is strengthened. The heat treatment is performed as much as possible immediately after bonding (before substrate conveyance). This is because in the case where the substrate is transported after bonding and before heat treatment, there is a high possibility that the substrate 142 is peeled off due to the bending of the second base substrate 102 or the like. The conditions for the heat treatment are also the same as those for the first base substrate 100 and the substrate 140, and thus description thereof is omitted.

  Next, the semiconductor layer 122 is separated (not shown). The semiconductor layer 122 is separated by heat treatment. The conditions for the heat treatment are the same as the conditions for separating the substrate 140, and thus the description is omitted.

  By performing the heat treatment as described above, a volume change of minute holes formed in the damaged region 126 occurs, and a crack occurs in the damaged region 126. As a result, the semiconductor layer 122 is separated along the damaged region 126. Accordingly, a part of the separated semiconductor layer 122 is disposed on the first base substrate 100, and another part of the separated semiconductor layer 122 is disposed on the second base substrate 102. become. Note that since the damaged region 126 is formed at a depth of about 250 nm here, the thickness of the separated semiconductor layer is about 250 nm or less at this stage. Further, the bonding strength between the second base substrate 102 and the insulating layer 128 is further improved by the heat treatment at the time of separation.

  The surface of the semiconductor layer separated as described above has defects due to the ion irradiation process and the separation process, and the flatness thereof is impaired. For this reason, defect reduction processing and planarization processing of the semiconductor layer are performed. The defect reduction process and the planarization process can be performed in the same manner as the defect reduction process and the planarity improvement process of the semiconductor layer 118. In order to effectively reduce the defects and improve the flatness of the surface, the laser beam irradiation treatment is particularly suitable.

  Thus, the semiconductor substrate 170 in which the semiconductor layer 130 is formed over the first base substrate 100 and the semiconductor substrate 172 in which the semiconductor layer 132 is formed over the second base substrate 102 are completed (FIG. 2F). (See FIG. 2G). Note that the thickness of the semiconductor layer 130 and the semiconductor layer 132 finally formed in this embodiment is about 100 nm or less.

  As described above, in this embodiment, the semiconductor layer separated from the bond substrate is thickened, and two semiconductor substrates are manufactured from the separated semiconductor layer. Thereby, the burden concerning the reproduction | regeneration processing of a bond board | substrate can be halved. That is, since the number of heat treatments and polishing processes necessary for regenerating the bond substrate can be substantially reduced, the possibility of problems such as scratches and cracks can be reduced. That is, since a large number of semiconductor substrates can be manufactured from one bond substrate, the manufacturing cost of the semiconductor substrate can be significantly reduced.

  Further, when the number of times of regenerating the bond substrate is increased, the quality of the semiconductor layer separated from the bond substrate is deteriorated. This problem is caused by an increase in defects due to heat treatment or polishing treatment. In the present invention, since the number of times of regeneration processing applied to the bond substrate can be reduced, an increase in defects in the bond substrate can be suppressed to the minimum, and a semiconductor substrate with the quality of the semiconductor layer maintained can be provided. .

  Note that although the case where two semiconductor substrates are manufactured using one semiconductor layer has been described in this embodiment mode, the present invention is not limited to this. Three or more semiconductor substrates may be manufactured using one semiconductor layer. In this case, it is necessary to form a thicker semiconductor layer separated from the bond substrate, but it is possible to further reduce the burden associated with the bond substrate regeneration process. That is, the manufacturing cost of the semiconductor substrate can be further reduced. In addition, by forming the semiconductor layer thick, defects in bonding of the semiconductor layers can be reduced and generation of defects and vacancies in the semiconductor layer can be suppressed, so that the quality of the semiconductor layer can be maintained.

(Embodiment 2)
In this embodiment, a method for manufacturing a semiconductor device using the above-described semiconductor substrate will be described with reference to FIGS. Here, a method for manufacturing a semiconductor device including a plurality of transistors (thin film transistors) is described as an example of the semiconductor device. Note that various semiconductor devices can be formed by using a combination of the transistors described below.

  FIG. 3A is a cross-sectional view of the semiconductor substrate manufactured according to Embodiment 1. Note that this embodiment mode shows a case where the insulating layer 116 or the insulating layer 128 in Embodiment Mode 1 has a two-layer structure.

The semiconductor layer 300 (corresponding to the semiconductor layer 130 and the semiconductor layer 132 in Embodiment Mode 1) is a p-type such as boron, aluminum, or gallium in order to control the threshold voltage of a thin film transistor (hereinafter referred to as TFT). An impurity or an n-type impurity such as phosphorus or arsenic may be added. The region to which the impurity is added and the kind of the impurity to be added can be changed as appropriate. For example, a p-type impurity can be added to the formation region of the n-channel TFT, and an n-type impurity can be added to the formation region of the p-channel TFT. When the above-described impurities are added, the dose may be set to about 1 × 10 ¹⁵ / cm ² or more and about 1 × 10 ¹⁷ / cm ² or less. After that, the semiconductor layer 300 is separated into island shapes, so that a semiconductor layer 302 and a semiconductor layer 304 are formed (see FIG. 3B).

  Next, a gate insulating layer 306 is formed so as to cover the semiconductor layer 302 and the semiconductor layer 304 (see FIG. 3C). Here, a silicon oxide film is formed as a single layer by a plasma CVD method. In addition, the gate insulating layer 306 may be formed by forming a film containing silicon oxynitride, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, or the like with a single-layer structure or a stacked structure.

  As a manufacturing method other than the plasma CVD method, a sputtering method or a method using oxidation or nitridation by high-density plasma treatment can be given. The high-density plasma treatment is performed using a mixed gas of a rare gas such as helium, argon, krypton, or xenon and a gas such as oxygen, nitrogen oxide, ammonia, nitrogen, or hydrogen. In this case, high-density plasma can be generated at a low electron temperature by exciting the plasma by introducing a microwave. By oxidizing or nitriding the surface of the semiconductor layer with oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by such high-density plasma, 1 nm or more An insulating layer of 20 nm or less, preferably 2 nm or more and 10 nm or less is formed so as to be in contact with the semiconductor layer.

  Since the oxidation or nitridation of the semiconductor layer by the high-density plasma treatment described above is a solid-phase reaction, the interface state density between the gate insulating layer 306 and the semiconductor layer 302 and between the gate insulating layer 306 and the semiconductor layer 304 can be extremely low. . Further, by directly oxidizing or nitriding the semiconductor layer by high-density plasma treatment, variation in the thickness of the formed insulating layer can be suppressed. In addition, since the semiconductor layer has crystallinity, even when the surface of the semiconductor layer is oxidized by solid-phase reaction using high-density plasma treatment, non-uniform oxidation at the crystal grain boundary is suppressed and the uniformity is good. A gate insulating layer having a low interface state density can be formed. In this manner, by using the insulating layer formed by high-density plasma treatment for part or all of the gate insulating layer of the transistor, variation in characteristics can be suppressed.

A more specific example of a method for manufacturing an insulating layer by plasma treatment will be described. Nitrous oxide (N ₂ O) is diluted 1 to 3 times (flow rate ratio) with argon (Ar) and microwaves (2.45 GHz) of 3 kW to 5 kW under a pressure of 10 Pa to 30 Pa. ) Electric power is applied to oxidize or nitride the surfaces of the semiconductor layer 302 and the semiconductor layer 304. By this treatment, a lower layer of the gate insulating layer 306 having a thickness of 1 nm to 10 nm (preferably 2 nm to 6 nm) is formed. Furthermore, nitrous oxide (N ₂ O) and silane (SiH ₄ ) were introduced, and microwave power (2.45 GHz) of 3 kW to 5 kW was applied under a pressure of 10 Pa to 30 Pa, and vapor phase growth was performed. A silicon oxynitride film is formed as an upper layer of the gate insulating layer 306. In this manner, by forming the gate insulating layer 306 by combining the solid phase reaction and the vapor deposition method, the gate insulating layer 306 having a low interface state density and an excellent withstand voltage can be formed. Note that in this case, the gate insulating layer 306 has a two-layer structure.

  Alternatively, the gate insulating layer 306 may be formed by thermally oxidizing the semiconductor layer 302 and the semiconductor layer 304. When such thermal oxidation is used, it is preferable to use a base substrate having relatively high heat resistance.

  Note that the gate insulating layer 306 containing hydrogen is formed, and then heat treatment is performed at a temperature of 350 ° C. to 450 ° C., whereby hydrogen contained in the gate insulating layer 306 is introduced into the semiconductor layer 302 and the semiconductor layer 304. You may make it diffuse. In this case, as the gate insulating layer 306, silicon nitride or silicon nitride oxide using a plasma CVD method can be used. The process temperature is preferably 350 ° C. or lower. In this manner, by supplying hydrogen to the semiconductor layer 302 and the semiconductor layer 304, the interface between the gate insulating layer 306 and the semiconductor layer 302 and the gate insulating layer 306 and the semiconductor layer 304 in the semiconductor layer 302, the semiconductor layer 304, and Defects at the interface can be effectively reduced.

  Next, after a conductive layer is formed over the gate insulating layer 306, the conductive layer is processed (patterned) into a predetermined shape, so that the electrode 308 is formed over the semiconductor layer 302 and the semiconductor layer 304 (FIG. 3). (See (D)). A CVD method, a sputtering method, or the like can be used for forming the conductive layer. The conductive layer is formed using a material such as tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), or niobium (Nb). can do. Alternatively, an alloy material containing the above metal as a main component or a compound containing the above metal may be used. Alternatively, a semiconductor material such as polycrystalline silicon doped with an impurity element imparting conductivity to a semiconductor may be used.

  In this embodiment mode, the electrode 308 is formed using a single conductive layer; however, the semiconductor device of the present invention is not limited to this structure. The electrode 308 may be formed of a plurality of stacked conductive layers. In the case of a two-layer structure, for example, a molybdenum film, a titanium film, a titanium nitride film, or the like may be used as a lower layer, and an aluminum film or the like may be used as an upper layer. In the case of a three-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film, a stacked structure of a titanium film, an aluminum film, and a titanium film, or the like may be employed.

  Note that a mask used for forming the electrode 308 may be formed using a material such as silicon oxide or silicon nitride oxide. In this case, a step of forming a mask by patterning a silicon oxide film, a silicon nitride oxide film, or the like is added. However, since the mask film is less reduced at the time of etching than a resist material, the electrode 308 having a more accurate shape is used. Can be formed. Alternatively, the electrode 308 may be selectively formed by a droplet discharge method without using a mask. Here, the droplet discharge method means a method of forming a predetermined pattern by discharging or ejecting a droplet containing a predetermined composition, and includes an ink jet method or the like in its category.

  Further, using an ICP (Inductively Coupled Plasma) etching method, etching conditions (amount of power applied to the coil-type electrode layer, a power amount applied to the electrode layer on the substrate side, and an electrode temperature on the substrate side) Etc.) is adjusted as appropriate, and the conductive layer is etched so as to have a desired tapered shape, whereby the electrode 308 can also be formed. The taper shape can also be controlled by the shape of the mask. As an etching gas, a chlorine-based gas such as chlorine, boron chloride, silicon chloride, or carbon tetrachloride, a fluorine-based gas such as carbon tetrafluoride, sulfur fluoride, or nitrogen fluoride, or oxygen may be used as appropriate. it can.

  Next, an impurity element imparting one conductivity type is added to the semiconductor layer 302 and the semiconductor layer 304 using the electrode 308 as a mask (see FIG. 4A). In this embodiment, an impurity element imparting n-type conductivity (eg, phosphorus or arsenic) is added to the semiconductor layer 302, and an impurity element imparting p-type conductivity (eg, boron) is added to the semiconductor layer 304. Note that when the n-type impurity element is added to the semiconductor layer 302, the semiconductor layer 304 to which the p-type impurity is added is covered with a mask or the like, and the addition of the n-type impurity element is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 304, the semiconductor layer 302 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done. Alternatively, after adding one of an impurity element imparting p-type conductivity or an impurity element imparting n-type to the semiconductor layer 302 and the semiconductor layer 304, an impurity imparting p-type at a higher concentration only to one semiconductor layer The other of the element or the impurity element imparting n-type conductivity may be added. By the addition of the impurities, an impurity region 310 is formed in the semiconductor layer 302 and an impurity region 312 is formed in the semiconductor layer 304.

Next, sidewalls 314 are formed on side surfaces of the electrode 308 (see FIG. 4B). The sidewalls 314 are formed by, for example, forming a new insulating layer so as to cover the gate insulating layer 306 and the electrode 308 and partially etching the insulating layer by anisotropic etching mainly in the vertical direction. can do. Note that the gate insulating layer 306 may be partially etched by the anisotropic etching described above. As the insulating layer for forming the sidewall 314, a film containing silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, an organic material, or the like is formed by a plasma CVD method, a sputtering method, or the like. A stacked structure may be used. In this embodiment, a silicon oxide film with a thickness of 100 nm is formed by a plasma CVD method. As the etching gas, a mixed gas of CHF ₃ and helium can be used. Note that the step of forming the sidewall 314 is not limited to these steps.

  Next, an impurity element imparting one conductivity type is added to the semiconductor layers 302 and 304 using the gate insulating layer 306, the electrodes 308, and the sidewalls 314 as masks (see FIG. 4C). Note that an impurity element having the same conductivity type as the impurity element added in the previous step is added to the semiconductor layer 302 and the semiconductor layer 304 at a higher concentration. Note that when the n-type impurity element is added to the semiconductor layer 302, the semiconductor layer 304 to which the p-type impurity is added is covered with a mask or the like, and the addition of the n-type impurity element is selectively performed. To be done. In addition, when an impurity element imparting p-type conductivity is added to the semiconductor layer 304, the semiconductor layer 302 to which an n-type impurity is added is covered with a mask or the like, and the impurity element imparting p-type conductivity is selectively added. To be done.

  By the addition of the impurity element, a pair of high-concentration impurity regions 316, a pair of low-concentration impurity regions 318, and a channel formation region 320 are formed in the semiconductor layer 302. In addition, by adding the impurity element, a pair of high-concentration impurity regions 322, a pair of low-concentration impurity regions 324, and a channel formation region 326 are formed in the semiconductor layer 304. The high concentration impurity region 316 and the high concentration impurity region 322 function as a source or a drain, and the low concentration impurity region 318 and the low concentration impurity region 324 function as an LDD (Lightly Doped Drain) region.

  Note that the side wall 314 formed over the semiconductor layer 302 and the side wall 314 formed over the semiconductor layer 304 have the same length in the direction in which carriers move (a direction parallel to a so-called channel length). However, they may be formed differently. The length of the sidewall 314 over the semiconductor layer 304 serving as a p-channel transistor is preferably larger than the length of the sidewall 314 over the semiconductor layer 302 serving as an n-channel transistor. This is because boron implanted to form a source and a drain in a p-channel transistor easily diffuses and easily induces a short channel effect. In the p-channel transistor, by increasing the length of the sidewall 314, high-concentration boron can be added to the source and the drain, and the resistance of the source and the drain can be reduced.

  In order to further reduce the resistance of the source and drain, a silicide layer in which part of the semiconductor layer 302 and the semiconductor layer 304 is silicided may be formed. Silicidation is performed by bringing a metal into contact with the semiconductor layer and reacting silicon in the semiconductor layer with the metal by heat treatment (eg, GRTA method, LRTA method, etc.). As the silicide layer, cobalt silicide or nickel silicide may be used. When the semiconductor layer 302 or the semiconductor layer 304 is thin, the silicide reaction may be advanced to the bottom of the semiconductor layer 302 or the semiconductor layer 304. Metal materials that can be used for silicidation include titanium (Ti), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), zirconium (Zr), Ha (hafnium), and tantalum (Ta). ), Vanadium (V), neodymium (Nb), chromium (Cr), platinum (Pt), palladium (Pd), and the like. The silicide layer can also be formed by laser light irradiation or the like.

  Through the above steps, an n-channel transistor 328 and a p-channel transistor 330 are formed. Note that although a conductive layer functioning as a source electrode or a drain electrode is not formed in the stage illustrated in FIG. 4C, the conductive layer functioning as the source electrode or the drain electrode may be referred to as a transistor. .

  Next, an insulating layer 332 is formed so as to cover the n-channel transistor 328 and the p-channel transistor 330 (see FIG. 4D). Although the insulating layer 332 is not necessarily provided, the formation of the insulating layer 332 can prevent impurities such as an alkali metal and an alkaline earth metal from entering the n-channel transistor 328 and the p-channel transistor 330. Specifically, the insulating layer 332 is preferably formed using a material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxide. In this embodiment, a silicon nitride oxide film with a thickness of about 600 nm is used as the insulating layer 332. In this case, the above-described hydrogenation step may be performed after the silicon nitride oxide film is formed. Note that although the insulating layer 332 has a single-layer structure in this embodiment, it is needless to say that a stacked structure may be used. For example, in the case of a two-layer structure, a stacked structure of a silicon oxynitride film and a silicon nitride oxide film can be employed.

  Next, an insulating layer 334 is formed over the insulating layer 332 so as to cover the n-channel transistor 328 and the p-channel transistor 330. The insulating layer 334 is preferably formed using an organic material having heat resistance such as polyimide, acrylic, polyimide, benzocyclobutene, polyamide, or epoxy. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane resins, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, PSG (phosphorus glass), BPSG (phosphorus boron glass) Alumina or the like can also be used. Here, the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin may have one selected from fluorine, an alkyl group, and an aromatic hydrocarbon in addition to hydrogen as a substituent. Note that the insulating layer 334 may be formed by stacking a plurality of insulating layers formed using these materials.

  Depending on the material, the insulating layer 334 can be formed by CVD, sputtering, SOG, spin coating, dipping, spray coating, droplet ejection (inkjet, screen printing, offset printing, etc.), doctor knife, A roll coater, curtain coater, knife coater, or the like can be used.

Next, contact holes are formed in the insulating layer 332 and the insulating layer 334 so that the semiconductor layer 302 and part of the semiconductor layer 304 are exposed. Then, a conductive layer 336 and a conductive layer 338 which are in contact with the semiconductor layer 302 and the semiconductor layer 304 through the contact holes are formed (see FIG. 5A). The conductive layer 336 and the conductive layer 338 function as a source electrode or a drain electrode of the transistor. In the present embodiment, a mixed gas of CHF ₃ and He is used as a gas used for etching when the contact hole is opened. However, the present invention is not limited to this.

  The conductive layers 336 and 338 can be formed by a CVD method, a sputtering method, or the like. Specifically, as the conductive layer 336 and the conductive layer 338, aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or the like can be used. Alternatively, an alloy containing the above material as its main component or a compound containing the above material may be used. Further, the conductive layer 336 and the conductive layer 338 may have a single-layer structure or a stacked structure.

  As an example of an alloy containing aluminum as a main component, an alloy containing aluminum as a main component and containing nickel can be given. Further, examples include aluminum as a main component and one or both of nickel and carbon or silicon. Aluminum and aluminum silicon (Al—Si) have low resistance and are inexpensive, and thus are suitable as materials for forming the conductive layers 336 and 338. In particular, aluminum silicon is preferable because generation of hillocks due to resist baking during patterning can be suppressed. Further, instead of silicon, a material in which about 0.5% Cu is mixed in aluminum may be used.

  When the conductive layer 336 and the conductive layer 338 have a stacked structure, for example, a stacked structure of a barrier film, an aluminum silicon film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon film, a titanium nitride film, and a barrier film is employed. Good. Note that a barrier film is a film formed using titanium, titanium nitride, molybdenum, molybdenum nitride, or the like. When the conductive layer is formed so that the aluminum silicon film is sandwiched between the barrier films, generation of hillocks of aluminum or aluminum silicon can be further prevented. In addition, when a barrier film is formed using titanium which is a highly reducing element, even if a thin oxide film is formed over the semiconductor layer 302 and the semiconductor layer 304, titanium included in the barrier film forms the oxide film. By reducing, the contact between the conductive layer 336 and the semiconductor layer 302 and between the conductive layer 338 and the semiconductor layer 304 can be improved. Alternatively, a plurality of barrier films may be stacked. In that case, for example, the conductive layer 336 and the conductive layer 338 can have a five-layer structure or a stacked structure of more layers such as titanium, titanium nitride, aluminum silicon, titanium, and titanium nitride from the lower layer.

Alternatively, tungsten silicide formed by a chemical vapor deposition method using WF ₆ gas and SiH ₄ gas may be used for the conductive layers 336 and 338. Alternatively, tungsten formed by hydrogen reduction of WF ₆ may be used for the conductive layer 336 and the conductive layer 338.

  Note that the conductive layer 336 is connected to the high-concentration impurity region 316 of the n-channel transistor 328. The conductive layer 338 is connected to the high concentration impurity region 322 of the p-channel transistor 330.

  FIG. 5B is a plan view of the n-channel transistor 328 and the p-channel transistor 330 illustrated in FIG. Here, a cross section taken along line MN in FIG. 5B corresponds to FIG. Note that in FIG. 5B, the conductive layer 336, the conductive layer 338, the insulating layer 332, the insulating layer 334, and the like are omitted for simplicity.

  Note that although the case where the n-channel transistor 328 and the p-channel transistor 330 each include one electrode 308 functioning as a gate electrode is described in this embodiment, the present invention is limited to this structure. Not. The transistor manufactured according to the present invention may have a multi-gate structure in which a plurality of electrodes functioning as gate electrodes are provided and the plurality of electrodes are electrically connected.

  In this embodiment mode, a semiconductor device (transistor) is manufactured using a semiconductor substrate in which the number of reuses of the bond substrate is improved. Therefore, an inexpensive semiconductor device with a sufficiently reduced manufacturing cost can be provided. In addition, by increasing the thickness of the semiconductor layer separated from the bond substrate, bonding defects in the manufacturing process of the semiconductor substrate can be reduced; thus, a highly reliable and high-performance semiconductor device can be provided using the semiconductor layer. Is possible.

  This embodiment can be used in combination with Embodiment 1.

(Embodiment 3)
In this embodiment, electronic devices using the semiconductor device manufactured in Embodiment 2 will be described with reference to FIGS.

  Electronic devices manufactured using a semiconductor device include a video camera, a digital camera, a goggle-type display (head-mounted display), a navigation system, an audio playback device (such as a car audio component), a computer, a game device, and a portable information terminal ( A display capable of playing back a recording medium such as a mobile computer, a mobile phone, a portable game machine, or an electronic book) and an image playback apparatus (specifically, Digital Versatile Disc (DVD)) and displaying the image. And the like).

  Note that a semiconductor device using the semiconductor substrate of the present invention is applied to a display portion (including a pixel portion and a driver circuit portion), a CPU, a memory, and the like in an electronic device.

  FIG. 6A illustrates a television receiver or a personal computer monitor. A housing 601, a support base 602, a display unit 603, a speaker unit 604, a video input terminal 605, and the like are included. A semiconductor device of the present invention is used for the display portion 603. According to the present invention, a highly reliable and high performance television receiver or personal computer monitor can be provided at a low price.

  FIG. 6B illustrates a digital camera. An image receiving portion 613 is provided on the front portion of the main body 611, and a shutter button 616 is provided on the upper surface portion of the main body 611. In addition, a display portion 612, operation keys 614, and an external connection port 615 are provided on the back surface of the main body 611. The semiconductor device of the present invention is used for the display portion 612, a CPU (not shown), a memory (not shown), and the like. According to the present invention, a highly reliable and high-performance digital camera can be provided at a low price.

  FIG. 6C illustrates a laptop personal computer. The main body 621 is provided with a keyboard 624, an external connection port 625, and a pointing device 626. In addition, a housing 622 having a display portion 623 is attached to the main body 621. The semiconductor device of the present invention is used for the display portion 623, a CPU (not shown), a memory (not shown), and the like. According to the present invention, a notebook personal computer with high reliability and high performance can be provided at a low price.

  FIG. 6D illustrates a mobile computer, which includes a main body 631, a display portion 632, a switch 633, operation keys 634, an infrared port 635, and the like. The display portion 632 is provided with an active matrix display device. The semiconductor device of the present invention is used for the display portion 632, CPU (not shown), memory (not shown), and the like. According to the present invention, a highly reliable and high performance mobile computer can be provided at a low price.

  FIG. 6E shows an image reproducing device. The main body 641 is provided with a display portion B 644, a recording medium reading portion 645, and operation keys 646. Further, a housing 642 including a speaker portion 647 and a display portion A 643 is attached to the main body 641. The semiconductor device of the present invention is used for the display portion A 643, the display portion B 644, a CPU (not shown), a memory (not shown), and the like. According to the present invention, a highly reliable and high performance image reproducing apparatus can be provided at a low price.

  FIG. 6F illustrates an electronic book. An operation key 653 is provided on the main body 651. A plurality of display portions 652 are attached to the main body 651. The semiconductor device of the present invention is used for the display portion 652, a CPU (not shown), a memory (not shown), and the like. According to the present invention, a highly reliable electronic book with high performance can be provided at a low price.

  FIG. 6G illustrates a video camera. A main body 661 is provided with an external connection port 664, a remote control receiver 665, an image receiver 666, a battery 667, an audio input unit 668, and operation keys 669. A housing 663 having a display portion 662 is attached to the housing. The semiconductor device of the present invention is used for the display portion 662, a light receiving element (not shown), a CPU (not shown), a memory (not shown), and the like. According to the present invention, a highly reliable video camera with high performance can be provided at a low price.

  FIG. 6H illustrates a cellular phone, which includes a main body 671, a housing 672, a display portion 673, an audio input portion 674, an audio output portion 675, operation keys 676, an external connection port 677, an antenna 678, and the like. The semiconductor device of the present invention is used for the display portion 673, CPU (not shown), memory (not shown), and the like. According to the present invention, a highly reliable and high-performance mobile phone can be provided at a low price.

  FIG. 7 shows an example of the configuration of a portable electronic device 700 having both a telephone function and an information terminal function. 7A is a front view, FIG. 7B is a rear view, and FIG. 7C is a development view. The portable electronic device 700 is an electronic device called a smartphone that has both functions of a telephone and an information terminal and can perform various data processing in addition to voice calls.

  The portable electronic device 700 includes a housing 701 and a housing 702. The housing 701 includes a display portion 711, a speaker 712, a microphone 713, operation keys 714, a pointing device 715, a camera lens 716, an external connection terminal 717, and the like. The housing 702 includes a keyboard 721, an external memory slot 722, a camera Lens 723, light 724, earphone terminal 725, and the like. An antenna is built in the housing 701. In addition to the above structure, a non-contact IC chip, a small recording device, or the like may be incorporated.

  The semiconductor device of the present invention is incorporated in a display portion 711, a light receiving element (not shown), a CPU (not shown), a memory (not shown), and the like. Note that the video (and the display direction) displayed on the display unit 711 varies depending on how the portable electronic device 700 is used. In addition, since the camera lens 716 is provided on the same surface as the display portion 711, a voice call with a video (so-called videophone) is possible. Note that the speaker 712 and the microphone 713 can be used not only for voice calls but also for recording and reproduction. When taking a still image and a moving image using the camera lens 723 (and the light 724), the display unit 711 is used as a viewfinder. The operation keys 714 are used for making and receiving calls, inputting simple information such as e-mails, scrolling the screen, moving the cursor, and the like.

  The housings 701 and 702 overlapped with each other (FIG. 7A) slide and can be developed as shown in FIG. 7C, so that they can be used as information terminals. In this case, smooth operation using the keyboard 721 and the pointing device 715 is possible. The external connection terminal 717 can be connected to various cables such as an AC adapter and a USB cable, and enables charging and data communication with a computer or the like. In addition, a recording medium can be inserted into the external memory slot 722 to support storage and movement of a larger amount of data. In addition to the above functions, a wireless communication function using an electromagnetic wave such as infrared rays, a television reception function, or the like may be provided. According to the present invention, a portable electronic device with high reliability and high performance can be provided at a low price.

  As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. Note that this embodiment can be used in combination with Embodiments 1 and 2.

It is a figure explaining the manufacturing method of a semiconductor substrate. It is a figure explaining the manufacturing method of a semiconductor substrate. FIG. 6 illustrates a manufacturing process of a semiconductor device. FIG. 6 illustrates a manufacturing process of a semiconductor device. It is the top view and sectional view of a semiconductor device. FIG. 11 illustrates an electronic device using a semiconductor device. FIG. 11 illustrates an electronic device using a semiconductor device.

Explanation of symbols

100 base substrate 102 base substrate 110 bond substrate 112 insulating layer 114 damaged region 116 insulating layer 118 semiconductor layer 120 substrate 122 semiconductor layer 124 insulating layer 126 damaged region 128 insulating layer 130 semiconductor layer 132 semiconductor layer 140 substrate 142 substrate 150 ion beam 152 ion Beam 160 Regenerative bond substrate 170 Semiconductor substrate 172 Semiconductor substrate 300 Semiconductor layer 302 Semiconductor layer 304 Semiconductor layer 306 Gate insulating layer 308 Electrode 310 Impurity region 312 Impurity region 314 Side wall 316 High concentration impurity region 318 Low concentration impurity region 320 Channel formation region 322 High-concentration impurity region 324 Low-concentration impurity region 326 Channel formation region 328 n-channel transistor 330 p-channel transistor 332 Insulating layer 334 Insulating layer 33 Conductive layer 338 Conductive layer 601 Housing 602 Support base 603 Display unit 604 Speaker unit 605 Video input terminal 611 Main unit 612 Display unit 613 Image receiving unit 614 External connection port 616 Shutter button 621 Main unit 622 Housing 623 Display unit 624 Keyboard 625 External Connection port 626 Pointing device 631 Main unit 632 Display unit 633 Switch 634 Operation key 635 Infrared port 641 Main unit 642 Case 643 Display unit A
644 Display B
645 Recording medium reading unit 646 Operation key 647 Speaker unit 651 Main unit 652 Display unit 653 Operation key 661 Main unit 662 Display unit 663 Case 664 External connection port 665 Remote control receiving unit 666 Image receiving unit 667 Battery 668 Audio input unit 669 Operation key 671 Main unit 672 Enclosure 673 Display unit 674 Audio input unit 675 Audio output unit 676 Operation key 677 External connection port 678 Antenna 700 Portable electronic device 701 Case 702 Case 711 Display unit 712 Speaker 713 Microphone 714 Operation key 715 Pointing device 716 Camera lens 717 External connection terminal 721 Keyboard 722 External memory slot 723 Camera lens 724 Light 725 Earphone terminal

Claims (8)

Irradiating one surface of the bond substrate with ions to form a first damaged region;
Forming a first insulating layer on one surface of the bond substrate;
Bringing the first base substrate and the surface of the first insulating layer into contact with each other, and bonding the first base substrate and the bond substrate;
Performing a first heat treatment to separate the bond substrate in the first damaged region to form a first semiconductor layer on the first base substrate;
Planarizing the surface of the first semiconductor layer;
Irradiating one surface of the first semiconductor layer with ions to form a second damaged region;
Forming a second insulating layer on one surface of the first semiconductor layer;
Bringing the second base substrate and the surface of the second insulating layer into contact with each other, and bonding the second base substrate and the first semiconductor layer together;
By performing a second heat treatment, the first semiconductor layer is separated in the second damaged region to form a second semiconductor layer on the first base substrate, and the second base substrate A method for manufacturing a semiconductor substrate, comprising forming a third semiconductor layer thereon. In claim 1,
A method for manufacturing a semiconductor substrate, wherein the bond substrate is reused by planarizing a surface of the separated bond substrate. In claim 1 or 2,
A method for manufacturing a semiconductor substrate, wherein a protective insulating layer is formed over one surface of the bond substrate before the ion irradiation. In any one of Claims 1 thru | or 3,
A method for manufacturing a semiconductor substrate, wherein a protective insulating layer is formed over one surface of the first semiconductor layer before irradiation with the ions. In any one of Claims 1 thru | or 4,
The method for manufacturing a semiconductor substrate, wherein the ions irradiated to the bond substrate contain H ⁺ as a main component. In any one of Claims 1 thru | or 5,
The method for manufacturing a semiconductor substrate, wherein the ions irradiated to the first semiconductor layer contain H ₃ ⁺ as a main component. In any one of Claims 1 thru | or 6,
The planarization is performed using any one of etching treatment, laser light irradiation treatment, heat treatment, and polishing treatment. In any one of Claims 1 thru | or 7,
A method for manufacturing a semiconductor substrate, wherein a plurality of semiconductor substrates are manufactured using the second semiconductor layer or the third semiconductor layer.

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