Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
  • B81C1/00349—Creating layers of material on a substrate
  • B81C1/00365—Creating layers of material on a substrate having low tensile stress between layers
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
  • C30B25/02—Epitaxial-layer growth
  • C30B25/18—Epitaxial-layer growth characterised by the substrate
  • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/0237—Materials
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  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02367—Substrates
  • H01L21/02428—Structure
  • H01L21/0243—Surface structure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02439—Materials
  • H01L21/02441—Group 14 semiconducting materials
  • H01L21/0245—Silicon, silicon germanium, germanium
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02436—Intermediate layers between substrates and deposited layers
  • H01L21/02494—Structure
  • H01L21/02513—Microstructure
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02656—Special treatments
  • H01L21/02658—Pretreatments
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02104—Forming layers
  • H01L21/02365—Forming inorganic semiconducting materials on a substrate
  • H01L21/02656—Special treatments
  • H01L21/02664—Aftertreatments
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B81—MICROSTRUCTURAL TECHNOLOGY
  • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
  • B81C2201/00—Manufacture or treatment of microstructural devices or systems
  • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
  • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
  • B81C2201/0191—Transfer of a layer from a carrier wafer to a device wafer

Definitions

• the invention relates to the field of substrates for crystal growth (epitaxial growth), as well as to crystal growth techniques using such substrates.
• GaN epitaxies are known by MOCVD technique for obtaining thick GaN layers (> 1-2 ⁇ m) on an epitaxy substrate.
• MOCVD technique for obtaining thick GaN layers (> 1-2 ⁇ m) on an epitaxy substrate.
• massive substrates sapphire, SiC and Si. These three substrates are the most used because the most available.
• substrates such as ZnO or LiGaO2.
• the epitaxial GaN layers deposited homogeneously on the surface of the substrate have a dislocation density between 10 8 and 10 10 / cm 2, regardless of the nucleation surface used.
• the state of stresses of thick layers of GaN obtained by MOCVD depends of course on the coefficient of thermal expansion of the epitaxy substrate which will determine the stresses of thermoelastic origin imposed on the system.
• the GaN layers obtained on sapphire are in compression while those obtained on SiC are slightly in tension and those on silicon highly in tension. This results, for the layers in tension, a strong tendency to form cracks in the epitaxial film, which destroys it. Compression layers are also a problem. This phenomenon is particularly true for growths on silicon. For this epitaxy support, the limit beyond which cracks appear is approximately 1 to 2 ⁇ m, which is a limiting factor as regards the obtaining of layers of good qualities.
• SOI Silicon on Insulator
• the crystalline quality seems to be able to be improved by growth on substrates with patterns.
• the dislocation densities obtained are of the order of 10 6 / cm 2 .
• the continuous films obtained have precise zones improved in crystal quality (case of the ELOG technique) or else have a homogeneous film in crystal quality (case of the LOFT technique). These techniques have been demonstrated on sapphire, SiC and Si 111.
• the problem therefore arises of producing a substrate or a support capable of absorbing, during crystal growth, a significant level of stresses, in particular during a thick epitaxy of material, and in particular in the case where the coefficient of expansion of the material is different or very different from that of the substrate or of the epitaxy support.
• the invention relates firstly to a support for crystal growth comprising: a nucleation or growth layer, - a buffer layer, or intermediate layer, polycrystalline or porous, or amorphous, a base substrate.
• the buffer layer makes it possible to absorb or accommodate the stresses appearing during an epitaxial growth carried out on the nucleation or growth layer of the support.
• the nucleation layer can be a layer of monocrystalline material, for example Si or SiC or GaN, or sapphire or AIN or diamond. It can be obtained by transfer from another substrate.
• the support substrate may be made of Si or SiC, and the buffer layer of amorphous silicon or of porous silicon or of polysilicon or of amorphous silicon dioxide SiO2 or of amorphous silicon nitride S13N4 or of silicon carbide or of nitride of nitrous oxide Gallium (GaN) or sapphire or aluminum nitride (AIN).
• the buffer layer of amorphous silicon or of porous silicon or of polysilicon or of amorphous silicon dioxide SiO2 or of amorphous silicon nitride S13N4 or of silicon carbide or of nitride of nitrous oxide Gallium (GaN) or sapphire or aluminum nitride (AIN).
• the nucleation layer is made of silicon
• the buffer layer is polycrystalline or porous
• the base substrate being made of silicon
• a layer of electrical insulator is also included between the nucleation layer and the buffer layer.
• the insulating layer can then be an oxide layer (for example of silicon) or a layer of boro-phospho-silicate glass.
• oxide layer for example of silicon
• boro-phospho-silicate glass a layer of boro-phospho-silicate glass.
• an intermediate layer is therefore formed between, on the one hand, the base substrate and, on the other hand, either the nucleation layer or the SOI bilayer (surface silicon layer and insulating layer (for example: silicon oxide)).
• mechanical absorption means or a mechanical system are formed on the base substrate making it possible to absorb the thermoelastic stresses generated at the surface.
• This mechanical system comprises, for example, a network of absorbing elements, which can be obtained by machining the base substrate, for example by ion etching.
• the invention also relates to a support for crystal growth comprising at least one nucleation or growth layer, and a base substrate, in which patterns are etched.
• the nucleation layer and the base substrate can be made of silicon, an oxide or electrical insulator layer being situated between the nucleation layer and the substrate.
• This second embodiment is therefore also compatible with an SOI type structure.
• a buffer layer may be located between, on the one hand, the nucleation or growth layer, or the oxide layer, and, on the other hand, the base substrate, this buffer layer being for example polycrystalline or porous, for example in Si or in amorphous silicon or in porous silicon or in polysilicon or in SiC or in GaN or in sapphire or in AIN.
• An epitaxial growth method according to the invention can be carried out on a support according to the invention, as defined above.
• FIGS. 1 and 2 represent a first embodiment of the invention
• FIGS. 3A to 4 represent a second embodiment of the invention
• FIGS. 5A and 5B represent steps of a method of substrate fracture.
• a buffer or intermediate layer capable of absorbing an amount of stresses, for example by generation of crystal defects in this layer or by mechanical displacement of material in this layer.
• a nucleation layer 2 a buffer layer 4 as mentioned above are indicated, and a support substrate 6 such as Si or SiC or sapphire (Al 2 O 3 ) or aluminum nitride (AIN) or diamond.
• the buffer layer 4 is for example a poly-crystalline or porous or amorphous layer.
• Si Silicon
• SiC silicon carbide
• GaN gallium nitride
• AIN aluminum nitride
• SiO2 silicon dioxide
• the buffer layer may be a thin layer of amorphous silicon, polysilicon or porous silicon (obtained by intentional porosification or by porous deposition).
• the nucleation layer 2 is for example a layer of monocrystalline material, obtained by transfer of a thin layer from a first substrate, for example by the fracture process known under the name of "Smart Cut” (see FIGS. 5A and 5B on this subject, or the article by AJ Auberton-Hervé cited later in this description).
• the nucleation layer has a thickness of the order of 0.1 to 2 ⁇ m, for example 0.5 ⁇ m
• the buffer layer has a thickness of the order of a few tenths of ⁇ m, for example of approximately 0, 01 ⁇ m to approximately 1 ⁇ m or 2 ⁇ m
• the substrate may have a thickness of approximately several hundred ⁇ m, or between 100 ⁇ m and 700 ⁇ m, for example approximately 500 ⁇ m or 525 ⁇ m.
• the coefficients of thermal expansion ci and c 2 of the nucleation layer 2 and of the substrate 6 can be different.
• SiC has a coefficient of thermal expansion of 4.5.10 "6 K " 1
• Si a coefficient of 2.5.10 -6 K "1
• alumina (AI 2 O 3 ) a coefficient of 7.10- 6 K -1 .
• This difference in the coefficients of the layer 2 and of the substrate 6 can generate stresses during temperature rise or fall phases, especially when the relative difference Ici - c 2 l / c ⁇ or Ici - C2I / C 2 is d '' at least 10% or 20% or 30% at room temperature, i.e. at about 20 ° C or 25 ° C.
• the stresses generated during a temperature excursion are absorbed by the buffer layer 4.
• the stresses are absorbed there by generation of defects.
• the porosities allow local movements of material which mechanically absorb tensions or stresses.
• the preferred mode of stress relaxation is by creep of the layers present.
• the invention also applies to an SOI type structure, in which the oxide is not a silicon oxide, but an oxide which becomes viscous at a lower temperature, for example a glass of borophospho-silicate (BPSG). If the layer is viscous, it absorbs tensions and stresses by creep.
• BPSG borophospho-silicate
• This same type of buffer layer can be inserted in an SOI structure, between the oxide or insulating layer and the substrate.
• a structure is shown in FIG. 2, where the reference 10 designates a thin layer of semiconductor material, preferably monocrystalline, for example made of silicon or silicon carbide SiC or gallium nitride GaN or sapphire or AIN .
• the reference 12 designates a layer of SiO2 oxide, the layer 14 the buffer layer, and the reference 16 a substrate of a semiconductor material, for example thick silicon.
• the oxide layer also acts as a stress accommodation layer, since the crystal growth processes take place at temperatures of the order of several hundred degrees (for example: 1000 ° C. ). At these temperatures, the oxide becomes viscous and absorbs some of the stresses.
• the buffer layer 14 will also absorb some of these stresses, but in a different way since it does not become viscous.
• the relative difference in coefficient of thermal expansion between the nucleation layer 10 and the substrate 16 can therefore here also be greater than 10% or 20% or 30% at room temperature (20 ° C or 25 ° C).
• the buffer layer 14 can for example result from a deposition of amorphous or polycrystalline silicon which can collect and absorb stresses, and for example has a thickness between 10 nm and 1 ⁇ m or between 0, 1 ⁇ m and 2 ⁇ m.
• the layer 10, which can be formed by transfer has a thickness of approximately 10 nm to 300 nm or even between 0.1 ⁇ m and 2 ⁇ m.
• the layer 12, which can be formed by deposition, has a thickness of the order of a few hundred nm, between for example 100 nm and 700 nm, for example 400 nm.
• the substrate 10 can have substantially the same thickness as the substrate 6 in FIG. 1.
• a layer 22 of elastic accommodation, or having a certain elasticity at least in an xy plane, parallel to the plane of the different layers, is generated in a substrate 20, or rigid support. 24, 26.
• This layer 22 is for example obtained by etching, in the substrate 20, studs, or trenches, or any other geometric pattern. These patterns have an elasticity or are flexible in a plane parallel to the planes of the layers 24, 26.
• the resulting elasticity can be calculated by applying the classical theory of beams.
• an elastic accommodation layer 23 similar to that of FIG. 3A, could also be formed on the rear face of the substrate 20, which makes it possible to avoid any problems of adhesion between layer 26 and substrate 20 which may appear in the configuration of FIG. 3A.
• This variant also makes it possible to absorb the stresses.
• FIGS. 3A and 3B can be present in the same substrate.
• notches 25, such as for example “saw cuts” are made in the substrate 20, on one side and / or the other of the substrate.
• a stress absorption effect is obtained.
• the engraved or hollowed out patterns are preferably repeated according to a two-dimensional periodicity or according to a single dimension as illustrated in FIG. 4.
• the layers 24, 26 and the substrate 20 can be identical or similar to the layers 2, 4 and to the substrate 6 of FIG. 1, with the same typical thicknesses, and obtained with the same techniques.
• the nucleation layer 24 can for example be a layer of monocrystalline material, obtained by thin layer transfer from a first substrate, for example by the “Smart Cut” or substrate fracture process (the steps of which are described below in connection with FIGS. 5A and 5B), and the buffer layer 26 can be, for example, a polycrystalline or porous layer, Si, or SiC, or GaN, or sapphire or AIN.
• FIGS. 3A, 3B or 3C can also be an SOI type structure, the layer 26 being an oxide or insulating layer and the layer 24 being a layer of fine silicon.
• the fact of bonding on a substrate with trenches can modify the bonding step, in particular because the surface contact can be significantly reduced (by around 50% for example).
• the geometric parameters of the patterns for example the width and / or the periodicity of these patterns.
• the surface is made of silicon
• an improper deposition is carried out (with an oxide for example) which will clog the surface trenches.
• This deposition can be carried out by a filling method of the “trench isolation” type, or STI (abbreviation of the English expression “Shallow Trench Isolation”) which is not optimized.
• STI abbreviation of the English expression “Shallow Trench Isolation”
• Such a method is for example described in CPChang et al. : "A highly manufacturable corner rounding solution for 0.18 ⁇ m shallow trench insulation", IEMD 97 - 661.
• a first step an ionic or atomic implantation is carried out in the substrate 40, forming a thin layer 52 which extends substantially parallel to the surface 41 of the substrate 40.
• a layer or a plane is thus formed weakening or fracture defining in the volume of the substrate 40 a lower region 45 intended to constitute a thin film and an upper region 44 constituting the mass of the substrate 40.
• This implantation is generally an implantation of hydrogen, but can also be done using other species, or with a hydrogen / helium co-location.
• the substrate 42 is for example provided with etched patterns, as described above.
• the etching is carried out from the surface 43 and / or from the surface 47.
• the two substrates 40 and 42 thus prepared are then assembled, face 43 against face 41, by a technique of "wafer bonding" type (assembly of wafers by any technique known in the field of microelectronics) or by contact of adherent type (by example by molecular adhesion) or by bonding.
• wafer bonding assembly of wafers by any technique known in the field of microelectronics
• adherent type by example by molecular adhesion
• bonding we can refer, with regard to these techniques, to the work by QY Tong and U. Gôsele "Semiconductor Wafer Bonding", (Science and Technology), Wiley Interscience Publications.
• a portion 44 of the substrate 40 is then removed by a thermal or mechanical treatment making it possible to cause a fracture along the embrittlement plane 52.
• An example of this technique is described in the article by A. Auberton-Henté et al. Cited above. The structure obtained is that of FIG. 5B. It may be desirable, in order to reinforce the bonding or assembly interface between the substrate 42 (or its face 43) and the thin layer 45 (or the contact face 41), to effect a temperature rise which can reach approximately 1000 ° C.
• the structure of patterns etched in the substrate 42 makes it possible to compensate for or absorb the stresses and the differences in variations due to the difference between the coefficients of thermal expansion. of the two substrates 40, 42.
• the relative difference between these coefficients can be, as already indicated above, at least 10% or at least 20% or at least 30% at room temperature.
• the film 45 can also be a nucleation or growth layer such as layer 2, 10 or 24 of FIGS. 1 - 3C (the substrate
• Figure 5B being similar to the substrate 6, 16, 20 of FIGS. 1 to 4). Unlike the latter, however, the structure of Figure 5B does not have a buffer layer.
• the film 45 can also be replaced by a set of superimposed films.
• this aspect of the invention relates not only to a monolayer system on a substrate, but to any multilayer system implementing deposition of the layers on a substrate.

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