EP1565949A2 - Memoire a semi-conducteur et son procede de production - Google Patents

Memoire a semi-conducteur et son procede de production

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Publication number
EP1565949A2
EP1565949A2 EP03788820A EP03788820A EP1565949A2 EP 1565949 A2 EP1565949 A2 EP 1565949A2 EP 03788820 A EP03788820 A EP 03788820A EP 03788820 A EP03788820 A EP 03788820A EP 1565949 A2 EP1565949 A2 EP 1565949A2
Authority
EP
European Patent Office
Prior art keywords
electrode
semiconductor memory
memory device
cavity
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP03788820A
Other languages
German (de)
English (en)
Inventor
Thomas Mikolajick
Wolfgang Werner
Helmut Klose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1565949A2 publication Critical patent/EP1565949A2/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H10N70/8616—Thermal insulation means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the present invention relates to a semiconductor memory device and a method for its production.
  • non-volatile memories are known in which the storage medium changes from a low-resistance, possibly crystalline, state to a high-resistance, possibly amorphous, state during a phase transition.
  • a material is used as the storage medium that has two stable phases, namely a high-resistance amorphous and a low-resistance crystalline phase. The material can be reversibly switched back and forth in relation to these two phases by means of electrical pulses.
  • chalcogenides have hitherto usually been used for this purpose, in principle any material is suitable as a storage medium for these non-volatile memories which allows reversible switching between a high-resistance and a low-resistance state.
  • the problem with known semiconductor memory technologies based on a phase change memory effect is that a certain amount of heat has to be supplied to the respective memory cell or the respective memory element in order to initiate and carry out the phase change. It must be prevented that the amount of heat supplied also influences neighboring cells or elements and changes their information status.
  • the invention is based on the object of specifying a semiconductor memory device based on a phase change memory effect and a method for its production, by means of which semiconductor memory devices having a phase change memory effect can be implemented with a particularly high integration density and nevertheless high functional reliability.
  • the object is achieved according to the invention by a semiconductor memory device according to the characterizing features of claim 1. Furthermore, the object is achieved by a method for producing a semiconductor memory device in accordance with the characterizing feature of claim 11.
  • the semiconductor memory device has at least one memory element with a phase change memory effect and is characterized in that a cavity arrangement with at least one cavity in spatial proximity to the respective memory element is provided for the at least one memory element in a semiconductor substrate such that the thermal coupling of the respective memory element is reduced to the environment of the memory cell by reducing the thermal conductivity between the memory element and the environment.
  • the respective cavity avoids the provision of a material which has a certain residual thermal conductivity.
  • the cavity whether evacuated or gas-filled, always has a lower thermal conductivity than a correspondingly designed material area, so that the thermal coupling between the memory cell and its surroundings, namely the semiconductor substrate or a neighboring element, is reduced.
  • a particularly advantageous embodiment of the semiconductor memory device according to the invention results if a first or lower access electrode device, a second or upper access electrode device and an at least partially formed storage medium with phase-dependent ohmic resistance with the access electrodes for the memory element in the semiconductor substrate.
  • the devices contacted is provided.
  • At least one of the access electrode devices, preferably the first or lower access electrode device, is provided and designed as an excitation electrode or heating electrode for locally heating the contacted storage medium and thus for initiating a corresponding phase conversion process or a corresponding phase conversion.
  • At least part of the cavity arrangement in particular at least one cavity, is provided in close proximity to the excitation electrode and / or in close proximity to the storage medium for thermal insulation from the surroundings.
  • the element which carries most of the heat and is therefore most likely to have a high temperature namely the electrode which is designed to heat the storage medium and thus to excite the phase change process, becomes thermal from the environment by providing the cavity insulated so that heat transfer to the environment and in particular to adjacent storage elements that are not selected is at least reduced.
  • a cavity of the cavity arrangement to be assigned to the excitation electrode and for the associated cavity to directly adjoin at least a part of the excitation electrode.
  • the associated cavity surrounds at least part of the excitation electrode.
  • the excitation electrode is designed as a connection region or plug region or as part thereof to a source / drain region of an intended and assigned selection transistor, in particular a lateral selection transistor. This results in a particularly compact design of the semiconductor memory device according to the invention, because an additional contact, connection or plug between the source / drain region of the selection transistor and the respective first, lower or bottom electrode is not necessary when forming the respective memory element.
  • the excitation electrode is formed in a recess or a trench structure or a trench, specifically in the semiconductor substrate on which the semiconductor memory device is based.
  • the storage medium is designed as a material area of the excitation electrode, in particular in an upper area of the trench structure.
  • This embodiment is also particularly space-saving, because the storage medium with phase conversion memory effect is also designed and provided in the connection area or plug area serving as the excitation electrode toward the source / drain area of the selection transistor. This is achieved in particular by filling an upper part of the underlying trench structure.
  • a plurality of memory elements can and will be provided in the semiconductor memory device according to the invention. It is advantageous here if a common memory area with a phase change memory effect is formed for the plurality of memory elements. Alternatively, individual storage areas can also be formed for the plurality of storage elements. However, it is particularly advantageous if two memory elements, which are formed adjacent to each other in the semiconductor substrate, share a memory area.
  • the cavity arrangement and in particular the respective cavity or the respective cavities are at least partially formed laterally between the plurality of storage elements.
  • the respective cavity arrangement or the respective cavity is then used jointly by a plurality of memory cells. Sharing cavity and
  • Storage medium can also be combined with one another in order to achieve a particularly compact embodiment of the semiconductor memory device according to the invention.
  • Another aspect of the present invention is to provide a method for producing a semiconductor memory device having at least one memory element with a phase change memory effect.
  • the manufacturing method according to the invention is characterized in that a cavity arrangement with at least one cavity in spatial proximity to the respective memory element is provided for the at least one memory element in a semiconductor substrate such that the thermal coupling of the respective memory element to the environment of the memory element by reducing the thermal Conductivity between the memory element and the environment is reduced.
  • provision is made for a contact with the first or lower access electrode device, a second or upper access electrode device and an at least partially formed storage medium with phase-dependent ohmic resistance for the at least one memory element in the semiconductor substrate in contact with the access electrode devices it is provided that at least one of the access electrode devices, preferably the first or lower access electrode device, is provided and designed as an excitation electrode for locally heating the contacted storage medium and thus for initiating a corresponding phase conversion process or a corresponding phase conversion, and that at least part of the cavity arrangement and in particular at least a cavity in the spatial vicinity of the excitation electrode and / or the storage medium for thermal n Isolation from the environment is provided.
  • a cavity of the cavity arrangement is in each case assigned to the excitation electrode in an advantageous manner, such that the assigned cavity is directly adjacent to at least a part of the excitation electrode.
  • the associated cavity is designed to surround at least part of the excitation electrode.
  • the excitation electrode is designed as a connection region or plug region or as part thereof to form a source / drain region of an intended and assigned connection transistor, in particular a lateral selection transistor.
  • the excitation electrode is formed in a recess or in a trench structure in the semiconductor substrate.
  • the storage medium itself can be designed as a material area of the excitation electrode, in particular in an upper area of the respective trench structure.
  • a plurality and in particular two storage elements are provided and if the plurality of storage elements are formed with a common storage area.
  • the cavity arrangement and in particular the respective cavities at least partially laterally between the plurality of memory elements or memory cells are formed.
  • a common further or second access electrode device is formed for the plurality of memory cells or memory elements.
  • individual additional or second access electrode devices for the plurality of memory elements or memory cells are also conceivable.
  • the cavity arrangement and in particular the respective cavities are lined with a thin layer of SiO 2 or BPSG.
  • phase change memories For future non-volatile memories, a number of concepts such as ferroelectric memories, magnetoresistive memories, but also phase change memories are discussed.
  • phase change memories With phase change memories, the information is presented as a crystalline or amorphous state of a glass-like material.
  • the phase change takes place in that the material is heated by a suitable electrical pulse.
  • Chalcogenides Ge x Sb y _ Te z , InSbTe, AglnSbTe and the like are used as preferred materials.
  • the most frequently discussed material Ge 2 Sb 2 Te 5 requires, for example, about 310 ° C for crystallization and about 600 ° C for melting and thus for the transfer of the material from the crystalline to the amorphous phase.
  • One problem is that even if the material is heated to 600 ° C, an adjacent cell must not become so hot that it changes its state. This problem limits the scalability and integration density of phase change memories today.
  • the limit of the scalability and integration density of phase change memories occurs due to the influence of a neighboring bit when erasing with minimum structure sizes of approximately 70 nm. With the minimum structure sizes of 180 nm or 130 nm currently under discussion, conventional integration paths could still be followed. Insulation materials with a far lower thermal conductivity than the previously used silicon dioxide are currently being discussed for the 70nm generation and beyond.
  • Silicon dioxide has a thermal conductivity of 0.014 W / cm K.
  • the preferred material class for phase change materials is 0.003 - 0.18W / cm K.
  • the currently preferred material composition Ge 2 Sb 2 Te 5 is 0.0046 W / cm K, so that in this case a large part of the heat is dissipated via the insulation material.
  • An improvement would result, for example, from the use of polyimide with a thermal conductivity of 0.0016 W / cm K. However, this cannot be easily integrated into a CMOS process flow at the required point.
  • the invention solves this problem in that the individual cells are separated from one another by cavities. As a result, the thermal conductivity between the cells becomes minimal.
  • One inventive idea is to separate the individual cells indirectly or directly from the surroundings or from one another by means of cavities, both structurally and by means of a suitable process control.
  • a suitable sacrificial layer is removed around the heating element. This means that the heater or the excitation electrode is thermally isolated from the environment.
  • the actively switched area is additionally isolated from the surroundings by being introduced into the opening for the heating electrode.
  • the heating elements are encapsulated in etch stop layers, and then the insulation material between the structures is removed. Again, it is possible to integrate the phase change material itself into the recess for the heating element.
  • An additional embodiment of the first variant provides that the sacrificial layer or the spacer is applied again and structured lithographically in such a way that they protrude significantly beyond the contact hole. In this way, before the metallization is applied, an opening can be etched up to the sacrificial layer and this can be selectively removed from the surroundings by wet chemical means. As a result, the structure is isolated downwards in the immediate vicinity.
  • a further variant based on all of the structures mentioned hitherto, consists in between the cavity and the heating electrode material or heating electrode material and chalcogen. nide another very thin layer (for example: 5-10 nm; for example: Si0 2 ) by the known spacer technique. This prevents the same from being attacked by the etching during the etching of the sacrificial layer and the heating electrode material.
  • 1-15 show a schematic and sectional side view of intermediate states which are achieved in one embodiment of the production method according to the invention.
  • Figs. 16-32 show in schematic and sectioned side views intermediate states that in another
  • Embodiment of the manufacturing method according to the invention can be achieved.
  • 33-35 show a schematic and sectioned side view of three further embodiments of the semiconductor memory device according to the invention. Structurally or functionally similar or the same elements or material areas are referred to below with the same reference numerals, without a detailed discussion of their properties being repeated each time the description or the figures appear.
  • FIG. 1 shows a schematic and sectional side view of a semiconductor substrate 20 with a first material region 21 and a second material region 22, the latter having electrically insulating properties.
  • a CMOS structure is formed in this semiconductor material region 20, which has, for example, selection transistors T1 and T2, which in turn have first source / drain regions SD11 or SD21, second source / drain regions SD12 or SD22 and gate regions Gl and G2.
  • trenches or trench structures 32 are formed in a standard manner above the adjacent source / drain regions SD12 and SD21 of the first and second selection transistors T1 and T2. These can also be called contact holes.
  • spacers 32f are formed in the trench structures 32, so that wall regions of the trench structure 32 are covered, but at least some of the bottom regions of the trench structures 32 remain free. As a result, the free diameter of the trench structure 32 is narrowed.
  • These spacers 32f are produced by conformal deposition of a material region, for example a dielectric or an insulation material - here in the form of a sacrificial layer which can be etched selectively with respect to the electrode material which will be deposited later - and closing etching back the 'laterally extending material portions, so that only the vertical areas of material in the form of the spacers 32f remain in the grave structure 32nd
  • a layer 24 of a suitable electrode material is deposited.
  • the lateral region of the material layer 24 is removed by means of CMP with a stop at the level of the first, lower or bottom electrodes 14-1, 14-2.
  • the spacer material 32f is selectively removed from the trench structures 32, so that only the first, lower or bottom electrodes 14-1 and 14-2 remain in the trench structures 32 in a columnar manner.
  • a material layer 25 is then deposited, the material of which has a very poor edge coverage.
  • the trench structures 32 with the first electrodes 14-1 and 14-2 located therein are not completely filled in, in such a way that cavities H1 and H2 remain which form the so-called cavity structure H in the sense of the invention.
  • the cavities Hl, H2 can be closed by deposition and subsequent flowing of a BPSG layer.
  • This variant has the advantage that the inner walls of the cavities Hl, H2 are then lined with BPSG.
  • CMP with stop at the top level of the first access electrode devices 14-1 and 14-2 removes planarized under the lateral portion of the material layer 25, so that only plug elements 15-1 and 15-2 are left remain above the cavities Hl and H2.
  • a layer 26 of phase change material is then deposited, as shown in the state of FIG. 9.
  • an embodiment of the semiconductor memory device according to the invention is completed by first structuring the phase conversion material 26 and using a second or upper one
  • Access electrode device 18 is covered.
  • so-called contacting or plug areas P1 and P2 are formed to the outer source / drain areas SD11 and SD22.
  • the entire structure is embedded in an insulation region 23 and covered with a metallization layer W for contacting the plug regions P1 and P2.
  • the storage elements E are formed by the two access electrode devices 14 and 18, here the lower electrodes 14 forming the excitation or heating electrode, and the area 16 of the phase change material provided between them.
  • the memory cells 10 can then be seen with the aid of the access transistors T1, T2 for the respective memory element E.
  • Another variant of the manufacturing method according to the invention is based on the structure shown in FIG. 5 and, in the transition to the intermediate state shown in FIG. 11, carries out an etching back process on the first or lower one Access electrode devices 14-1 and 14-2 to obtain reduced first or lower access electrode devices 14-1 'and 14-2'.
  • the phase change material is then deposited in the form of a layer 26.
  • planarization is then carried out using a CMP method, so that the lateral layer regions of the layer 26 are removed from the surface of the substrate region 22.
  • the spacer elements 32f are then selectively etched out, as a result of which the cavities H1 and H2, which are the first or lower access electrode devices 14-1 'and 14-2' and the storage media 16-1 and 16-2 quasi surround and form the cavity arrangement H in the sense of the invention.
  • the counter electrode is formed in the form of the second or upper access electrode device 18, which is a common access electrode for the two memory elements E shown.
  • FIG. 16 Another variant of the manufacturing method according to the invention begins with an arrangement which corresponds to the arrangement corresponds to FIG. 1 and which is shown again in FIG. 16.
  • a comparatively wide recess or trench structure 32 is then formed and subsequently with a thin etching stop layer 32f, e.g. B. made of silicon nitride or the like.
  • the etching stop layer 32f is then etched back, so that lateral regions are removed therefrom and only the spacers 32f remain on the side walls of the trench structure 32.
  • a suitable electrode material is then deposited in the form of a layer 26.
  • the layer 26 of the electrode material is then also etched back, so that, in addition to the spacers 32f, the columns of the first or lower ones
  • Access electrode devices 14-1 and 14-2 remain.
  • a further etching stop layer is then optionally deposited and etched back, so that inner spacer elements 32f are formed in each case, which further narrow the trench structure 32.
  • the remaining trench structure 32 is then covered with an insulation layer 22z, for. B. made of oxide or BPSG, if necessary, using a planarization process using CMP. 22, the insulation layers 22 and 22z are then etched back to reduced or reduced insulation layers 22 ', so that the first or lower access electrode devices 14-1 and 14-2 as well as the etching stop layers in the form of the spacers 32f from the surface of the protrude reduced insulation layer 22 '.
  • an insulation layer 22z for. B. made of oxide or BPSG, if necessary, using a planarization process using CMP. 22
  • the insulation layers 22 and 22z are then etched back to reduced or reduced insulation layers 22 ', so that the first or lower access electrode devices 14-1 and 14-2 as well as the etching stop layers in the form of the spacers 32f from the surface of the protrude reduced insulation layer 22 '.
  • a further etching stop layer 27 is then formed, for example B. of silicon nitride or the like, which covers and embeds the first or lower access electrode devices 14-1 and 14-2 and the spacers 32f.
  • planarization is then carried out by means of CMP, specifically with a stop at the level of the first or lower access electrode devices 14-1 and 14-2.
  • the etching stop layer 27 is then opened between two cells, as is indicated by the recess 42 in FIG. 25 in the section of the line B-B 'of FIG. 26, namely the top view.
  • the insulation material of the region 22z is first removed selectively to the etching stop layer through the opening hole 42 by etching, as a result of which a cavity H between the two lower or first access electrode devices 14-1 and 14-2 arises.
  • An insulation layer with poor edge coverage is then deposited in order to close the opening hole 42 and thus the cavity H by means of a plug 42p.
  • the cavities Hl, H2 can be closed by deposition and subsequent flowing of a BPSG layer. This variant has the advantage that the inner walls of the cavities Hl, H2 are then lined with BPSG.
  • a layer 26 of the phase change material is then deposited again.
  • the 28 then follows the structuring of the storage material 16 from the material layer 26 of the phase change material, the covering and structuring with the common second or upper access electrode device 18, the embedding in an insulation area 23, the formation of the plugs Pl and P2 for contacting the outer source / drain regions SD11 and SD22, the selection transistors T1 and T2, and connecting the plug regions P1 and P2 by means of a metallization region W.
  • etching back of the formed first or lower access electrode devices 14-1 and 14-2 is carried out in order to reduce or reduce first or lower access electrode devices 14-1 'and 14 -2 'as shown in Fig. 29.
  • phase change material is then in turn deposited and removed by means of a CMP process, so that only material areas 16-1 and 16-2 individually for the first or lower access electrode devices 14-1 and 14-2 within the etched-back areas of these electrodes 14-1 and 14-2 remain.
  • the common second or upper access electrode device 18 is then formed.
  • the usual completion takes place by embedding in an insulation region 23, forming the plug regions P1 and P2 for connecting the outer source / drain regions SD11 and SD22 of the adjacent selection transistors T1, T2 and also contacting or connecting the plug areas P1 and P2 by means of a metallization layer W.
  • the memory cells 10 are essentially defined by the access or selection transistors T1 and T2.
  • the cells 10 are initially essentially thermally insulated from one another by the cavity H formed.
  • a thermal insulator 40 is also provided between the phase conversion material 16 and the second or upper access electrode device 18, which is made of BPSG or polyimide, for example.
  • the second or upper access electrode device 18 is drawn around the phase change material 16.
  • thermo insulator 40 between the phase change material 16 and the second or upper access electrode device 18 provided, but contacting of the second or upper access electrode device 18 with the phase change material 16 is realized in the middle through a contact hole.
  • access takes place at the edges of the layer structure made of storage medium 16 or phase change material 16, thermal insulator 40 and second or upper access electrode device 18.
  • the first semiconductor material substrate region 21 of the semiconductor substrate 20 can consist of p-silicon, for example. Accordingly, the source / drain regions SD11, SD12, SD21, SD22 can then consist of n + silicon.
  • the conductivity types or line types can also be exchanged.
  • the gates Gl and G2 can be made of polysilicon, polycide, salicide or of a suitable material. Silicon dioxide, silicon oxynitride, BPSG or the like can be used as insulation materials, in particular for regions 22 and 23. Etching stop materials for the spacers 32f can be formed, for example, from silicon nitride, aluminum oxide or the like.
  • the material for the first or lower access electrode devices 14, 14-1, 14-2, 14-1 ', 14-2' may be used: tantalum nitride, tantalum silicon nitride, titanium nitride, Titanium aluminum nitride, titanium silicon nitride, carbon, molybdenum, tungsten, titanium tungsten and the like.
  • the material of the counter electrode, that is to say the second or upper access electrode devices 18, can be aluminum, copper, tungsten, silicide or the like.
  • the plugs Pl and P2 can consist of tungsten, polysilicon, copper or aluminum.
  • the metallizations for the conductor tracks W can, for example, consist of aluminum and copper.
  • the thermal insulator 40 may be made of, for example, BPSG, polyimide, or the like.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un mémoire à semi-conducteur (1) à effet de mémorisation par conversion de phase, ainsi qu'un procédé de production d'une telle mémoire. Selon ledit procédé, chaque élément de mémoire (E) d'un substrat de semi-conducteur (20) présente un ensemble de cavités (H) dont au moins une cavité (H1, H2) est spatialement proche de l'élément de mémoire (E) correspondant, de telle sorte que le couplage thermique dudit élément de mémoire (E) correspondant avec son environnement est réduit grâce à la réduction de la conductivité thermique entre cet élément de mémoire (E) et son environnement.
EP03788820A 2002-11-26 2003-11-24 Memoire a semi-conducteur et son procede de production Withdrawn EP1565949A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10255117 2002-11-26
DE10255117A DE10255117A1 (de) 2002-11-26 2002-11-26 Halbleiterspeichereinrichtung sowie Verfahren zu deren Herstellung
PCT/DE2003/003885 WO2004049440A2 (fr) 2002-11-26 2003-11-24 Memoire a semi-conducteur et son procede de production

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EP1565949A2 true EP1565949A2 (fr) 2005-08-24

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EP03788820A Withdrawn EP1565949A2 (fr) 2002-11-26 2003-11-24 Memoire a semi-conducteur et son procede de production

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US (1) US20050270826A1 (fr)
EP (1) EP1565949A2 (fr)
AU (1) AU2003292985A1 (fr)
DE (2) DE10255117A1 (fr)
WO (1) WO2004049440A2 (fr)

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US7515454B2 (en) * 2006-08-02 2009-04-07 Infineon Technologies Ag CBRAM cell and CBRAM array, and method of operating thereof
US8138028B2 (en) * 2007-02-12 2012-03-20 Macronix International Co., Ltd Method for manufacturing a phase change memory device with pillar bottom electrode
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WO2004049440A2 (fr) 2004-06-10
WO2004049440A3 (fr) 2004-10-07
AU2003292985A1 (en) 2004-06-18
DE10255117A1 (de) 2004-06-17
US20050270826A1 (en) 2005-12-08
DE10394112D2 (de) 2005-10-20

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