Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
  • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
  • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F9/00—Arrangements for program control, e.g. control units
  • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
  • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
  • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F15/00—Digital computers in general; Data processing equipment in general
  • G06F15/76—Architectures of general purpose stored program computers
  • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit

Definitions

• a common computing architecture for processing relatively large amounts of data in a relatively short period of time includes multiple interconnected processors that share the processing burden. By sharing the processing burden, these multiple processors can often process the data more quickly than a single processor can for a given clock frequency. For example, each of the processors can process a respective portion of the data or execute a respective portion of a processing algorithm.
• FIG. 1 is a schematic block diagram of a conventional computing machine 10 having a multi-processor architecture.
• the machine 10 includes a master processor 12 and coprocessors 14 ⁇ - 14 n , which communicate with each other and the master processor via a bus 16, an input port 18 for receiving raw data from a remote device (not shown in FIG. 1), and an output port 20 for providing processed data to the remote source.
• the machine 10 also includes a memory 22 for the master processor 12, respective memories 24* / - 24 n for the coprocessors 14 ⁇ - 14 n , and a memory 26 that the master processor and coprocessors share via the bus 16.
• the memory 22 serves as both a program and a working memory for the master processor 12, and each memory 24 ⁇ - 24 tone serves as both a program and a working memory for a respective coprocessor 14 ⁇ - 14 nom.
• the shared memory 26 allows the master processor 12 and the coprocessors 14 to transfer data among themselves, and from/to the remote device via the ports 18 and 20, respectively.
• the master processor 12 and the coprocessors 14 also receive a common clock signal that controls the speed at which the machine 10 processes the raw data.
• the computing machine 10 effectively divides the processing of raw data among the master processor 12 and the coprocessors 14.
• the remote source such as a sonar array loads the raw data via the port 18 into a section of the shared memory 26, which acts as a first-in-first-out (FIFO) buffer (not shown) for the raw data.
• the master processor 12 retrieves the raw data from the memory 26 via the bus 16, and then the master processor and the coprocessors 14 process the raw data, transferring data among themselves as necessary via the bus 16.
• the master processor 12 loads the processed data into another FIFO buffer (not shown) defined in the shared memory 26, and the remote source retrieves the processed data from this FIFO via the port 20.
• the computing machine 10 processes the raw data by sequentially performing n + 1 respective operations on the raw data, where these operations together compose a processing algorithm such as a Fast Fourier Transform (FFT). More specifically, the machine 10 forms a data-processing pipeline from the master processor 12 and the coprocessors 14. For a given frequency of the clock signal, such a pipeline often allows the machine 10 to process the raw data faster than a machine having only a single processor.
• FFT Fast Fourier Transform
• the master processor 12 After retrieving the raw data from the raw-data FIFO (not shown) in the memory 26, the master processor 12 performs a first operation, such as a trigonometric function, on the raw data. This operation yields a first result, which the processor 12 stores in a first-result FIFO (not shown) defined within the memory 26.
• the processor 12 executes a program stored in the memory 22, and performs the above-described actions under the control of the program.
• the processor 12 may also use the memory 22 as working memory to temporarily store data that the processor generates at intermediate intervals of the first operation.
• the coprocessor 14 ⁇ performs a second operation, such as a logarithmic function, on the first result. This second operation yields a second result, which the coprocessor 14 ⁇ stores in a second-result FIFO (not shown) defined within the memory 26.
• the coprocessor 14 ⁇ executes a program stored in the memory 24 ⁇ , and performs the above-described actions under the control of the program.
• the coprocessor 14 ⁇ may also use the memory 24 ⁇ as working memory to temporarily store data that the coprocessor generates at intermediate intervals of the second operation.
• the coprocessors 24 2 - 24 n sequentially perform third - n th operations on the second - (n-1) th results in a manner similar to that discussed above for the coprocessor 24 ⁇ .
• the n th operation which is performed by the coprocessor 24 n , yields the final result, i.e., the processed data.
• the coprocessor 24 registers the processed data into a processed-data FIFO (not shown) defined within the memory 26, and the remote device (not shown in FIG. 1) retrieves the processed data from this FIFO.
• the computing machine 10 is often able to process the raw data faster than a computing machine having a single processor that sequentially performs the different operations.
• the single processor cannot retrieve a new set of the raw data until it performs all n + 1 operations on the previous set of raw data.
• the master processor 12 can retrieve a new set of raw data after performing only the first operation. Consequently, for a given clock frequency, this pipeline technique can increase the speed at which the machine 10 processes the raw data by a factor of approximately n + 1 as compared to a single-processor machine (not shown in FIG. 1).
• the computing machine 10 may process the raw data in parallel by simultaneously performing n + 1 instances of a processing algorithm, such as an FFT, on the raw data. That is, if the algorithm includes n + 1 sequential operations as described above in the previous example, then each of the master processor 12 and the coprocessors 14 sequentially perform all n + 1 operations on respective sets of the raw data. Consequently, for a given clock frequency, this parallel-processing technique, like the above-described pipeline technique, can increase the speed at which the machine 10 processes the raw data by a factor of approximately n + 1 as compared to a single-processor machine (not shown in FIG.
• a processing algorithm such as an FFT
• the computing machine 10 can process data more quickly than a single-processor computer machine (not shown in FIG. 1 ), the data-processing speed of the machine 10 is often significantly less than the frequency of the processor clock. Specifically, the data-processing speed of the computing machine 10 is limited by the time that the master processor 12 and coprocessors 14 require to process data. For brevity, an example of this speed limitation is discussed in conjunction with the master processor 12, although it is understood that this discussion also applies to the coprocessors 14. As discussed above, the master processor 12 executes a program that controls the processor to manipulate data in a desired manner. This program includes a sequence of instructions that the processor 12 executes.
• the processor 12 typically requires multiple clock cycles to execute a single instruction, and often must execute multiple instructions to process a single value of data. For example, suppose that the processor 12 is to multiply a first data value A (not shown) by a second data value B (not shown). During a first clock cycle, the processor 12 retrieves a multiply instruction from the memory 22. During second and third clock cycles, the processor 12 respectively retrieves A and B from the memory 26. During a fourth clock cycle, the processor 12 multiplies A and B, and, during a fifth clock cycle, stores the resulting product in the memory 22 or 26 or provides the resulting product to the remote device (not shown). This is a best-case scenario, because in many cases the processor 12 requires additional clock cycles for overhead tasks such as initializing and closing counters.
• Gops Gigaoperations/second
• FIG. 2 is a block diagram of a hardwired data pipeline 30 that can typically process data faster than a processor can for a given clock frequency, and often at substantially the same rate at which the pipeline is clocked.
• the pipeline 30 includes operator circuits 32 ⁇ - 32 n that each perform a respective operation on respective data without executing program instructions. That is, the desired operation is "burned in" to a circuit 32 such that it implements the operation automatically, without the need of program instructions.
• the pipeline 30 can typically perform more operations per second than a processor can for a given clock frequency.
• the pipeline 30 can often solve the following equation faster than a processor can for a given clock frequency:
• Y(x k ) (5x k + 3)2 xk
• x k represents a sequence of raw data values.
• the operator circuit 32 ⁇ is a multiplier that calculates 5X k
• the circuit 32 2 is an adder that calculates 5X k + 3
• the circuit 32 ⁇ receives data value x-t and multiplies it by 5 to generate 5x ⁇ .
• the pipeline 30 continues processing subsequent raw data values x in this manner until all the raw data values are processed. [21] Consequently, a delay of two clock cycles after receiving a raw data value x-t — this delay is often called the latency of the pipeline 30 — the pipeline generates the result (5x* ⁇ + 3)2 x1 , and thereafter generates one result — e.g., (5x 2 + 3)2 x2 , (5x 3 + 3)2 x3 , . . ., 5x impart + 3)2 xn — each clock cycle.
• the pipeline 30 thus has a data-processing speed equal to the clock speed.
• the master processor 12 and coprocessors 14 (FIG. 1) have data-processing speeds that are 0.4 times the clock speed as in the above example, the pipeline 30 can process data 2.5 times faster than the computing machine 10 (FIG. 1) for a given clock speed.
• a designer may choose to implement the pipeline 30 in a programmable logic IC (PLIC), such as a field-programmable gate array (FPGA), because a PLIC allows more design and modification flexibility than does an application specific IC (ASIC).
• PLIC programmable logic IC
• FPGA field-programmable gate array
• ASIC application specific IC
• the designer merely sets interconnection-configuration registers disposed within the PLIC to predetermined binary states. The combination of all these binary states is often called “firmware.”
• the designer loads this firmware into a nonvolatile memory (not shown in FIG. 2) that is coupled to the PLIC. When one "turns on” the PLIC, it downloads the firmware from the memory into the interconnection-configuration registers.
• the designer merely modifies the firmware and allows the PLIC to download the modified firmware into the interconnection-configuration registers.
• This ability to modify the PLIC by merely modifying the firmware is particularly useful during the prototyping stage and for upgrading the pipeline 30 "in the field".
• the hardwired pipeline 30 typically cannot execute all algorithms, particularly those that entail significant decision making.
• a processor can typically execute a decision-making instruction (e.g., conditional instructions such as "if A, then go to B, else go to C") approximately as fast as it can execute an operational instruction (e.g., "A + B") of comparable length.
• the pipeline 30 may be able to make a relatively simple decision (e.g., "A > B?"), it typically cannot execute a relatively complex decision (e.g., "if A, then go to B, else go to C”).
• the size and complexity of the required circuitry often makes such a design impractical, particularly where an algorithm includes multiple different complex decisions.
• processors are typically used in applications that require significant decision making, and hardwired pipelines are typically limited to "number crunching" applications that entail little or no decision making.
• processors typically include industry-standard communication interfaces that facilitate the interconnection of the components to form a processor-based computing machine.
• a standard communication interface typically includes two layers: a physical layer and a service layer.
• the physical layer includes the circuitry and the corresponding circuit interconnections that form the interface and the operating parameters of this circuitry.
• the physical layer includes the pins that connect the component to a bus, the buffers that latch data received from the pins, and the drivers that drive data onto the pins.
• the operating parameters include the acceptable voltage range of the data signals that the pins receive, the signal timing for writing and reading data, and the supported modes of operation (e.g., burst mode, page mode).
• Conventional physical layers include transistor-transistor logic (TTL) and RAMBUS.
• TTL transistor-transistor logic
• RAMBUS RAMBUS.
• the service layer includes the protocol by which a computing component transfers data. The protocol defines the format of the data and the manner in which the component sends and receives the formatted data.
• Conventional communication protocols include file-transfer protocol (FTP) and TCP/IP (expand).
• a computing machine includes a first buffer and a processor coupled to the buffer.
• the processor is operable to execute an application, a first data-transfer object, and a second data-transfer object, publish data under the control of the application, load the published data into the buffer under the control of the first data-transfer object, and retrieve the published data from the buffer under the control of the second data-transfer object.
• the processor is operable to retrieve data and load the retrieved data into the buffer under the control of the first data-transfer object, unload the data from the buffer under the control of the second data-transfer object, and process the unloaded data under the control of the application.
• the computing machine is a peer-vector machine that includes a hardwired pipeline accelerator coupled to the processor
• the buffer and data-transfer objects facilitate the transfer of data — whether unidirectional or bidirectional — between the application and the accelerator.
• FIG. 1 is a block diagram of a computing machine having a conventional multi-processor architecture.
• FIG. 2 is a block diagram of a conventional hardwired pipeline.
• FIG. 3 is schematic block diagram of a computing machine having a peer-vector architecture according to an embodiment of the invention.
• FIG. 4 is a functional block diagram of the host processor of FIG. 3 according to an embodiment of the invention.
• FIG. 5 is a functional block diagram of the data-transfer paths between the data-processing application and the pipeline bus of FIG. 4 according to an embodiment of the invention.
• FIG. 6 is a functional block diagram of the data-transfer paths between the accelerator exception manager and the pipeline bus of FIG. 4 according to an embodiment of the invention.
• FIG. 7 is a functional block diagram of the data-transfer paths between the accelerator configuration manager and the pipeline bus of FIG. 4 according to an embodiment of the invention.
• FIG. 3 is a schematic block diagram of a computing machine 40, which has a peer-vector architecture according to an embodiment of the invention.
• the peer-vector machine 40 includes a pipeline accelerator 44, which performs at least a portion of the data processing, and which thus effectively replaces the bank of coprocessors 14 in the computing machine 10 of FIG. 1. Therefore, the host-processor 42 and the accelerator 44 are "peers" that can transfer data vectors back and forth. Because the accelerator 44 does not execute program instructions, it typically performs mathematically intensive operations on data significantly faster than a bank of coprocessors can for a given clock frequency.
• the machine 40 has the same abilities as, but can often process data faster than, a conventional computing machine such as the machine 10.
• a conventional computing machine such as the machine 10.
• providing the accelerator 44 with the same communication interface as the host processor 42 facilitates the design and modification of the machine 40, particularly where the communications interface is an industry standard.
• the accelerator 44 includes multiple components (e.g., PLICs), providing these components with this same communication interface facilitates the design and modification of the accelerator, particularly where the communication interface is an industry standard.
• the machine 40 may also provide other advantages as described below and in the previously cited patent applications.
• the peer-vector computing machine 40 includes a processor memory 46, an interface memory 48, a bus 50, a firmware memory 52, optional raw ( - data input ports 54 and 56, processed-data output ports 58 and 60, and an optional router 61.
• the host processor 42 includes a processing unit 62 and a message handler 64
• the processor memory 46 includes a processing-unit memory 66 and a handler memory 68, which respectively serve as both program and working memories for the processor unit and the message handler.
• the processor memory 46 also includes an accelerator-configuration registry 70 and a message-configuration registry 72, which store respective configuration data that allow the host processor 42 to configure the functioning of the accelerator 44 and the structure of the messages that the message handler 64 sends and receives.
• the pipeline accelerator 44 is disposed on at least one PLIC (not shown) and includes hardwired pipelines 74 ⁇ - 74 n , which process respective data without executing program instructions.
• the firmware memory 52 stores the configuration firmware for the accelerator 44. If the accelerator 44 is disposed on multiple PLICs, these PLICs and their respective firmware memories may be disposed on multiple circuit boards, i.e., daughter cards (not shown). The accelerator 44 and daughter cards are discussed further in previously cited U.S. Patent App. Serial Nos.
• the accelerator 44 may be disposed on at least one ASIC, and thus may have internal interconnections that are unconfigurable. In this alternative, the machine 40 may omit the firmware memory 52. Furthermore, although the accelerator 44 is shown including multiple pipelines 74, it may include only a single pipeline. In addition, although not shown, the accelerator 44 may include one or more processors such as a digital-signal processor (DSP).
• DSP digital-signal processor
• FIG. 4 is a functional block diagram of the host processor 42 and the pipeline bus 50 of FIG. 3 according to an embodiment of the invention.
• the processing unit 62 executes one or more software applications
• the message handler 64 executes one or more software objects that transfer data between the software application(s) and the pipeline accelerator 44 (FIG. 3).
• splitting the data-processing, data-transferring, and other functions among different applications and objects allows for easier design and modification of the host-processor software.
• a software application is described as performing a particular operation, it is understood that in actual operation, the processing unit 62 or message handler 64 executes the software application and performs this operation under the control of the application.
• a software object is described as performing a particular operation, it is understood that in actual operation, the processing unit 62 or message handler 64 executes the software object and performs this operation under the control of the object.
• the processing unit 62 executes a data-processing application 80, an accelerator exception manager application (hereinafter the exception manager) 82, and an accelerator configuration manager application (hereinafter the configuration manager) 84, which are collectively referred to as the processing-unit applications.
• the data-processing application processes data in cooperation with the pipeline accelerator 44 (FIG. 3).
• the data- processing application 80 may receive raw sonar data via the port 54 (FIG. 3), parse the data, and send the parsed data to the accelerator 44, and the accelerator may perform an FFT on the parsed data and return the processed data to the data- processing application for further processing.
• the exception manager 82 handles exception messages from the accelerator 44, and the configuration manager 84 loads the accelerator's configuration firmware into the memory 52 during initialization of the peer-vector machine 40 (FIG. 3).
• the configuration manager 84 may also reconfigure the accelerator 44 after initialization in response to, e.g., a malfunction of the accelerator.
• the processing-unit applications may communicate with each other directly as indicated by the dashed lines 85, 87, and 89, or may communicate with each other via the data-transfer objects 86.
• the message handler 64 executes the data-transfer objects 86, a communication object 88, and input and output read objects 90 and 92, and may execute input and output queue objects 94 and 96.
• the data-transfer objects 86 transfer data between the communication object 88 and the processing-unit applications, and may use the interface memory 48 as a data buffer to allow the processing-unit applications and the accelerator 44 to operate independently.
• the memory 48 allows the accelerator 44, which is often faster than the data-processing application 80, to operate without "waiting" for the data-processing application.
• the communication object 88 transfers data between the data objects 86 and the pipeline bus 50.
• the input and output read objects 90 and 92 control the data-transfer objects 86 as they transfer data between the communication object 88 and the processing-unit applications. And, when executed, the input and output queue objects 94 and 96 cause the input and output read objects 90 and 92 to synchronize this transfer of data according to a desired priority
• the message handler 64 instantiates and executes a conventional object factory 98, which instantiates the data-transfer objects 86 from configuration data stored in the message-configuration registry 72 (FIG. 3).
• the message handler 64 also instantiates the communication object 88, the input and output reader objects 90 and 92, and the input and output queue objects 94 and 96 from the configuration data stored in the message-configuration registry 72. Consequently, one can design and modify these software objects, and thus their data-transfer parameters, by merely designing or modifying the configuration data stored in the registry 72. This is typically less time consuming than designing or modifying each software object individually.
• FIG. 5 is a functional block diagram of the data-processing application
• the data-processing application 80 includes a number of threads 100 ⁇
• the thread 100 ⁇ may perform an addition
• the thread 100 2 may perform a subtraction, or both the threads 100 ⁇ and 100 2 may perform an addition.
• Each thread 100 generates, i.e., publishes, data destined for the pipeline accelerator 44 (FIG. 3), receives, i.e., subscribes to, data from the accelerator, or both publishes and subscribes to data. For example, each of the threads 100 ⁇ - IOO 4 both publish and subscribe to data from the accelerator 44.
• a thread 100 may also communicate directly with another thread 100. For example, as indicated by the dashed line 102, the threads IOO3 and WO4 may directly communicate with each other.
• a thread 100 may receive data from or send data to a component (not shown) other than the accelerator 44 (FIG. 3). But for brevity, discussion of data transfer between the threads 100 and such another component is omitted.
• the interface memory 48 and the data-transfer objects 86 ⁇ a - 86 nb functionally form a number of unidirectional channels 104 ⁇ - 104 immunity for transferring data between the respective threads 100 and the communication object 88.
• the interface memory 48 includes a number of buffers IO6 1 - 106 radical, one buffer per channel 104.
• the buffers 106 may each hold a single grouping (e.g., byte, word, block) of data, or at least some of the buffers may be FIFO buffers that can each store respective multiple groupings of data.
• the channel 104 ⁇ includes a buffer IO6 1 , a data-transfer object 86 ⁇ a for transferring published data from the thread 100 ⁇ to the buffer IO6 1 , and a data-transfer object 86 ⁇ b for transferring the published data from the buffer IO6 1 to the communication object 88.
• Including a respective channel 104 for each allowable data transfer reduces the potential for data bottlenecks and also facilitates the design and modification of the host processor 42 (FIG. 4).
• the object factory 98 instantiates the data-transfer objects 86 and defines the buffers 104. Specifically, the object factory 98 downloads the configuration data from the registry 72 and generates the software code for each data-transfer object 86 xb that the data-processing application 80 may need.
• the identity of the data-transfer objects 86 Xb that the application 80 may need is typically part of the configuration data — the application 80, however, need not use all of the data-transfer objects 86.
• the object factory 98 respectively instantiates the data objects 86 xa .
• the object factory 98 instantiates data-transfer objects 86 xa and 86 X b that access the same buffer 104 as multiple instances of the same software code. This reduces the amount of code that the object factory 98 would otherwise generate by approximately one half.
• the message handler 64 may determine which, if any, data-transfer objects 86 the application 80 does not need, and delete the instances of these unneeded data-transfer objects to save memory. Alternatively, the message handler 64 may make this determination before the object factory 98 generates the data-transfer objects 86, and cause the object factory to instantiate only the data-transfer objects that the application 80 needs. In addition, because the data-transfer objects 86 include the addresses of the interface memory 48 where the respective buffers 104 are located, the object factory 98 effectively defines the sizes and locations of the buffers when it instantiates the data-transfer objects.
• the object factory 98 instantiates the data-transfer objects 86 ⁇ a and 86ib in the following manner. First, the factory 98 downloads the configuration data from the registry 72 and generates the common software code for the data-transfer object 86 ⁇ a and 86 ⁇ b . Next, the factory 98 instantiates the data-transfer objects 86 and 86 ⁇ b as respective instances of the common software code. That is, the message handler 64 effectively copies the common software code to two locations of the handler memory 68 orto other program memory (not shown), and executes one location as the object 86 ⁇ a and the other location as the object 86 1b . [64] Still referring to FIGS. 3-5, after initialization of the host processor 42, the data-processing application 80 processes data and sends data to and receives data from the pipeline accelerator 44.
• the thread 100 ⁇ generates and publishes data to the data-transfer object 86 ⁇ a .
• the thread 100 ⁇ may generate the data by operating on raw data that it receives from the accelerator 44 (further discussed below) or from another source (not shown) such as a sonar array or a data base via the port 54.
• the data-object 86 ⁇ a loads the published data into the buffer
• the data-transfer object 86 1b determines that the buffer 106 ⁇ has been loaded with newly published data from the data-transfer object 86 ⁇ a .
• the output reader object 92 may periodically instruct the data-transfer object 86 ⁇ b to check the buffer 106 ⁇ for newly published data.
• the output reader object 92 notifies the data-transfer object 86i b when the buffer 106 ⁇ has received newly published data.
• the output queue object 96 generates and stores . a unique identifier (not shown) in response to the data-transfer object 86 ⁇ a storing the published data in the buffer 106 ⁇ .
• the output reader object 92 In response to this identifier, the output reader object 92 notifies the data-transfer object 86i b that the buffer 106 1 contains newly published data. Where multiple buffers 106 contain respective newly published data, then the output queue object 96 may record the order in which this data was published, and the output reader object 92 may notify the respective data-transfer objects 86 xb in the same order. Thus, the output reader object 92 and the output queue object 96 synchronize the data transfer by causing the first data published to be the first data that the respective data-transfer object 86 Xb sends to the accelerator 44, the second data published to be the second data that the respective data- transfer object 86 Xb sends to the accelerator, etc.
• the output reader and output queue objects 92 and 96 may implement a priority scheme other than, or in addition to, this first-in-first-out scheme. For example, suppose the thread 100 ⁇ publishes first data, and subsequently the thread 100 2 publishes second data but also publishes to the output queue object 96 a priority flag associated with the second data. Because the second data has priority over the first data, the output reader object 92 notifies the data-transfer object 86 2 b of the published second data in the buffer 106 2 before notifying the data-transfer object 86 1b of the published first data in the buffer 106 ⁇ .
• the data-transfer object 86i b retrieves the published data from the buffer 106 ⁇ and formats the data in a predetermined manner. For example, the object 86i b generates a message that includes the published data (i.e., the payload) and a header that, e.g., identifies the destination of the data within the accelerator 44. This message may have an industry-standard format such as the Rapid IO
• the data-transfer object 86i b formats the published data, it sends the formatted data to the communication object 88.
• the communication object 88 sends the formatted data to the pipeline accelerator 44 via the bus 50.
• the communication object 88 is designed to implement the communication protocol (e.g., Rapid IO, TCP/IP) used to transfer data between the host processor 42 and the accelerator 44.
• the communication object 88 implements the required hand shaking and other transfer parameters (e.g., arbitrating the sending and receiving of messages on the bus 50) that the protocol requires.
• the data-transfer object 86 Xb can implement the communication protocol, and the communication object 88 can be omitted.
• the pipeline accelerator 44 then receives the formatted data, recovers the data from the message (e.g., separates the data from the header if there is a header), directs the data to the proper destination within the accelerator, and processes the data.
• the pipeline accelerator 44 (FIG. 3) sending data to the host processor 42 (FIG. 3) is discussed in conjunction with the channel 104 2 .
• the pipeline accelerator 44 generates and formats data. For example, the accelerator 44 generates a message that includes the data payload and a header that, e.g., identifies the destination threads 100 ⁇ and 100 2 , which are the threads that are to receive and process the data. As discussed above, this message may have an industry-standard format such as the Rapid IO (input/output) format.
• the accelerator 44 drives the formatted data onto the bus 50 in a conventional manner.
• the communication object 88 receives the formatted data from the bus 50 and provides the formatted data to the data-transfer object 86 2b .
• the formatted data is in the form of a message
• the communication object 88 analyzes the message header (which, as discussed above, identifies the destination threads 100 ⁇ and 100 2 ) and provides the message to the data-transfer object 86 2b in response to the header.
• the communication object 88 provides the message to all of the data-transfer objects 86 foi b , each of which analyzes the message header and processes the message only if its function is to provide data to the destination threads 100 ⁇ and 7O0 2 . Consequently, in this example, only the data-transfer object 86 2b processes the message.
• the data-transfer object 86 2b loads the data received from the communication object 88 into the buffer 106 2 .
• the data-transfer object 86 2b recovers the data from the message (e.g., by stripping the header) and loads the recovered data into the buffer 106 2 .
• the data-transfer object 86 2a determines that the buffer 106 2 has received new data from the data-transfer object 86 2b .
• the input reader object 90 may periodically instruct the data-transfer object 86 2a to check the buffer 106 2 for newly received data. Alternatively, the input reader object 90 notifies the data-transfer object 86 2a when the buffer 106 2 has received newly published data.
• the input queue object 94 generates and stores a unique identifier (not shown) in response to the data-transfer object 86 2b storing the published data in the buffer 106 2 .
• the input reader object 90 notifies the data-transfer object 86 2a that the buffer 106 2 contains newly published data.
• the input queue object 94 may record the order in which this data was published, and the input reader object 90 may notify the respective data-transfer objects 86 xa in the same order.
• the input reader and input queue objects 90 and 94 may implement a priority scheme other than, or in addition to, this first-in-first-out scheme.
• the data-object 86 2a transfers the data from the buffer 106 2 to the subscriber threads 100 ⁇ and 100 2 , which perform respective operations on the data.
• the data-object 86 2a transfers the data from the buffer 106 2 to the subscriber threads 100 ⁇ and 100 2 , which perform respective operations on the data.
• FIG. 5 an example of one thread receiving and processing data from another thread is discussed in conjunction with the thread WO 4 receiving and processing data published by the thread IOO 3 .
• the thread WO 3 publishes the data directly to the thread WO 4 via the optional connection (dashed line) 7 * 02.
• the thread IOO 3 publishes the data to the thread OO 4 via the channels 104 5 and 104 ⁇ - Specifically, the data-transfer object 86 5a loads the published data into the buffer IO6 5 .
• the data-transfer object 86 5b retrieves the data from the buffer 106s and transfers the data to the communication object 88, which publishes the data to the data-transfer object 86 ⁇ b - Then, the data-transfer object 86 6 b loads the data into the buffer 106 ⁇ .
• the data-transfer object 86 6a transfers the data from the buffer 106 ⁇ to the thread IOO 4 .
• the data is not being transferred via the bus 50, then one may modify the data-transfer object 865 b such that it loads the data directly into the buffer 7 * 06 6 , thus bypassing the communication object 88 and the data-transfer object 86 ⁇ b - But modifying the data-transfer object 865 b to be different from the other data-transfer objects 86 may increase the complexity modularity of the message handler 64.
• a single thread may publish data to multiple locations within the pipeline accelerator 44 (FIG. 3) via respective multiple channels.
• a single thread may publish data to multiple locations within the pipeline accelerator 44 (FIG. 3) via respective multiple channels.
• a single thread may publish data to multiple locations within the pipeline accelerator 44 (FIG. 3) via respective multiple channels.
• the accelerator 44 may receive data via a single channel 104 and provide it to multiple locations within the accelerator. Furthermore, multiple threads (e.g., threads 100 ⁇ and 100 2 ) may subscribe to data from the same channel (e.g., channel 104 2 ).
• FIG. 6 is a functional block diagram of the exception manager 82, the data-transfer objects 86, and the interface memory 48 according to an embodiment of the invention.
• the exception manager 82 receives and logs exceptions that may occur during the initialization or operation of the pipeline accelerator 44 (FIG. 3).
• an exception is a designer-defined event where the accelerator 44 acts in an undesired manner.
• a buffer (not shown) that overflows may be an exception, and thus cause the accelerator 44 to generate an exception message and send it to the exception manager 82.
• Generation of an exception message is discussed in previously cited U.S. Patent App. Serial No. 10/683,929 entitled PIPELINE ACCELERATOR FOR IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD.
• the exception manager 82 may also handle exceptions that occur during the initialization or operation of the pipeline accelerator 44 (FIG. 3). For example, if the accelerator 44 includes a buffer (not shown) that overflows, then the exception manager 82 may cause the accelerator to increase the size of the buffer to prevent future overflow. Or, if a section of the accelerator 44 malfunctions, the exception manager 82 may cause another section of the accelerator or the data-processing application 80 to perform the operation that the malfunctioning section was intended to perform. Such exception handling is further discussed below and in previously cited U.S. Patent App. Serial No. 10/;683,929 entitled
• the exception manager 82 subscribes to data from one or more subscriber threads 100 (FIG. 5) and determines from this data whether an exception has occurred.
• the exception manager 82 subscribes to the same data as the subscriber threads 700 (FIG. 5) subscribe to. Specifically, the manager 82 receives this data via the same respective channels 104 s (which include, e.g., channel 104 2 of FIG. 5) from which the subscriber threads 100 (which include, e.g., threads 100 1 and 100 2 of FIG. 5) receive the data. Consequently, the channels 104 s provide this data to the exception manager 82 in the same manner that they provide this data to the subscriber threads 100.
• the exception manager 82 subscribes to data from dedicated channels 7 " 06 (not shown), which may receive data from sections of the accelerator 44 (FIG. 3) that do not provide data to the threads 100 via the subscriber channels 7O4 S .
• the object factory 98 (FIG. 4) generates the data-transfer objects 86 for these channels during initialization of the host processor 42 as discussed above in conjunction with FIG. 4.
• the exception manager 82 may subscribe to the dedicated channels 106 exclusively or in addition to the subscriber channels 704 s .
• the exception manager 82 analyzes the data to determine if an exception has occurred.
• the data may represent the result of an operation performed by the accelerator 44.
• the exception manager 82 determines whether the data contains an error, and, if so, determines that an exception has occurred and the identity of the exception.
• the exception manager 82 logs, e.g., the corresponding exception code and the time of occurrence, for later use such as during a debug of the accelerator 44.
• the exception manager 82 may also determine and convey the identity of the exception to, e.g., the system designer, in a conventional manner.
• the exception manager 82 may implement an appropriate procedure for handling the exception.
• the exception manager 82 may handle the exception by sending an exception-handling instruction to the accelerator 44, the data-processing application 80, or the configuration manager 84.
• the exception manager 82 may send the exception-handling instruction to the accelerator 44 either via the same respective channels 7 " 04 p (e.g., channel 104 ⁇ of FIG. 5) through which the publisher threads 700 (e.g., thread 700 ? of FIG. 5) publish data, or through dedicated exception-handling channels 104 (not shown) that operate as described above in conjunction with FIG. 5.
• the exception manager 82 sends instructions via other channels 7O4, then the object factory 98 (FIG.
• the exception manager 82 may publish exception-handling instructions to the data-processing application 80 and to the configuration manager 84 either directly (as indicated by the dashed lines 85 and 89 in FIG. 4) or via the channels 104 dpa1 and 104 dpa2 (application 80) and channels 104 cm ⁇ and 104 cm2 (configuration manager 84), which the object factory 98 also generates during the initialization of the host processor 42.
• the exception-handling instructions may cause the accelerator 44, data-processing application 80, or configuration manager 84 to handle the corresponding exception in a variety of ways.
• the exception-handling instruction may change the soft configuration or the functioning of the accelerator. For example, as discussed above, if the exception is a buffer overflow, the instruction may change the accelerator's soft configuration (i.e., by changing the contents of a soft configuration register) to increase the size of the buffer.
• the instruction may change the accelerator's functioning by causing the accelerator to take the disabled section "off line.”
• the exception manager 82 may, via additional instructions, cause another section of the accelerator 44, or the data-processing application 80, to "take over" the operation from the disabled accelerator section as discussed below. Altering the soft configuration of the accelerator 44 is further discussed in previously cited U.S. Patent App. Serial No. 10/683,929 entitled PIPELINE ACCELERATOR FOR IMPROVED COMPUTING ARCHITECTURE AND RELATED SYSTEM AND METHOD (Attorney Docket No. 1934-13-3).
• the exception-handling instructions may cause the data-processing application to "take over" the operation of a disabled section of the accelerator 44 that has been taken off line.
• the processing unit 62 (FIG. 3) may perform this operation more slowly and less efficiently than the accelerator 44, this may be preferable to not performing the operation at all. This ability to shift the performance of an operation from the accelerator 44 to the processing unit 62 increases the flexibility, reliability, maintainability, and fault-tolerance of the peer-vector machine 40 (FIG. 3).
• the exception-handling instruction may cause the configuration manager to change the hard configuration of the accelerator 44 so that the accelerator can continue to perform the operation of a malfunctioning section that has been taken off line. For example, if the accelerator 44 has an unused section, then the configuration manager 84 may configure this unused section to perform the operation that was to be the malfunctioning section. If the accelerator 44 has no unused section, then the configuration manager 84 may reconfigure a section of the accelerator that currently performs a first operation to perform a second operation of, i.e., take over for, the malfunctioning section.
• This technique may be useful where the first operation can be omitted but the second operation cannot, or where the data-processing application 80 is more suited to perform the first operation than it is the second operation.
• This ability to shift the performance of an operation from one section of the accelerator 44 to another section of the accelerator increases the flexibility, reliability, maintainability, and fault-tolerance of the peer-vector machine 40 (FIG. 3).
• the configuration manager 84 loads the firmware that defines the hard configuration of the accelerator 44 during initialization of the peer-vector machine 40 (FIG. 3), and, as discussed above in conjunction with FIG. 6, may load firmware that redefines the hard configuration of the accelerator in response to an exception according to an embodiment of the invention.
• the configuration manager 84 often reduces the complexity of designing and modifying the accelerator 44 and increases the fault-tolerance, reliability, maintainability, and flexibility of the peer-vector machine 40 (FIG. 3).
• the configuration manager 84 receives configuration data from the accelerator configuration registry 70, and loads configuration firmware identified by the configuration data.
• the configuration data are effectively instructions to the configuration manager 84 for loading the firmware. For example, if a section of the initialized accelerator 44 performs an FFT, then one designs the configuration data so that the firmware loaded by the manager 84 implements an FFT in this section of the accelerator. . Consequently, one can modify the hard configuration of the accelerator 44 by merely generating or modifying the configuration data before initialization of the peer-vector machine 40.
• the configuration manager 84 typically reduces the complexity of designing and modifying the accelerator 44.
• the configuration manager 84 determines whether the accelerator 44 can support the configuration defined by the configuration data. For example, if the configuration data instructs the configuration manager 84 to load firmware for a particular PLIC (not shown) of the accelerator 44, then the configuration manager 84 confirms that the PLIC is present before loading the data. If the PLIC is not present, then the configuration manager 84 halts the initialization of the accelerator 44 and notifies an operator that the accelerator does not support the configuration. [101] After the configuration manager 84 confirms that the accelerator supports the defined configuration, the configuration manager loads the firmware into the accelerator 44, which sets its hard configuration with the firmware, e.g., by loading the firmware into the firmware memory 52.
• the configuration manager 84 sends the firmware to the accelerator 44 via one or more channels 104 t that are similar in generation, structure, and operation to the channels 104 of FIG. 5.
• the configuration manager 84 may also receive data from the accelerator 44 via one or more channels 104 u .
• the accelerator 44 may send confirmation of the successful setting of its hard configuration to the configuration manager 84.
• the configuration manager 84 may set the accelerator's hard configuration in response to an exception-handling instruction from the exception manager 84 as discussed above in conjunction with FIG. 6.
• the configuration manager 84 downloads the appropriate configuration data from the registry 70, loads reconfiguration firmware identified by the configuration data, and sends the firmware to the accelerator 44 via the channels 704*.
• the configuration manager 84 may receive confirmation of successful reconfiguration from the accelerator 44 via the channels 104 u .
• the configuration manager 84 may receive the exception-handling instruction directly from the exception manager 82 via the line 89 (FIG. 4) or indirectly via the channels 104 cm ⁇ and 104 cm2 .
• the configuration manager 84 may also reconfigure the data-processing application 80 in response to an exception-handling instruction from the exception manager 84 as discussed above in conjunction with FIG. 6.
• the configuration manager 84 instructs the data-processing application 80 to reconfigure itself to perform an operation that, due to malfunction or other reason, the accelerator 44 cannot perform.
• the configuration manager 84 may so instruct the data-processing application 80 directly via the line 87 (FIG. 4) or indirectly via channels 104 dp ⁇ and 104 dp2 , and may receive information from the data-processing application, such as confirmation of successful reconfiguration, directly or via another channel 704 (not shown).
• the exception manager 82 may send an exception-handling instruction to the data-processing 80, which reconfigures itself, thus bypassing the configuration manager 82.
• the configuration manager 82 may reconfigure the accelerator 44 or the data-processing application 80 for reasons other than the occurrence of an accelerator malfunction.

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