EP1531489A2 - Plaquette, dispositif semi-conducteur et son procédé de fabrication - Google Patents

Plaquette, dispositif semi-conducteur et son procédé de fabrication Download PDF

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Publication number
EP1531489A2
EP1531489A2 EP04257009A EP04257009A EP1531489A2 EP 1531489 A2 EP1531489 A2 EP 1531489A2 EP 04257009 A EP04257009 A EP 04257009A EP 04257009 A EP04257009 A EP 04257009A EP 1531489 A2 EP1531489 A2 EP 1531489A2
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Prior art keywords
crystal silicon
silicon integrated
insulating substrate
integrated circuits
integrated circuit
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EP04257009A
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German (de)
English (en)
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EP1531489A3 (fr
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Arinobou Kanegae
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Sharp Corp
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Sharp Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L27/1266—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate the substrate on which the devices are formed not being the final device substrate, e.g. using a temporary substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to a wafer including single-crystal silicon integrated circuits, and a semiconductor device in which a single-crystal silicon integrated circuit cut out from the wafer is arranged on an insulating substrate.
  • the present invention further relates to methods for fabricating the wafer and the semiconductor.
  • An active matrix driving device has been widely used as a driving device for a liquid crystal display panel, an OLED (Organic Light Emitting Diode), or other displays.
  • the active matrix driving device adopts a semiconductor device in which thin film transistors (TFTs) made of amorphous silicon or polycrystalline silicon are arranged on a glass substrate.
  • TFTs thin film transistors
  • an active matrix driving device has adopted a semiconductor device in which a polycrystalline silicon integrated circuit is arranged on an insulating substrate such as a glass substrate.
  • a polycrystalline silicon integrated circuit In this polycrystalline silicon integrated circuit, peripheral drivers are integrated by using the polycrystalline silicon.
  • the high fineness of a display device such as the liquid crystal display panel calls for high-performance of the active matrix driving device to be used.
  • a Japanese translation of unexamined PCT publication No. 7-503557/ 1995 discloses a method for forming a single-crystal silicon integrated circuit on an insulating substrate such as a glass substrate.
  • an integrated circuit (a single-crystal silicon layer) is formed on a silicon substrate, prior to bonding the integrated circuit with the insulating substrate via an adhesive agent.
  • the adhesive agent is used for bonding the insulating substrate with the single-crystal silicon integrated circuit, which is preliminary formed
  • another method for forming the single-crystal integrated circuit on the insulating substrate there is another method for forming the single-crystal integrated circuit on the insulating substrate.
  • a silicon substrate is bonded with the insulating substrate, and then a thinning process is carried out to form an SOI (Silicon On Insulator) configuration.
  • SOI Silicon On Insulator
  • Examples of the semiconductor device utilizing the SOI configuration are disclosed in Japanese Patents No. 2743391 (issued on February 6, 1998), No. 3141486 (issued on December 22, 2000), and No. 3278944 (issued on February 22, 2002).
  • the Smart Cut method hydrogen ions having a predetermined concentration are implanted into a silicon substrate so as to have a predetermined implanted depth.
  • This silicon substrate is bonded with an insulating substrate serving as a handling wafer.
  • the single-crystal silicon layer is separated by annealing from the silicon substrate at a portion where hydrogen ions are implanted, thereby forming the SOI configuration.
  • a semiconductor device in which the single-crystal silicon integrated circuit is formed on the insulating substrate By forming a single-crystal silicon integrated circuit on the single-crystal silicon layer separated from the silicon substrate based on the process described above, a semiconductor device in which the single-crystal silicon integrated circuit is formed on the insulating substrate.
  • the restrictions do not occur on the fabrication process and/or the device configuration. This is because the single-crystal silicon layer (the layer to become the single-crystal silicon integrated circuit) is formed on the insulating substrate without the adhesive agent, like in a method such as the Smart Cut method. Instead, the following problem occurs.
  • the hydrogen ions are implanted into the silicon substrate, so that the single-crystal silicon layer is formed.
  • the hydrogen ions may be implanted into an active region, in which a field effect transistor (FET) or other devices are formed, in the single-crystal silicon layer. This causes the active region to be damaged.
  • FET field effect transistor
  • an object of the present invention is to provide a semiconductor device and a fabrication method therefor in which a single-crystal silicon integrated circuit is bonded with an insulating substrate without an adhesive agent, the semiconductor device in which an active region of the single-crystal silicon integrated circuit is not damaged by an implantation of hydrogen ions, thereby exhibiting full capacity of an element.
  • a semiconductor wafer in accordance with the present invention includes (a) a buried oxide layer formed on a silicon substrate; (b) a desired number of single-crystal silicon integrated circuits formed in an active layer on the buried oxide layer; and (c) an oxide for covering the single-crystal silicon integrated circuits, the oxide being filled in (i) a region between adjacent single-crystal silicon integrated circuits, and (ii) a region between adjacent elements in each of the single-crystal silicon integrated circuits, the oxide having such a depth that reaches the buried oxide layer.
  • the oxide may be made of the same material as the buried oxide layer.
  • a desired number of single-crystal silicon integrated circuits are formed on the silicon active layer of the buried oxide layer formed on the silicon substrate. This allows an arrangement in which the single-crystal silicon integrated circuits (single-crystal silicon layer) are separated by the buried oxide layer from silicon substrate.
  • the buried oxide layer is an oxide film which is formed by simultaneously carrying out with respect to the silicon substrate an annealing at a high temperature and an ion implantation of oxygen so that an oxide film layer is formed at a predetermined depth from the surface of the silicon substrate.
  • an oxide covers the single-crystal silicon integrated circuits, and the oxide is filled in (i) a region between adjacent single-crystal silicon integrated circuits, and (ii) a region between adjacent elements in each of the single-crystal silicon integrated circuits, the oxide having such a depth that reaches the buried oxide layer.
  • the oxide is made of the same material as the buried oxide layer, the single-crystal silicon integrated circuit which is cut out from wafer is surrounded by the oxide. As such, it is possible to equalize characteristics, such as a resistance to the etching, in all directions.
  • a method for fabricating a semiconductor wafer in accordance with the present invention includes the steps of: (A) forming an buried oxide layer on a silicon substrate; (B) forming a desired number of single-crystal silicon integrated circuits in an active layer on the buried oxide layer; (C) causing (i) a separation of the single-crystal silicon integrated circuits, and (ii) a separation of elements in each of the single-crystal silicon integrated circuits to be simultaneously carried out by using an oxide; and (D) causing the single crystal silicon integrated circuits to be surrounded by the oxide.
  • a semiconductor device in accordance with the present invention includes at least a single-crystal silicon integrated circuit on an insulating substrate, wherein the single-crystal silicon integrated circuit is surrounded by an oxide.
  • the insulating substrate may include a non-single-crystal silicon transistor, and the oxide may be a silicon dioxide.
  • the semiconductor device of the present invention is arranged such that each of the single crystal silicon integrated circuits is surrounded by the oxide. As such, because of the following reason, it is possible to bond the insulating substrate with the single crystal silicon integrated circuit, without an adhesive agent.
  • a non-single-crystal silicon transistor may be formed on the insulating substrate, along with the single-crystal silicon integrated circuit.
  • the non-single-crystal silicon transistor indicates a transistor which is formed in an amorphous silicon layer or in a polycrystalline silicon layer.
  • each single-crystal silicon integrated circuit is surrounded by the silicon dioxide.
  • a method for fabricating a semiconductor device in accordance with the present invention in which the semiconductor device includes at least a single-crystal silicon integrated circuit on an insulating substrate, said method includes the steps of: (A) forming a desired number of single-crystal silicon integrated circuits on a semiconductor wafer in which a buried oxide layer is formed on a silicon substrate; (B) carrying out, simultaneously, a separation of adjacent single-crystal silicon integrated circuits and a separation of adjacent elements in each of the single-crystal silicon integrated circuits; (C) cutting out the single-crystal silicon integrated circuits from the semiconductor wafer such that the single-crystal silicon integrated circuits have the buried oxide layer after being cut out; (D) bonding the insulating substrate with a surface, opposite to a surface on which the buried oxide layer is formed, of the single-crystal silicon integrated circuit.
  • a semiconductor device of the present invention is so arranged as shown in Fig. 1 that a single-crystal silicon integrated circuit (Hereinafter referred to as single-crystal silicon IC) 21 is bonded to an insulating substrate 101 made of a glass substrate, via an oxide film 102 made of silicon dioxide.
  • a single-crystal silicon IC 21 is cut out from an SOI (Silicon On Insulator) wafer 1 shown in Fig. 2.
  • Fig. 2 is a plane view showing the SOI wafer 1 on which the single-crystal silicon IC 21 is formed.
  • the SOI wafer 1 includes three layers, i.e., a silicon layer 2, a BOX layer (silicon oxide film (Buried Oxide)) 3, and an active layer (silicon active layer) 4.
  • a silicon layer 2 As shown in Fig. 3(a), the SOI wafer 1 includes three layers, i.e., a silicon layer 2, a BOX layer (silicon oxide film (Buried Oxide)) 3, and an active layer (silicon active layer) 4.
  • SIMOX Separatation by Implanted Oxygen
  • oxygen ions of high concentration are implanted into a single-crystal silicon wafer substrate, and at the same time the single-crystal silicon wafer substrate is annealed under a high temperature.
  • a layer formed between the buried silicon oxide layer (BOX layer 3) and the surface of the single-crystal silicon wafer substrate serves as the active layer 4.
  • the SOI wafer 1 shown in Fig. 3(a) is processed as follows so that the single-crystal silicon IC 21 is fabricated.
  • grooves 5 and 6 are formed by removing the active layer 4 on the buried silicon oxide layer 3.
  • the groove 6 is formed for causing desired number of single-crystal silicon ICs 21 to be formed on the SOI wafer 1.
  • the groove 5 is formed for causing elements to be separated from one another in each of the single-crystal silicon ICs 21 to an element and an adjacent element, respectively in the single-crystal silicon IC 21. Note that the forming of the desired number of single-crystal silicon ICs 21 and the separating of the elements in each of single-crystal silicon ICs 21 are simultaneously carried out.
  • the grooves 5 and 6 are formed as follows.
  • Resist is applied on the SOI wafer 1, and then patterned by photo lithography so as to cover regions other than the grooves 5 and 6. Thereafter, the SOI wafer 1 thus patterned is subject to an isotropic etching such as RIE (Reactive Ion Etching). The etching is carried out with respect to silicon up to such a etching depth that can reach the BOX layer 3.
  • RIE Reactive Ion Etching
  • silicon dioxide which is an oxide
  • a gas such as TEOS (Tetra Ethyl ortho silicate; Si(OC 2 H 5 ) 4
  • the silicon dioxide deposited in the groove 5 is referred to as silicon dioxide 9
  • the silicon dioxide deposited in the groove 6 is referred to as silicon dioxide 10. This allows the forming of the desired number of single-crystal silicon ICs 21 and the separating of the elements in each of single-crystal silicon ICs 21 to be simultaneously carried out.
  • the silicon dioxide 9 and 10 are so arranged as to touch the BOX layer 3 made of the silicon dioxide. As such, the single-crystal silicon IC 21 is covered, except for the surface thereof, with the silicon dioxide.
  • the present embodiment is not limited to the foregoing step.
  • the forming of the desired number of single-crystal silicon ICs 21 and the separating of the elements in each of single-crystal silicon ICs 21 may be simultaneously carried out by (i) covering the regions other than the grooves 5 and 6 with silicon nitride, and (ii) carrying out LOCOS (Local Oxidation of Silicon).
  • thermal oxidation is carried out with respect to the regions where the grooves 5 and 6 are formed.
  • the thermal oxidation is dry O 2 oxidation, and the temperature in the furnace is substantially 1050°C.
  • the oxidation in this case may be pyrogenic oxidation.
  • the silicon nitride no longer required is removed by dry etching. Note that it is important to carry out the oxidation so that separated oxide films of the BOX layer 3 and the single-crystal silicon IC 21 substantially have a continuity.
  • a gate oxide film 11 of approximately 5 nm to 30 nm is formed by the thermal oxidation on a top surface of the SOI wafer 1.
  • the gate oxide film 11 is also made of the silicon dioxide. This allows every surface of the single-crystal silicon IC 21 to be coated with the oxide (silicon dioxide).
  • a gate electrode 12 is formed on the gate oxide film 11 as shown in Fig. 4(a), with the use of a conventional LSI fabrication process.
  • a polysilicon film or a tungsten silicide film that can become the gate electrode 12 is formed on the gate oxide film 11.
  • the gate electrode 12 is patterned by the photo lithography. It is easy to achieve a micro-fabrication of 0.5 ⁇ m or less by using equipment for fabricating an LSI.
  • phosphorus or boron is implanted, in a self-aligning manner, in regions 4a where a source section and a drain section are formed, then activated by a thermal treatment at about a temperature of 1000°C.
  • An LDD (Lightly Doped Drain) or the like is formed as needed. Note that it is necessary that a depth of the silicon active region be 200 nm or less, ideally 50 nm or less, in view of short channel effect of transistors.
  • field effect transistors 20 which are the elements in the single-crystal silicon IC 21.
  • an interlayer insulating film 13 of approximately 300 nm is formed as shown in Fig. 4(b), and levelled by CMP (Chemical Mechanical Polishing) method, so that the single-crystal silicon IC 21 is completed.
  • the levelling may be by SOG (Spin On Glass) method or other methods, other than the CMP method.
  • SOG Spin On Glass
  • an insulating substrate 101 (see Fig. 1) having a plane surface and a high deformation point is prepared, apart from the single-crystal silicon IC.
  • the insulating substrate 101 is, for example, 1737 glass substrate produced by Corning. Note that the insulating substrate 101 in Fig. 1 is coated with the oxide film 102 of approximately 100 nm. However, the insulating substrate 101 may be without the oxide film 102.
  • each of the insulating substrate 101 and the single-crystal silicon IC 21 cut out from the wafer 1 is cleaned with a liquid called SC1 liquid, and then dried, prior to the bonding of them.
  • the liquid temperature is a room temperature.
  • the cleaning is carried out by soaking the single-crystal silicon IC 21 and the insulating substrate 101 into the SC1 liquid for 5 minutes. It is preferable to avoid soaking the single-crystal silicon IC 21 and the insulating substrate 101 into the SC1 liquid for a long time. This is because the ammonia water etches the surface of the silicon oxide.
  • the single-crystal silicon IC 21 and the insulating substrate 101 are then cleaned using flowing pure water (specific resistance of 10 M ⁇ cm or more) for 10 minutes, and is promptly dried using a spin dryer, or the like. After the cleaning and drying process, the single-crystal silicon IC 21 and the insulating substrate 101 are spontaneously bonded with each other, by bringing the respective surfaces of the single-crystal silicon IC 21 and the insulating substrate 101 together, and slightly pressing against each other.
  • Van der waals force, electrode duplex, and hydrogen bonding respectively contribute to the bonding of the single-crystal silicon IC 21 with the insulating substrate 101, without an adhesive agent. As such, it is easier to bond two substrates with each other, when each of the surfaces of the two substrates has a similar balance of the above three contributions.
  • a force, for bonding the single-crystal silicon IC 21 with the insulating substrate 101 is reinforced by a thermal treatment such as an annealing in an electric furnace at a temperature of 450°C to 600°C, or a lamp annealing.
  • a top portion of the BOX layer 3 in the single-crystal silicon IC 21 is etched by using a halogen gas including fluoride such as CIF 3 .
  • a halogen gas including fluoride such as CIF 3 . It is known that the halogen gas including fluoride has such a selection ratio causing a large difference between an etching rate with respect to the silicon and an etching rate with respect to the silicon dioxide. This causes only the silicon to be etched, and not the silicon dioxide.
  • etching may be carried out before the thermal treatment.
  • the silicon dioxide (the silicon dioxide 10 for causing the separation of the integrated circuits from one another, and the silicon dioxide 10 for causing the separation of the elements from one another) is formed in the region between the single-crystal silicon ICs 21, and in the region where the elements are separated from one another in each of the single-crystal silicon ICs 21.
  • the silicon dioxide 10 is so formed as to reach the BOX layer 3 of the wafer 1. Therefore, the single-crystal silicon IC 21 cut out from the wafer 1 has the active region which is surrounded by the silicon dioxide.
  • the halogen gas including the fluoride does not etch the active layer 4 (i.e., an active region for a thin film device such as a field effect transistor) formed in the single-crystal silicon IC 21.
  • a polishing of silicon may be carried out prior to the etching so that the time required to carry out the etching is shortened. The polishing will be carried out by the CMP method, the MRF method, etching or the like, before the single-crystal silicon ICs are cut out from a semiconductor wafer.
  • a desired number of single-crystal silicon ICs 21 are formed on the insulating substrate 101, and (ii) the oxide (silicon dioxide) coats every surface of the single-crystal silicon IC 21.
  • the single-crystal silicon IC 21 is bonded with the insulating substrate 101, and then the silicon layer 2 is removed by the etching. Then, using an excimer laser beam, SLS (Sequential Lateral Solidification) method is carried out with respect to a region of the insulating substrate 101 which is different from the region where the single-crystal silicon IC 21 is bonded, so that only a surface of amorphous silicon film forms poly-crystal. It should be noted that the region of the insulating substrate 101 where the single-crystal silicon IC 21 is bonded is kept from being exposed to the excimer laser beam.
  • non-single-crystal silicon integrated circuit 31 (Hereinafter referred to as non-single-crystal silicon IC), a film of a wiring metal is formed (not shown) and patterned after carrying out the steps of forming a gate insulating film, a gate electrode film, an interlayer insulating film, and a contact hole (not shown).
  • the silicon IC made of the single-crystal silicon thin film is formed so as to be surrounded by an oxide.
  • the non-single-crystal silicon IC 31 is fabricated before or after the single-crystal silicon IC 21 is fabricated.
  • the single-crystal silicon IC is formed so as to be surrounded by an oxide.
  • a desired number of single-crystal silicon ICs having the arrangement are formed on the SOI (Silicon On Insulator) substrate including a buried oxide film (BOX layer), and a single-crystal silicon layer on the BOX layer.
  • the single-crystal silicon ICs are separated from each other by an oxide which has such a depth that a continuity of the BOX layer and the oxide is maintained.
  • a predetermined number of single-crystal silicon ICs are formed on a SOI wafer.
  • a separation of the single-crystal silicon ICs and a separation of elements in each of the single-crystal silicon ICs are simultaneously carried out by the oxidation of the silicon. Then, the single-crystal silicon ICs are cut out from the SOI wafer.
  • the single-crystal silicon IC is bonded with the insulating substrate in a surface on a side of the single-crystal silicon thin film with respect to the BOX layer via the oxide film, or is bonded, at room temperature, with the insulating substrate whose surface is not coated with the oxide film.
  • the single-crystal silicon IC and the insulating substrate thus bonded undergo a thermal treatment at a temperature of 400°C (preferably at a temperature of 600 °C or higher), and undergo the etching and/or polishing so that the BOX layer is exposed. Note that the etching may be carried out before the thermal treatment.
  • a predetermined number of single-crystal silicon ICs are formed on a SOI wafer. Then, first and second grooves, each having such a depth as to reach the BOX layer, are formed by carrying out the etching with respect to (i) a region, between the adjacent single-crystal silicon ICs, which will become the first groove, and (ii) a region, between adjacent elements in each of the single-crystal silicon ICs, which will become the second groove.
  • the first groove and the second groove are respectively filled with the silicon dioxide, so as to separate the single-crystal silicon ICs from one another, and so as to separate the elements from one another. Then, the single-crystal silicon ICs are cut out from the SOI wafer.
  • the single-crystal silicon IC is bonded with the insulating substrate in a surface on a side of the single-crystal silicon thin film with respect to the BOX layer via the oxide film, or is bonded, at room temperature, with the insulating substrate whose surface is not coated with the oxide film.
  • the single-crystal silicon IC and the insulating substrate thus bonded undergo a thermal treatment at a temperature of 400°C (preferably at a temperature of 600°C or higher), and undergo the etching so that the BOX layer is exposed.
  • the configuration of the present invention it is possible to easily bond the insulating substrate with the single-crystal silicon IC via the oxide film without any adhesive agent. This is because a thermal treatment is carried out after the insulating substrate and the single-crystal silicon IC are bonded with each other, via the oxide film.
  • the active region of the transistor is protected against the halogen gas including the fluoride, which is used for removing the silicon under the BOX layer. This is because the active region of the single-crystal silicon IC is surrounded by the oxidation film.
  • the present embodiment deals with the case where the SIMOX method is utilized for fabricating the SOI wafer 1.
  • the SOI wafer 1 may be fabricated by ELTRAN (Epitaxial Layer Transfer) method disclosed, for example, in Tokukaihei 7-235651 (published on September 5, 1995), or the like.
  • the ELTRAN method is a method for separating a single-crystal silicon layer from a porous silicon layer through the steps of (i) forming an oxide film layer, the porous silicon layer, and an epitaxial silicon layer on a silicon substrate, and then (ii) bonding the silicon substrate with a handling wafer.
  • a semiconductor device of the present invention is so arranged as shown in Fig. 6 that a single-crystal silicon integrated circuit (Hereinafter referred to as single-crystal silicon IC) 61 and a non-single-crystal silicon integrated circuit (Hereinafter referred to as non-single-crystal silicon IC) 71 are bonded to an insulating substrate 201 made of a glass substrate, via an oxide film 202 made of silicon dioxide.
  • Such a single-crystal silicon IC 61 is cut out from an SOI (Silicon On Insulator) wafer 41 shown in Fig. 7.
  • Fig. 7 is a plane view showing the SOI wafer 41 on which the single-crystal silicon IC 61 is formed. Further, before or after the single-crystal silicon IC 61 is formed, the non-single-crystal silicon IC 71 is formed.
  • the SOI wafer 41 includes three layers, i.e., a silicon layer 42, a BOX layer (silicon oxide film (Buried Oxide)) 43, and an active layer (silicon active layer) 44.
  • SIMOX Separatation by Implanted Oxygen
  • oxygen ions of high concentration are implanted into a single-crystal silicon wafer substrate, and at the same time the single-crystal silicon wafer substrate is annealed under a high temperature.
  • a layer formed between the buried silicon oxide layer (BOX layer 43) and the surface of the single-crystal silicon wafer substrate serves as the active layer 44.
  • the SOI wafer 41 shown in Fig. 8(a) is processed as follows so that the single-crystal silicon IC 61 is fabricated.
  • grooves 45 and 46 are formed by removing the active layer 44 on the buried silicon oxide layer 43.
  • the groove 46 is formed for causing desired number of single-crystal silicon ICs 61 to be formed on the SOI wafer 41.
  • the groove 46 is formed for causing desired number of single-crystal silicon ICs 61 to be formed on the SOI wafer 41.
  • the groove 45 is formed for causing elements to be separated from one another in each of the single-crystal silicon ICs 61 to an element and an adjacent element, respectively in the single-crystal silicon IC 61.
  • the grooves 45 and 46 are formed as follows. Resist is applied on the SOI wafer 41, and then patterned by photo lithography so as to cover regions other than the grooves 45 and 46. Thereafter, the SOI wafer 41 thus patterned is subject to an isotropic etching such as RIE (Reactive Ion Etching). The etching is carried out with respect to silicon up to such a etching depth that can reach the BOX layer 43.
  • RIE Reactive Ion Etching
  • silicon dioxide 50 which is an oxide, is deposited in the grooves 45 and 46 while using a gas such as TEOS (Tetra Ethyl ortho silicate; Si(OC 2 H 5 ) 4 ).
  • TEOS Tetra Ethyl ortho silicate
  • the silicon dioxide 50 is so arranged as to touch the BOX layer 43 made of the silicon dioxide. As such, the single-crystal silicon IC 61 is covered, except for the surface thereof, with the silicon dioxide.
  • the present embodiment is not limited to the foregoing step.
  • the forming of the desired number of single-crystal silicon ICs 61 and the separating of the elements in each of single-crystal silicon ICs 61 may be simultaneously carried out by (i) covering the regions other than the grooves 45 and 46 with silicon nitride, and (ii) carrying out LOCOS (Local Oxidation of Silicon).
  • thermal oxidation is carried out with respect to the regions where the grooves 45 and 46 are formed.
  • the thermal oxidation is dry O 2 oxidation, and the temperature in the furnace is substantially 1050°C.
  • the oxidation in this case may be pyrogenic oxidation.
  • the silicon nitride no longer required is removed by dry etching. Note that it is important to carry out the oxidation so that separated oxide films of the BOX layer 43 and the single-crystal silicon IC 61 substantially have a continuity.
  • a gate oxide film 51 of approximately 5 nm to 30 nm is formed by the thermal oxidation on a top surface of the SOI wafer 41.
  • the gate oxide film 51 is also made of the silicon dioxide. This allows every surface of the single-crystal silicon IC 61 to be coated with the oxide (silicon dioxide).
  • a gate electrode 52 is formed on the gate oxide film 11 as shown in Fig. 8(d), with the use of a conventional LSI fabrication process.
  • a polysilicon film or a tungsten silicide film that can become the gate electrode 52 is formed on the gate oxide film 11.
  • the gate electrode 52 is patterned by the photo lithography. It is easy to achieve a micro-fabrication of 0.5 ⁇ m or less by using equipment for fabricating an LSI.
  • phosphorus or boron is implanted, in a self-aligning manner, in regions 53 where a source section and a drain section are formed, then activated by a thermal treatment at about a temperature of 1000°C.
  • An LDD (Lightly Doped Drain) or the like is formed as needed. Note that it is necessary that a depth of the silicon active region be 200 nm or less, ideally 50 nm or less, in view of short channel effect of transistors.
  • field effect transistors 60 which are the elements in the single-crystal silicon IC 61.
  • an interlayer insulating film 54 of approximately 300 nm is formed as shown in Fig. 8(f), and levelled by CMP (Chemical Mechanical Polishing) method.
  • the levelling may be by SOG (Spin On Glass) method or other methods, other than the CMP method.
  • SOG Spin On Glass
  • a contact 55 is formed in a groove formed as shown in Fig. 8(g), by carrying out dry etching and/or wet etching.
  • a conductive metal wiring 56 is formed on a surface of the contact 55 as shown in Fig. 8(h). It is preferable that the metal wiring 56 be made of a heat-resistant material such as Ti. This is because a thermal treatment is carried out later, at a temperature of 400°C to 600°C.
  • the material of the metal wiring is not limited to Ti.
  • the metal wiring 56 By forming the metal wiring 56 on the single-crystal silicon IC 61 before the single crystal silicon IC 61 is bonded with the insulating substrate, it is possible to keep designing rules for the metal wiring layout to the minimum. This allows a reduction in the layout and an improvement in the operation speed.
  • an interlayer insulating film 57 of approximately 300 nm is formed as shown in Fig. 8(i), and levelled by the CMP method, the SOG method, or other method. It is preferable to use the CMP method or the SOG method in this process as well, rather than using the mechanical polishing.
  • a thinning process may be carried out in advance with respect to a surface opposite to a levelled surface of the wafer, by using MRF (Magnetorheological Finishing) or the like (see Fig. 9(a)).
  • MRF Magnetic Heological Finishing
  • a thinning process By carrying out the thinning process in advance, it is possible to reduce time needed for later carrying out a thinning process by etching. This allows an improvement in yield of productivity.
  • the silicon layer 42 since it is difficult for the mechanical polishing to accurately control the thickness of the silicon layer 42, the silicon layer 42 ultimately needs to be removed in a post-process by carrying out the etching using the halogen gas including the fluoride.
  • the single-crystal silicon ICs are cut out from the wafer by dicing or the like.
  • each of the single-crystal silicon IC thus cut out is coated with the oxide film.
  • an insulating substrate 201 (see Fig. 6) having a plane surface and a high deformation point is prepared, apart from the single-crystal silicon IC 61.
  • the insulating substrate 201 is, for example, 1737 glass substrate produced by Corning. Note that the insulating substrate 201 in Fig. 6 is coated with the oxide film 202 of approximately 100 nm. However, the insulating substrate 201 may be without the oxide film 202.
  • each of the insulating substrate 201 and the single-crystal silicon IC 61 cut out from the wafer 41 is cleaned with a liquid called SC1 liquid, and then dried, prior to the bonding of them.
  • the liquid temperature is a room temperature.
  • the cleaning is carried out by soaking the single-crystal silicon IC 61 and the insulating substrate 201 into the SC1 liquid for 5 minutes. It is preferable to avoid soaking the single-crystal silicon IC 61 and the insulating substrate 201 into the SC1 liquid for a long time. This is because the ammonia water etches the surface of the silicon oxide.
  • the single-crystal silicon IC 61 and the insulating substrate 201 are then cleaned using flowing pure water (specific resistance of 10 M ⁇ cm or more) for 10 minutes, and is promptly dried using a spin dryer, or the like. After the cleaning and drying process, the single-crystal silicon IC 61 and the insulating substrate 201 are spontaneously bonded with each other, by bringing the respective surfaces of the single-crystal silicon IC 61 and the insulating substrate 201 together, and slightly pressing against each other (see Fig. 9(c)).
  • Van der waals force, electrode duplex, and hydrogen bonding respectively contribute to the bonding of the single-crystal silicon IC 61 with the insulating substrate 101, without an adhesive agent. As such, it is easier to bond two substrates with each other, when each of the surfaces of the two substrates has a similar balance of the above three contributions.
  • a force, for bonding the single-crystal silicon IC 61 with the insulating substrate 201 is reinforced by a thermal treatment such as an annealing in an electric furnace at a temperature of 450°C to 600°C, or a lamp annealing.
  • a top portion of the BOX layer 43 in the single-crystal silicon IC 61 is etched by using the halogen gas including the fluoride such as CIF 3 .
  • the halogen gas including fluoride has such a selection ratio causing a large difference between an etching rate with respect to the silicon and an etching rate with respect to the silicon dioxide. This causes only the silicon (the silicon layer 42 which has been subject to the thinning process) to be etched, and not the silicon dioxide.
  • the present embodiment deals with the case where the etching is carried out after the thermal treatment.
  • the etching is carried out after the thermal treatment.
  • the etching be carried out after the thermal treatment. This is because the strength for bonding the single-crystal silicon IC 61 and the insulating substrate 201 is weak without carrying out the thermal treatment. This may cause the single-crystal silicon IC 61 to be peeled or misaligned by, for example, the transfer of the substrate which is carried out during the etching process.
  • the silicon dioxide 50 is formed in the region between the single-crystal silicon ICs 61, and in the region where the elements are separated from one another in each of the single-crystal silicon ICs 61.
  • the silicon dioxide 50 is so formed as to reach the BOX layer 43 of the wafer 41. Therefore, the single-crystal silicon IC 61 cut out from the wafer 41 has the active region which is surrounded by the silicon dioxide.
  • the halogen gas including the fluoride does not etch the active layer 44 (i.e., an active region for a thin film device such as a field effect transistor) formed in the single-crystal silicon IC 61.
  • a polishing of silicon may be carried out prior to the etching so that the time required to carry out the etching is shortened. The polishing will be carried out by the MRF method or the like before the single-crystal silicon ICs are cut out.
  • a second contact 58 and a second metal wiring 59 are formed from a side of the BOX layer.
  • the second contact 58 and the second metal wiring 59 are provided for electrically connecting the single-crystal silicon IC, which has been bonded with the insulating substrate, with an external circuit such as a non-single-crystal silicon IC.
  • the present embodiment deals with the case where the second metal wiring 59 is connected via the gate electrode 52 of the single-crystal silicon IC.
  • the second metal wiring 59 is not limited to such a case.
  • the semiconductor device shown in Fig. 10 in which (i) a desired number of single-crystal silicon ICs 61 are formed on the insulating substrate 201, and (ii) the oxide (silicon dioxide) coats every surface of the single-crystal silicon IC 61.
  • the single-crystal silicon IC 61 is formed on the insulating substrate 201.
  • the following description deals with the case where the single-crystal silicon IC 61 and the non-single-crystal IC 71 coexist on a single same insulating substrate 201 (see Fig. 6).
  • the insulating substrate 201 is bonded with the single-crystal silicon IC 61, which has been cut out from the SOI wafer 41 which has been fabricated in the step shown in Fig. 8(i), and then the silicon layer 42 is removed by the etching. Then, using an excimer laser beam, SLS (Sequential Lateral Solidification) method is carried out with respect to a region of the insulating substrate 201 which is different from the region where the single-crystal silicon IC 61 is bonded (see Fig. 9(e)), so that only a surface of amorphous silicon film forms poly-crystal. This allows the formation of a non-single-crystal silicon 72. It should be noted that the region of the insulating substrate 201 where the single-crystal silicon IC 61 is bonded is kept from being exposed to the excimer laser beam.
  • a gate insulating film 80 is formed for the non-single-crystal silicon IC 71, and the gate electrode film 81 is formed on a surface of the insulating film 80 as shown in Fig. 11(a).
  • an interlayer insulating film 82 is so formed as to cover the gate electrode film 81 as shown in Fig. 11(c), and a contact hole 83 is formed as shown in Fig. 11(c) such that the contact hole reaches the gate electrode film 81 or the implanted-portion 85.
  • a wiring metal 84 is formed and patterned in the contact hole 83.
  • non-single-crystal silicon IC 71 is formed after the single-crystal silicon IC 61 is formed, it is possible to form the non-single-crystal silicon IC 71 before the single-crystal silicon IC 61 is formed.
  • the non-single-crystal 72 is formed on the insulating substrate 201 shown in Fig 12(a) (see Fig. 12(b)).
  • the gate insulating film 80 is formed for the non-single-crystal silicon IC 71, and the gate electrode film 81 is formed on the surface of the gate insulating film 80 as shown in Fig. 12(d).
  • the interlayer insulating film 82 is so formed as to cover the gate electrode film 81 as shown in Fig. 12(f).
  • the single-crystal silicon IC 61 (chip) is cut out from the SOI wafer 41, and is bonded with the insulating substrate 201 as shown in Fig. 12(g).
  • the etching is carried out with respect to the silicon layer 42 to which the thinning process has been previously carried out.
  • the contact hole 83 is formed, such that the contact hole reaches the gate electrode film 81, the implanted-portion 85, or the gate electrode 52.
  • a wiring metal 84 is formed and patterned in the contact hole 83.
  • the foregoing steps also allows the formation of the semiconductor device as shown in Fig. 6, in which the single-crystal silicon IC 61 and the non-single-crystal silicon IC 71 coexist.
  • the silicon IC made of the single-crystal silicon thin film is formed so as to be surrounded by an oxide.
  • the single-crystal silicon IC is formed so as to be surrounded by an oxide.
  • a desired number of single-crystal silicon ICs having the arrangement are formed on the SOI (Silicon On Insulator) substrate including a buried oxide film (BOX layer), and a single-crystal silicon layer on the BOX layer.
  • the single-crystal silicon ICs are separated from each other by an oxide which has such a depth that a continuity of the BOX layer and the oxide is maintained.
  • a predetermined number of single-crystal silicon ICs are formed on a SOI wafer.
  • a separation of the single-crystal silicon ICs and a separation of elements in each of the single-crystal silicon ICs are simultaneously carried out by the oxidation of the silicon. Then, the single-crystal silicon ICs are cut out from the SOI wafer.
  • the single-crystal silicon IC is bonded with the insulating substrate in a surface on a side of the single-crystal silicon thin film with respect to the BOX layer via the oxide film, or is bonded, at room temperature, with the insulating substrate whose surface is not coated with the oxide film.
  • the single-crystal silicon IC and the insulating substrate thus bonded undergo a thermal treatment at a temperature of 400°C (preferably at a temperature of 600°C or higher), and undergo the etching so that the BOX layer is exposed. Note that the etching may be carried out before the thermal treatment.
  • a predetermined number of single-crystal silicon ICs are formed on a SOI wafer. Then, first and second grooves, each having such a depth as to reach the BOX layer, are formed by carrying out the etching with respect to (i) a region, between the adjacent single-crystal silicon ICs, which will become the first groove, and (ii) a region, between adjacent elements in each of the single-crystal silicon ICs, which will become the second groove.
  • the first groove and the second groove are respectively filled with the silicon dioxide, so as to separate the single-crystal silicon ICs from one another, and so as to separate the elements from one another. Then, the single-crystal silicon ICs are cut out from the SOI wafer.
  • the single-crystal silicon IC is bonded with the insulating substrate in a surface on a side of the single-crystal silicon thin film with respect to the BOX layer via the oxide film, or is bonded, at room temperature, with the insulating substrate whose surface is not coated with the oxide film.
  • the single-crystal silicon IC and the insulating substrate thus bonded undergo a thermal treatment at a temperature of 400°C (preferably at a temperature of 600 °C or higher), and undergo the etching so that the BOX layer is exposed.
  • the present method is characterized by polishing, in advance, a surface of the SOI wafer which is opposite to a surface on which the single-crystal silicon IC is formed. As such, it is possible to reduce the time taken for the etching, and to improve the productivity.
  • the configuration of the present invention it is possible to easily bond the insulating substrate with the single-crystal silicon IC via the oxide film without any adhesive agent. This is because a thermal treatment is carried out after the insulating substrate and the single-crystal silicon IC are bonded with each other, via the oxide film.
  • the active region of the transistor is protected against the halogen gas including the fluoride, which is used for removing the silicon under the BOX layer. This is because the active region of the single-crystal silicon IC is surrounded by the oxidation film.
  • the present embodiment deals with the case where the SIMOX method is utilized for fabricating the SOI wafer 41.
  • the SOI wafer 41 may be fabricated by ELTRAN (Epitaxial Layer Transfer) method disclosed, for example, in Tokukaihei 7-235651 / 1995 (Published on September 5, 1995), or the like.
  • the ELTRAN method is a method for separating a single-crystal silicon layer from a porous silicon layer through the steps of (i) forming an oxide film layer, the porous silicon layer, and an epitaxial silicon layer on a silicon substrate, and then (ii) bonding the silicon substrate with a handling wafer.
  • a method of the present invention for fabricating a wafer may include the steps of: (A) forming an buried oxide layer on a silicon substrate; (B) forming a desired number of single-crystal silicon integrated circuits in an active layer on the buried oxide layer; (C) forming a first groove in a region where adjacent single-crystal silicon integrated circuits are separated from one another, and a second groove in a region where elements in each of the single-crystal silicon integrated circuits are separated from one another, each of the first and second grooves having such a depth that reaches the buried oxide layer; (D) filling an oxide simultaneously in the first and second grooves, so that (i) a separation of the single-crystal silicon integrated circuits, and (ii) a separation of elements in each of the single-crystal silicon integrated circuits are simultaneously carried out by using an oxide;(D) causing the single crystal silicon integrated circuits to be surrounded by the oxide.
  • the foregoing method allows obtaining of a wafer in which each of the single-crystal silicon integrated circuits is surrounded by the oxide. Further, as described above, by forming the first groove in the region where adjacent single-crystal silicon integrated circuits are separated from one another, and the second groove in the region where elements in each of the single-crystal silicon integrated circuits are separated from one another, each of the first and second grooves having such a depth that reaches the buried oxide layer, and filling the oxide simultaneously in the first and second grooves, and causing the single crystal silicon integrated circuits to be surrounded by the oxide, it is possible to separate the single crystal silicon integrated circuits from one another, and possible to separate from one another the elements in each of the single crystal silicon integrated circuits. This allows the simplification of the fabricating process, thereby avoiding a reduction of the yield.
  • a method of the present invention for fabricating a semiconductor device which includes at least a single-crystal silicon integrated circuit on an insulating substrate may include the steps of: (A) forming a desired number of single-crystal silicon integrated circuits on a silicon active layer of a semiconductor wafer in which a buried oxide layer is formed on a silicon substrate; (B) forming a first groove in a region where adjacent single-crystal silicon integrated circuits are separated from one another, and a second groove in a region where elements in each of the single-crystal silicon integrated circuits are separated from one another, each of the first and second grooves having such a depth that reaches the buried oxide layer; (C) cutting out the single-crystal silicon integrated circuits from the semiconductor wafer after an oxide is simultaneously filled in the first groove and the second groove; (D) bonding the insulating substrate with a surface, opposite to a surface on which the buried oxide layer is formed, of the single-crystal silicon integrated circuit.
  • the foregoing method allows obtaining of a semiconductor device in which each of the single-crystal silicon integrated circuits is surrounded by the oxide. Further, as described above, by forming the first groove in the region where adjacent single-crystal silicon integrated circuits are separated from one another, and the second groove in the region where elements in each of the single-crystal silicon integrated circuits are separated from one another, each of the first and second grooves having such a depth that reaches the buried oxide layer, and filling the oxide simultaneously in the first and second grooves, and causing the single crystal silicon integrated circuits to be surrounded by the oxide, it is possible to separate the single crystal silicon integrated circuits from one another, and possible to separate from one another the elements in each of the single crystal silicon integrated circuits. This allows the simplification of the fabricating process, thereby avoiding a reduction of the yield.
  • the method of the present invention for fabricating the semiconductor device may be such that (i) the strength of the bonding is improved by a heat treatment, after the single-crystal silicon integrated circuit is bonded with the insulating substrate, and (ii) before or after a heat treatment is carried out subsequently to the bonding of the single-crystal silicon integrated circuit with the insulating substrate, a thinning process is carried out up to the buried oxide layer.
  • the method of the present invention for fabricating the semiconductor device may include the steps of: (A) carrying out a thinning process by polishing or the like with respect to the semiconductor wafer, before the single-crystal silicon integrated circuit is cut out from the semiconductor wafer; (B) bonding the insulating substrate with the single-crystal silicon integrated circuit cut out from the semiconductor wafer after the thinning process; and (C) carrying out the thinning process, up to the buried oxide layer, with respect to a side of the single-crystal silicon integrated circuit opposite to a surface where the insulation substrate is bonded.
  • the thinning process is carried out with respect to the silicon layer up to certain degree before the single-crystal silicon integrated circuit is cut out from the wafer, and another thinning process is carried out by an etching using a gas or the like up to the buried oxide layer after cutting out the single-crystal silicon integrated circuit from the wafer.
  • polishing may be MRF (Magnetorheological Finishing) or the like.
  • a non-single-crystal silicon transistor may be formed on a side of the surface, with which the single-crystal silicon integrated circuits are bonded, of the insulating substrate. This allows obtaining of a semiconductor device in which the single-crystal silicon integrated circuit and the non-single-crystal silicon integrated circuit coexist.
  • the single-crystal silicon integrated circuit may be formed on the insulating substrate after the non-single-crystal silicon integrated circuit is formed on the insulating substrate. This allows obtaining of a semiconductor device in which (i) each of the single-crystal silicon integrated circuits is surrounded by the oxide, and (ii) the single-crystal silicon integrated circuit and the non-single-crystal silicon integrated circuit coexist.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2079105A1 (fr) * 2007-01-10 2009-07-15 Sharp Kabushiki Kaisha Procédé de fabrication d'un dispositif à semi-conducteur, procédé de fabrication d'un dispositif d'affichage, dispositif à semi-conducteur, procédé de fabrication d'un élément semi-conducteur et élément semi-conducteur
US8188564B2 (en) 2007-12-27 2012-05-29 Sharp Kabushiki Kaisha Semiconductor device having a planarizing film formed in a region of a step portion
WO2018114583A1 (fr) * 2016-12-19 2018-06-28 X-Celeprint Limited Structure d'isolation pour dispositifs imprimables par micro-transfert
US10361124B2 (en) 2014-06-18 2019-07-23 X-Celeprint Limited Systems and methods for controlling release of transferable semiconductor structures

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101401195B (zh) * 2006-03-28 2010-11-03 夏普株式会社 半导体元件的转印方法和半导体装置的制造方法以及半导体装置
WO2007148448A1 (fr) * 2006-06-20 2007-12-27 Sharp Kabushiki Kaisha Composant à semiconducteur et son procédé de fabrication
JP2008147418A (ja) * 2006-12-11 2008-06-26 Hitachi Ltd 薄膜トランジスタ装置、画像表示装置およびその製造方法
WO2008123117A1 (fr) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Substrat soi et procédé de réalisation d'un substrat soi
WO2008123116A1 (fr) * 2007-03-26 2008-10-16 Semiconductor Energy Laboratory Co., Ltd. Substrat soi et procédé de réalisation d'un substrat soi
SG178762A1 (en) * 2007-04-13 2012-03-29 Semiconductor Energy Lab Display device, method for manufacturing display device, and soi substrate
JP5437626B2 (ja) * 2007-12-28 2014-03-12 株式会社半導体エネルギー研究所 半導体装置及び半導体装置の作製方法
US20100289037A1 (en) * 2008-01-15 2010-11-18 Shin Matsumoto Semiconductor device, manufacturing method thereof and display device
CN104538354B (zh) * 2014-12-31 2018-01-09 深圳市华星光电技术有限公司 一种ltps tft像素单元及其制造方法
US20200372317A1 (en) * 2018-02-13 2020-11-26 Panasonic Intellectual Property Management Co., Ltd. Wireless communication semiconductor device and manufacturing method therefor
US10541214B2 (en) * 2018-04-27 2020-01-21 Juniper Networks, Inc. Enhanced bonding between III-V material and oxide material
CN113381287A (zh) * 2021-06-09 2021-09-10 中国科学院微电子研究所 一种染料激光器及其制备方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486318A1 (fr) * 1990-11-15 1992-05-20 Seiko Instruments Inc. Dispositif semi-conducteur pour utilisation dans une vanne de lumière et son procédé de fabrication
US5258325A (en) * 1990-12-31 1993-11-02 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
JPH06291291A (ja) * 1993-03-31 1994-10-18 Seiko Instr Inc 半導体装置の製造方法
EP0886306A1 (fr) * 1997-06-16 1998-12-23 IMEC vzw Procédé d'adhésion de substrates à basse température
JPH1124106A (ja) * 1997-07-03 1999-01-29 Seiko Epson Corp 液晶パネル用基板及び液晶パネル並びにそれらの製造方法
US5869867A (en) * 1996-03-19 1999-02-09 Nec Corporation FET semiconductor integrated circuit device having a planar element structure
US20020160574A1 (en) * 2001-04-27 2002-10-31 Zahurak John K. Method of forming a dual-gated semiconductor-on-insulator device
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
US20030183876A1 (en) * 2002-03-26 2003-10-02 Yutaka Takafuji Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
WO2003081664A2 (fr) * 2002-03-25 2003-10-02 Commissariat A L'energie Atomique Procede de transfert d'elements de substrat a substrat
EP1463105A2 (fr) * 2003-03-20 2004-09-29 Sharp Kabushiki Kaisha Dispositif à semi-conducteur et procede de fabrication associe par la technique de transfert

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
US3343255A (en) * 1965-06-14 1967-09-26 Westinghouse Electric Corp Structures for semiconductor integrated circuits and methods of forming them
US3918079A (en) * 1971-01-22 1975-11-04 Signetics Corp Encapsulated beam lead construction for semiconductor device and assembly and method
JPH01106466A (ja) * 1987-10-19 1989-04-24 Fujitsu Ltd 半導体装置の製造方法
JP2743391B2 (ja) * 1988-08-25 1998-04-22 ソニー株式会社 半導体メモリの製造方法
US6067062A (en) 1990-09-05 2000-05-23 Seiko Instruments Inc. Light valve device
JP2967126B2 (ja) * 1990-09-05 1999-10-25 セイコーインスツルメンツ株式会社 平板型光弁基板用半導体集積回路装置
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
WO1993015589A1 (fr) 1992-01-22 1993-08-05 Kopin Corporation Arrangement de dispositifs en silicium monocristallin destines a l'affichage par projection
JP3141486B2 (ja) * 1992-01-27 2001-03-05 ソニー株式会社 半導体装置
JP2948018B2 (ja) * 1992-03-17 1999-09-13 三菱電機株式会社 半導体装置およびその製造方法
JP3278944B2 (ja) * 1992-12-25 2002-04-30 ソニー株式会社 Ｓｏｉ型半導体装置およびその製造方法
JP3262470B2 (ja) * 1993-12-28 2002-03-04 キヤノン株式会社 半導体基板およびその作製方法
US5753529A (en) * 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
JP2654607B2 (ja) * 1994-09-22 1997-09-17 日本電気株式会社 半導体装置の製造方法
JP2674533B2 (ja) * 1994-11-14 1997-11-12 日本電気株式会社 Ｓｏｉ基板及びこれを用いた半導体装置とその製造方法
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
JPH08335684A (ja) * 1995-06-08 1996-12-17 Toshiba Corp 半導体装置
US6144101A (en) * 1996-12-03 2000-11-07 Micron Technology, Inc. Flip chip down-bond: method and apparatus
JP2001036092A (ja) * 1999-07-23 2001-02-09 Mitsubishi Electric Corp 半導体装置
US6235567B1 (en) * 1999-08-31 2001-05-22 International Business Machines Corporation Silicon-germanium bicmos on soi
KR20010086499A (ko) 2000-03-02 2001-09-13 윤종용 쏘이 기판을 사용하는 반도체 장치의 형성 방법
JP4776755B2 (ja) * 2000-06-08 2011-09-21 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US6562666B1 (en) 2000-10-31 2003-05-13 International Business Machines Corporation Integrated circuits with reduced substrate capacitance
US20020140030A1 (en) 2001-03-30 2002-10-03 Mandelman Jack A. SOI devices with integrated gettering structure
JP2003282885A (ja) * 2002-03-26 2003-10-03 Sharp Corp 半導体装置およびその製造方法
JP4974474B2 (ja) * 2004-06-22 2012-07-11 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US7358586B2 (en) * 2004-09-28 2008-04-15 International Business Machines Corporation Silicon-on-insulator wafer having reentrant shape dielectric trenches

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0486318A1 (fr) * 1990-11-15 1992-05-20 Seiko Instruments Inc. Dispositif semi-conducteur pour utilisation dans une vanne de lumière et son procédé de fabrication
US5258325A (en) * 1990-12-31 1993-11-02 Kopin Corporation Method for manufacturing a semiconductor device using a circuit transfer film
JPH06291291A (ja) * 1993-03-31 1994-10-18 Seiko Instr Inc 半導体装置の製造方法
US5869867A (en) * 1996-03-19 1999-02-09 Nec Corporation FET semiconductor integrated circuit device having a planar element structure
EP0886306A1 (fr) * 1997-06-16 1998-12-23 IMEC vzw Procédé d'adhésion de substrates à basse température
JPH1124106A (ja) * 1997-07-03 1999-01-29 Seiko Epson Corp 液晶パネル用基板及び液晶パネル並びにそれらの製造方法
US6475838B1 (en) * 2000-03-14 2002-11-05 International Business Machines Corporation Methods for forming decoupling capacitors
US20020160574A1 (en) * 2001-04-27 2002-10-31 Zahurak John K. Method of forming a dual-gated semiconductor-on-insulator device
WO2003081664A2 (fr) * 2002-03-25 2003-10-02 Commissariat A L'energie Atomique Procede de transfert d'elements de substrat a substrat
US20030183876A1 (en) * 2002-03-26 2003-10-02 Yutaka Takafuji Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
EP1463105A2 (fr) * 2003-03-20 2004-09-29 Sharp Kabushiki Kaisha Dispositif à semi-conducteur et procede de fabrication associe par la technique de transfert

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2079105A1 (fr) * 2007-01-10 2009-07-15 Sharp Kabushiki Kaisha Procédé de fabrication d'un dispositif à semi-conducteur, procédé de fabrication d'un dispositif d'affichage, dispositif à semi-conducteur, procédé de fabrication d'un élément semi-conducteur et élément semi-conducteur
EP2079105A4 (fr) * 2007-01-10 2012-07-25 Sharp Kk Procédé de fabrication d'un dispositif à semi-conducteur, procédé de fabrication d'un dispositif d'affichage, dispositif à semi-conducteur, procédé de fabrication d'un élément semi-conducteur et élément semi-conducteur
US8188564B2 (en) 2007-12-27 2012-05-29 Sharp Kabushiki Kaisha Semiconductor device having a planarizing film formed in a region of a step portion
US10361124B2 (en) 2014-06-18 2019-07-23 X-Celeprint Limited Systems and methods for controlling release of transferable semiconductor structures
WO2018114583A1 (fr) * 2016-12-19 2018-06-28 X-Celeprint Limited Structure d'isolation pour dispositifs imprimables par micro-transfert
US10297502B2 (en) 2016-12-19 2019-05-21 X-Celeprint Limited Isolation structure for micro-transfer-printable devices

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US20050098827A1 (en) 2005-05-12
EP1531489A3 (fr) 2007-10-17
KR20050045893A (ko) 2005-05-17
US7390696B2 (en) 2008-06-24
KR100732403B1 (ko) 2007-06-27
US20080164623A1 (en) 2008-07-10

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