Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
  • H10B12/0383—Making the capacitor or connections thereto the capacitor being in a trench in the substrate wherein the transistor is vertical
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/05—Making the transistor
  • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/01—Manufacture or treatment
  • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
  • H10B12/03—Making the capacitor or connections thereto
  • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
  • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
  • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
  • H10B12/48—Data lines or contacts therefor
  • H10B12/488—Word lines

Definitions

• the present invention relates to a memory cell with a trench formed in a substrate.
• the trench is suitable for arranging a trench capacitor and a vertical selection transistor above the trench capacitor in the trench.
• Memory components such as DRAMs (Dynamic Random Access Memories), consist of a cell array and a control periphery, with individual memory cells being arranged in the cell array.
• DRAMs Dynamic Random Access Memories
• a DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns and are driven by word lines and bit lines. The reading out of data from the memory cells or the writing of data into the memory cells is accomplished by activating suitable word lines and bit lines.
• a DRAM memory cell usually contains a transistor connected to a capacitor.
• the transistor consists, among other things, of two diffusion regions which are separated from one another by a channel which is controlled by a gate. Depending on the direction of the current flow, one diffusion region is referred to as the drain region and the other diffusion region is referred to as the source region.
• One of the diffusion regions is connected to a bit line, the other diffusion region to the capacitor and the gate to a word line.
• the transistor is controlled so that a
• the selection transistor can be formed as a vertical transistor in a trench above a trench capacitor.
• a generic memory cell with a trench capacitor and a vertical transistor is known from US 5,744,386. Further explanations regarding trench capacitors or transistors are described in US Pat. No. 5,208,657.
• a memory cell with: a substrate; a trench which has a lower region, a middle region, an upper region and an inner wall and is arranged in the substrate, the lower region being arranged below the middle region and the middle region below the upper region;
• an insulation collar which is arranged in the central region on the inner wall of the trench;
• a dielectric layer arranged in the lower region of the trench;
• a conductive trench filling which is arranged the lower region and the central region of the trench;
• an epitaxially grown layer which is arranged in the upper region of the trench on the inner wall of the trench and on the conductive trench filling, a barrier layer being arranged between the conductive trench filling and the epitaxially grown layer.
• the advantage of the barrier layer which is arranged between the conductive trench filling and the epitaxially grown layer, is its effect as a diffusion barrier against dopants or metals and other materials that are present in the conductive trench filling.
• the barrier layer is advantageously designed in such a way that it represents a barrier for the materials, but not for the electrical charge, which is stored in the trench capacitor.
• An advantageous embodiment of the arrangement according to the invention provides that a second dielectric layer with an inner opening is arranged in the upper region of the trench above the epitaxially grown layer.
• the advantage of the second dielectric layer is that it can be used to self-adjust a gate connection from a word line to the gate electrode of the vertical transistor.
• the second dielectric layer serves as a mask for the free etching of the gate electrode when it is connected to the word line. This has the The advantage that only significantly less stringent adjustment tolerances have to be observed, which offers the possibility of driving the miniaturization process further.
• the trench can be made wider than the contacts and wider than the word line for more efficient use of the available area, since the etching process automatically etches the inner opening in the second dielectric layer. This results in lower safety requirements and a more space-saving word line - Layout possible.
• a method for producing a memory cell comprising the steps of: forming a trench in a substrate which has a lower one
• Region a central region, an upper region and an inner wall
• a second dielectric layer with an inner opening in the upper region of the trench, above the epitaxially grown layer is formed.
• the advantage of the second dielectric layer with the inner opening is that with its help a gate Connection of a word line to a gate electrode of the vertical transistor can be formed in a self-aligned manner.
• a further advantageous method step consists in the barrier layer being overgrown laterally during the epitaxial growth of the layer, starting from the inner wall of the trench. Mechanical stresses in the epitaxially grown layer are reduced, since it can slide on the barrier layer.
• a closing joint is formed in the layer, which is healed by means of a thermal step at a temperature between 900 and 1200 ° C.
• the annealing step can be carried out in ultra high vacuum (UHV) at a pressure between 10 ⁇ 5 and 10 ⁇ 10 Torr, preferably at 10 ⁇ 9 Torr and a temperature between 400 ° C and 900 ° C, preferably at 500 ° C.
• UHV ultra high vacuum
• the thermal annealing step is also referred to as the reflow step and on the one hand leads to mechanical stresses of the epitaxially grown one
• a further advantageous embodiment of the method according to the invention provides that a second trench is formed in the epitaxially grown layer and a dielectric layer is formed on a side wall of the second trench.
• the dielectric layer is a gate oxide. It is advantageous here that the gate oxide is formed on the epitaxially grown layer and insulates the channel of the transistor from a gate electrode.
• One variant of the method provides that the second trench is formed up to the barrier layer.
• a further variant of the method provides that trench bottom insulation is formed in the second trench on the barrier layer.
• an isolation trench is arranged such that it surrounds the memory cell and an adjacent memory cell and an active region is formed between the memory cell and the adjacent memory cell, which is doped. This arrangement connects two adjacent memory cells to an active area, on which a bit line contact can later be formed.
• the channel region of the vertical transistor is not isolated, as would be the case with an SOI transistor (Silicon On Insulator).
• SOI transistor Silicon On Insulator
• the bulk connection improves the control behavior of the vertical transistor and it can be put into a blocking state again by means of a suitable gate voltage.
• the isolation trench also has the task of isolating the memory cell and the adjacent memory cell from the other memory cells, as a result of which leakage currents are reduced.
• the epitaxially grown layer has a further doped region which is connected to the conductive trench filling and has an upper doped region which is connected to the active region.
• the doped regions form the source region and the drain region of the vertical transistor.
• a further advantageous embodiment of the invention provides that a bit line runs over the active area and contacts the active area.
• the bit line is routed in sections over the isolation trench and in sections over the active area, which is contacted thereby.
• F- 03 SD N »d ⁇ F" F 1 ⁇ t- CD d F- ⁇ ⁇ ri F - li F 1 SD tr i ⁇ d 0 N ⁇ li li ⁇ ⁇ 0 tr F- ⁇ F 1 rt F d tr ⁇ F- 03 O tr d rt ⁇ tr to SD 3
• F- 5 ⁇
• ⁇ rt rt SD a s PJ d ⁇ d d CQ ⁇ CQ ö-: F) F- d ⁇ li ⁇ ü d li • CQ tr F- 03 F- M
• Figure 2 3,, 5 and 6 successive manufacturing steps of a memory cell based on Figure 1;
• FIGS. 10 and 11 show a second variant of manufacturing steps for a memory cell, starting from FIG. 7;
• FIG. 12 and FIG. 13 show a further variant with manufacturing steps of a memory cell, starting from FIG. 7;
• FIG. 14 to FIG. 20 successive production steps of a trench capacitor, subsequently the
• FIG. 21 top view of an arrangement of trenches
• FIG. 22 top view of an arrangement of active areas
• FIG. 23 top view of an arrangement of bit lines
• FIG. 24 top view of an arrangement of memory cells
• FIG. 25 top view of a further arrangement of bit lines
• FIG. 26 top view of an arrangement of memory cells
• FIG. 27 top view of an arrangement of word lines.
• FIG. 1 shows a memory cell 1 which comprises a trench 3 which is formed in a substrate 2.
• substrate 2 consists of silicon, which can be doped with boron, phosphorus or arsenic.
• the trench 3 has a lower region 4, a middle region 5 and an upper region 6.
• the trench 3 also has an inner wall 7.
• An insulation collar 8 is arranged on the inner wall 7 in the middle region 5 and the upper region 6 of the trench 3.
• the insulation collar 8 usually consists of silicon oxide.
• the hard mask 50 is formed, for example, from silicon nitride.
• the inner wall 7 of the trench 3 is lined with a dielectric layer 9 in the lower region 4 of the trench 3.
• the dielectric layer 9 can optionally be located in the middle region 5 and in the upper region 6 on the insulation collar 8 or under the insulation collar 8, that is to say on the inner wall 7 of the trench.
• the trench 3 is filled with a conductive trench filling 10.
• the conductive trench filling 10 consists, for example, of doped silicon, a metal silicide, a metal nitride or a metal which can comprise the elements titanium, tantalum, tungsten, cobalt, nickel and molybdenum.
• the conductive trench filling 10 serves as the inner one
• Silicicides such as titanium silicide, cobalt silicide and wolfra silicide as well as metals and metal compounds such as tungsten, tungsten nitride and titanium nitride are suitable as further materials for the barrier layer 60. These materials also permit a selective epitaxy process, the selective epitaxy not growing on the tungsten nitride or titanium nitride, but growing laterally - starting from the inner trench wall 7 of the trench 3.
• a silicidation step is then carried out at a temperature of approx. 700 ° C. for a period of between 10 and 60 seconds in a nitrogen-containing atmosphere.
• the deposited metal layer reacts with a silicon arranged below it to form a silicide.
• the rest of the metal remains on a layer of e.g. Silicon oxide or silicon nitride.
• the metal is subsequently removed by means of a cleaning step with H20 / NH40H / H202 in a ratio of 5/1/1 at approx. 65 ° C. (Hot Huang A).
• a further temperature step can then be carried out at temperatures of around 850 ° C in a nitrogen-containing atmosphere in order to improve the conductivity of the silicide layer.
• a subsequent cleaning step can be performed with Huang A B (SCI / SC2) to remove particles and contaminants.
• the barrier layer can be formed by means of doping.
• the conductive trench filling 10 consists, for example, of polycrystalline silicon, nitrogen, Tungsten or carbon as a dopant are introduced into the conductive trench filling and form the barrier layer 60.
• the doping can be carried out, for example, by means of plasma doping or ion implantation at an acceleration energy of less than 1 keV. This corresponds to an ultra low energy (ULE) ion implantation to form very flat doping regions.
• UEE ultra low energy
• an epitaxially grown layer 11 is grown in an epitaxial step in the upper region 5 and in the middle region 6 of the trench 3.
• the epitaxially grown silicon grows on existing silicon. Since the conductive trench filling 10 is covered by the barrier layer 60, the epitaxially grown silicon grows laterally starting from the inner wall 7 of the trench 3 in a ring-like structure, a closing joint 61 being formed there, where different growth fronts of the epitaxially grown silicon layer meet.
• a hydrogen prebake can be carried out at approx. 900 ° C and approx. 20 torr.
• the surface of a silicon layer is cleaned, e.g. Silicon oxide is removed.
• the epitaxial layer can e.g. at 900 ° C with the Precürsor gases SiH2Cl2 / HC1 / H2 with the flow rates 180 sccm / 120 sccm / 10 slm at a pressure of 15 Torr.
• a reflow process is carried out, for example, in a process chamber under a hydrogen atmosphere at a temperature between 900 ° C. and 1100 ° C., preferably 1050 ° C. and an H2 gas flow of 15 slm for a period of between 10 and 60 seconds.
• the epitaxial layer can be grown in UHV at approx. 500 ° C with silane or Si2H6 as a precursor.
• a pressure between 10 ⁇ 3 and 10 -7 is suitable and a Pressure of 10 ⁇ 5 Torr preferred.
• the annealing step (reflow) can be carried out in UHV at approx. 10 ⁇ 9 Torr. It is advantageous to use low temperatures around 500 ° C. since this includes a smaller temperature budget, which enables the use of a capacitor dielectric with a high dielectric constant in the trench capacitor.
• the reflow enables the epitaxially grown layer to flow, while the monocrystalline structure of the epitaxially grown layer is retained.
• the process steps for the epitaxial growth of a silicon layer and the annealing (reflow) of the epitaxially grown silicon layer can be repeated any number of times in order to produce an epitaxially grown silicon layer without a closing joint with a desired thickness.
• the cross section of the trench 3 consequently requires a 10 to 100 nm thick, selectively grown silicon epitaxial layer.
• the closing joint 61 is avoided and a single-crystalline silicon block is formed above the conductive trench filling 10. This is connected seamlessly and without dislocation to the substrate 2 via the inner wall 7 of the trench 3.
• the vertical transistor is then produced in the silicon block.
• FIG. 6 shows the barrier layer 60 on the conductive trench filling 10.
• the monocrystalline silicon block 11, which has grown epitaxially, is arranged on the barrier layer 60.
• FIG. 2a shows a variant of the method in which only the conductive trench filling 10 is sunk in and the insulation collar 8 remains.
• a partial thinning of the isolation trench is shown with reference to FIG. 3a. If the insulation collar has a thickness of approx. 40 nanometers, approx. 30 n are removed, which is carried out, for example, with a wet chemical etching. 4a, the conductive trench filling 10 is sunk again and the barrier layer 60 is formed, as described, for example, in connection with FIG.
• the insulation collar 8 is etched in conformity, the inner wall 7 of the trench 3 being partially exposed.
• the insulation collar 8 partially remains in a thin form above the barrier layer 60 9.
• the epitaxially grown layer 11 is subsequently formed, as described in connection with FIG. 5.
• FIG. 3b Another method variant, which is based on FIG. 2a, is shown in FIG. 3b.
• the insulation collar 8 initially remains completely in the trench 3 and the conductive trench filling 10 is sunk deeper.
• the barrier layer 60 is deposited over the entire area and a lacquer filling 64 is filled into the trench and sunk.
• the barrier layer is removed from the surface of the hard mask 50 and remains there in the trench 3, where the barrier layer 60 with the lacquer filling 64 is protected from the etching.
• the insulation collar 8 is subsequently removed from the side wall 7 of the trench 3.
• the barrier layer is U-shaped or goblet-shaped in section.
• a further process variant according to FIG. 3c forms the dielectric layer only after the isolation trench has been formed.
• the trench is then filled with the conductive trench filling, which is sunk in the upper region 6 of the trench 3.
• the dielectric layer 9 is subsequently selectively removed from the insulation collar 8 in the upper region 6, e.g. removed by wet chemical etching.
• the conductive trench filling 10 is sunk again and subsequently the barrier layer 60 is formed.
• the insulation collar 8 is removed from the upper area 6 and the inner wall 7 of the trench 3 is exposed.
• figure 3g it is shown that the dielectric layer 9 has been removed from the insulation collar, which e.g. can be carried out by means of a wet chemical etching.
• FIG. 3h Another method variant, which follows FIG. 3f, is shown in FIG. 3h.
• a lacquer filling 64 is filled into the trench 3 and etched back.
• the part of the dielectric layer 9 which is not protected by the lacquer filling 64 is then removed, and then the lacquer filling 64 is removed.
• a second dielectric layer 12 is deposited.
• the second dielectric layer 12 is, for example, a silicon nitride layer applied by means of a CVD process.
• the subsequent etching of the epitaxially grown layer 11 is carried out in such a way that the second trench 63 formed in this way extends as far as the barrier layer 60. Then, implantations are also carried out to form the lower doping region 18 and the upper doping region 19. Furthermore, the third dielectric layer 14 is formed as a gate oxide. The gate electrode 23 is then produced using the method steps already described above.
• trench bottom insulation 62 is additionally formed in the second trench 63.
• the trench bottom insulation 62 has the advantage that a subsequently inserted gate electrode 23 is insulated from the conductive trench filling 10.
• a conformal oxide layer is deposited, so that the second trench 63 is filled with silicon oxide.
• the silicon oxide layer is then removed from the surface of the hard mask 50 by means of a CMP process and the silicon oxide is sunk into the second trench 63 by means of a sinking process, so that the trench bottom insulation 62 is produced.
• the gate electrode 23 is produced in accordance with the method described above.
• a mask 53 is deposited on the substrate and structured, so that parts of the underlying structure are exposed.
• the mask 53 is placed in such a way that it covers an active region 17 to be formed and releases those regions of the surface in which the isolation trench 15 is later formed. It is particularly advantageous to choose the opening in the mask 53 such that the second dielectric layer 12 is at least partially exposed.
• the advantage is that as Adjustment tolerance, the width of the lateral spacing web of the second dielectric layer 12 is available. Further adjustment tolerance for the formation of the active areas is achieved by previously filling the inner opening 13 with planarizing material. After opening a thin one
• a subsequent nitride etching can be carried out selectively to the planarizing material with the cover layer with the mask 53.
• An anti-reflective layer (ARC), for example, is suitable as a planarizing material. As a result, the entire cross-sectional area of the trench 3 is available as an adjustment tolerance.
• a first etching step is carried out to form the isolation trench.
• a second etching step is carried out to form the isolation trenches, this etching step being carried out selectively with respect to the material of the second dielectric layer 12, which in this case is formed from silicon nitride. This method ensures that the isolation trench 15 is formed in a self-aligned manner between adjacent trenches.
• the mask 53 is removed from the substrate surface and optionally the planarizing material from the opening 13, thermal oxidation of the opened isolation trenches is carried out and then an oxide - for example an HDP oxide (high density Plasma Oxyd) - deposited, which forms the isolation trench 15 and the oxide filling 54 in the inner opening
• the surface is then planarized using a CMP process and the hard mask 50 is removed from the substrate surface.
• the gate electrode 23 is connected to a word line 24.
• FIG. 21 shows the hexagonal arrangement of storage trenches.
• the trench 3 is also shown.
• the hexagonal arrangement is particularly favorable since it reduces imaging errors in the lithographic exposure.
• FIG. 22 shows a mask for the formation of the active areas and an active area 17 is marked.
• FIG. 23 shows a first course of bit lines, the bit line 20 running parallel to the other bit lines.
• FIG. 24 shows the combination of FIGS. 21, 22 and 23 with different overlays for better identification of the position, two trenches in each case being connected by an active region 17 and the bit line 20 partly via the active region 17 and partly via the
• Isolation trench 15 runs.
• FIG. 25 Another exemplary embodiment of a bit line arrangement is shown in FIG. 25, the bit line 20 being arranged in a zigzag pattern.
• FIGS. 21, 22 and 25 The combination of FIGS. 21, 22 and 25 is shown with reference to FIG.
• the trench 3 is connected with the active region 17 to an adjacent trench and is surrounded by the isolation trench 15. Furthermore, the course of the bit line 20 is shown, which in turn runs partly over the active region 17 and over the isolation trench 15. Furthermore, a section line A is shown in FIG. 24, which intersects the active regions 17 in the longitudinal direction.
• FIG. 24 An advantage of the invention is that a silicon nitride cover with an inner opening 13 is produced in the trench 3 above the vertical transistor. In order to clarify the position, the inner opening 13 is shown in some trenches as examples in FIGS. 24 and 26. Since the bit lines are sheathed, for example, with a dielectric sheath 21, it is possible to form the contact with the gate electrode 23 in a self-aligned manner when the gate connection 28 is formed between the bit lines and through the inner opening 13. Furthermore, it is advantageous according to the invention not to arrange the trench 3 under the intersection of the word line and the bit line, but slightly offset from it.
• a particular advantage of the method according to the invention is the increased adjustment tolerance, which is made possible by the self-adjusted process of the gate connection production. This makes it possible to connect the word line to the gate electrode.
• Another advantage of the invention is that the inner opening 13 is opened in a self-adjusted manner from above and the gate connection 28 is contacted in a self-adjusted manner. This makes it possible to design the trench with a larger diameter than the minimum structure width in order to increase the capacity of the trench.
• Another advantage of the method according to the invention is that the gate oxide does not grow out of the trench 3, but is only formed on the epitaxially grown layer 11 in the second trench 63.
• Another advantage of the method according to the invention is that the upper doped region 19 is connected to the active region 17.
• Bit line 20 also runs on active area 17 and connects to it.
• Another advantage of the method according to the invention is to surround the bit line with an insulation sleeve. It is particularly advantageous to form the dielectric shell 21 from silicon nitride, since this can be used as an etching mask in subsequent oxide structures.
• Another advantage of the method according to the invention is the word line 24 above the bit line 20, as a result of which the coupling capacitance between the word line and the bit line is kept low and the total capacitance of the bit line is also low, which enables the memory cell to be read out reliably.
• a buried plate (burried plate) can be provided as the counter electrode of the trench capacitor.
• a buried plate can be provided as the counter electrode of the trench capacitor.
• dopant is diffused into the substrate from the trench 3 filled with a doped material.
• a buried trough can be provided (burried layer) which connects the buried plates of adjacent trench capacitors.

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• 2001
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