EP1314201A1 - Procede de realisation d'un anti-fusible et anti-fusible permettant la connexion electrique selective de zones conductrices voisines - Google Patents

Procede de realisation d'un anti-fusible et anti-fusible permettant la connexion electrique selective de zones conductrices voisines

Info

Publication number
EP1314201A1
EP1314201A1 EP01958074A EP01958074A EP1314201A1 EP 1314201 A1 EP1314201 A1 EP 1314201A1 EP 01958074 A EP01958074 A EP 01958074A EP 01958074 A EP01958074 A EP 01958074A EP 1314201 A1 EP1314201 A1 EP 1314201A1
Authority
EP
European Patent Office
Prior art keywords
layer
conductive
antifuse
sacrificial layer
fuse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01958074A
Other languages
German (de)
English (en)
Inventor
Matthias Lehr
Uwe Schilling
Veronika Polei
Irene Sperl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1314201A1 publication Critical patent/EP1314201A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method for producing antifuses and an antifuse for the selective electrical connection of adjacent conductive areas.
  • Fuses are generally understood to mean conductive connections which are integrated in an integrated circuit and which can be separated by certain measures after completion of the circuit in order to make certain individual settings for the integrated circuit. In doing so, they maintain their setting even without a supply voltage being applied, i.e. they are usually characterized by a permanent physical connection or separation of two contacts. The most common are so-called aser fuses. These are formed by thin conductor tracks, which can be cut with a laser beam depending on the desired setting, thereby opening the conductive connection.
  • Antifuses are known for example from "Application-Specific Integrated Circuits", Ch. 4.1, 1997, Addison Wesley Longman, Ine. They are the opposite of a conventional fuse, i.e. they represent an initially open switch that can be activated by a suitable measure, e.g. can be closed by applying a programming current. Antifuses usually consist of thin insulating layers between two conductive contacts. They are switched by making the insulating layer conductive after the application of a programming voltage.
  • Integrated antifuses usually consist of a dielectric layer on top of a contact or Conductor layer is applied and on which there is another contact area.
  • Such antifuse structures are usually produced by depositing a dielectric layer over the entire area and then essentially over the entire area, except in the lithographically defined fuse areas, by means of dry etching (RIE: Reactive Ion Etching), so that islands of dielectric material on the contact layer remain.
  • RIE Reactive Ion Etching
  • Conductor layers of the underlying conductor level are attacked and their surface is undesirably changed.
  • antifuses for the selective electrical connection of adjacent conductive regions are produced by first applying a sacrificial layer to the surface of a first conductive region, which is located in a non-conductive region of a substrate.
  • This sacrificial layer is first structured, for example with the aid of a photolithographic process, so that a window is created over the first conductive area.
  • a fuse layer is applied to the sacrificial layer structured in this way.
  • This fuse layer is preferably a dielectric layer.
  • a non-conductive layer is applied thereon, which is provided with contact openings, into which conductive material is introduced, in order to form a second conductive region.
  • This manufacturing method has the advantage that at no time exposed conductive areas are exposed to an etching process or another harmful process, which can be attacked and damaged as a result.
  • this process is a simple manufacturing process with which both standard contacts and anti-fuse
  • the fuse layer is formed from a dielectric material and also has a contact layer via which the dielectric material of the fuse layer and the second conductive region are contacted.
  • This has the advantage that the contact layer can be used as an etching stop layer in the step of introducing the contact opening into the non-conductive layer. It can thus be avoided that the dielectric layer is etched through if the etching process is too long for the production of the contact holes and then an electrical connection is established between the first and the second conductive region and thus no fuse contact is formed.
  • the removal of the sacrificial layer further comprises that the surface of this sacrificial layer is previously freed of the fuse layer with the aid of a CMP process (Chemical Mechanical Polishing).
  • CMP process Chemical Mechanical Polishing
  • the sacrificial layer is more easily accessible to a subsequent selective etching process, in which the etchant is selected so that it does not attack the fuse layer. If the fuse layer on the sacrificial layer were not removed by a CMP process, it would be it makes sense to carry out a further masking step before an etching process for the joint removal of the fuse layer and the sacrificial layer. This masking step is then necessary in order to protect the fuse layer on the first conductive region from the etching process, because the etchant to be used etches fuse layer as well as sacrificial layer.
  • FIG. 1 shows a manufacturing process of an antifuse
  • FIGS. 1 a to 1 a showing cross sections through the semiconductor structure according to FIG
  • Fig. 2 shows schematically an antifuse, which is made with the method of Fig.l.
  • the manufacturing method shown in FIG. 1 is carried out on a substrate material, which is preferably processed with the aid of standard planar technology, in which a sequence of individual processes that act over the entire surface of the wafer surface is carried out, which specifically lead to local change in the semiconductor material via suitable masking layers.
  • a preprocessed material serves as the starting material
  • Substrate wafer (not shown) preferably essentially made of silicon, on the surface of which there is an oxide layer 1, into which conductive regions 2, 2 'of tungsten are introduced, the surfaces of which are exposed.
  • oxide layer 1 into which conductive regions 2, 2 'of tungsten are introduced, the surfaces of which are exposed.
  • the sacrificial layer 3 can consist of BPSG, BSG, polysilicon, amorphous silicon or, depending on the etching chemistry, corresponding other materials.
  • the sacrificial layer 3 is preferably structured using a photolithographic process.
  • a photoresist layer 4 is applied to the sacrificial layer 3 and structured photolithographically, so that the sacrificial layer 3 is not covered by the photoresist layer 4 over the conductive regions 2, 2 'on which an antifuse structure is to be formed.
  • this window in the lacquer layer 4 exposes the sacrificial layer 3 up to the surface of the conductive region 2.
  • the photoresist layer 4 is then removed and then a dielectric layer 5 and a contacting layer 6 are applied over the entire surface.
  • the dielectric layer 5 preferably consists of a dielectric material such as Si 3 N / SiON or Si0 2 , but other dielectric materials can also be used.
  • the contacting layer 6 consists of a material that is conductive and that forms a stable connection with the dielectric layer 5.
  • the dielectric layer 5 and the contacting layer 6 of the surface of the sacrificial layer 3 are removed by a CMP method (Chemical Mechanical Polishing) where it is located on the sacrificial layer 3.
  • CMP method Chemical Mechanical Polishing
  • the layers 5, 6 in the previously exposed window of the sacrificial layer 3 remain.
  • a structure is thus obtained in which the sacrificial layer 3 is exposed and a dielectric layer 5 and a contacting layer 6 are located in the regions above the conductive region 2.
  • the dielectric layer 5 and the contacting layer 6 can also be removed by an etching process, in which case the region above the conductive region 2 must be masked so that the layers 5, 6 are not removed by the etching step.
  • FIG. 1d A structure is shown in FIG. 1d as it is after the sacrificial layer 3 has been removed and the subsequent one Application of an oxide layer 7 arises.
  • the sacrificial layer 3 can be etched with H 2 S0 4 / HF-containing solutions or comparable etching agents.
  • windows are provided at the points at which the contacts are to be made with the aid of a photolithographic masking and subsequent etching, which, depending on whether simple contacting of the under the Conductive region 2 'located in the oxide layer or an antifuse structure is to be formed, extend completely or as far as the contacting layer 6 through the oxide layer 7.
  • the etching process or the etching agents of the etching process are selected such that the etching process in the antifuse structure ends either after the oxide layer 7 has been etched through, determined by the etching time or after the contacting layer 6 has been reached.
  • the contacting layer 6 serves as an etching stop layer, so that the dielectric layer 5 is protected from being etched through.
  • Contacting layer forms. In this way, contacts 8, 8 'accessible from the surface are formed.
  • the dielectric layer consists of Si 3 N
  • the sacrificial layer consists of BPSG or BSG, which is removed with the aid of a wet-chemical lift-off method using H2S0 4 / HF-containing solutions. Since the etching rate of H 2 S0 4 / HF-containing solutions in BPSG or BSG is significantly higher than that in Si 3 N 4 , the sacrificial layer 3 can be removed almost without impairing the dielectric layer 5.
  • a contacting layer 6 it is suitable as an etching stop layer for the contact openings of the conductive region 8, as a result of which the dielectric layer 5 can be protected against etching through.
  • the dielectric layer 5 itself can represent such an etching stop layer, as a result of which the use of the contacting layer 6 becomes superfluous.
  • an antifuse is schematically shown, which was produced by the method described above. It has a first conductive region 2, which is embedded in an oxide layer 1 on a substrate. A dielectric fuse layer 5, which covers the first conductive region 2, is located on this first conductive region 2. A precise adjustment is not necessary. Above the fuse layer 5 there is a contacting layer 6, which is provided for process reasons. It serves primarily to avoid destruction or damage to the fuse layer 2 in subsequent process steps. On the contacting layer 6 there is an oxide layer 7, in which there is a contact opening reaching as far as the contacting layer 6, into which a conductive material 8, eg tungsten is introduced. Of course, it can be provided that further conductive areas can be provided below the conductive layer 2, which may be in contact with the conductive area.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La présente invention concerne un procédé de réalisation de structures anti-fusibles et d'anti-fusibles qui permettent la connexion électrique sélective de zones conductrices voisines. Le procédé comprend l'application d'une couche consommable (3) sur une première zone conductrice (2), la structuration de la couche consommable par un processus photolythographique, l'application d'une couche fusible (5, 6), l'élimination de la couche consommable, l'application d'une couche isolante (7), la formation d'une ouverture dans la couche isolante, et l'introduction de matériau conducteur dans l'ouverture afin de former une deuxième couche conductrice (8).
EP01958074A 2000-09-01 2001-08-16 Procede de realisation d'un anti-fusible et anti-fusible permettant la connexion electrique selective de zones conductrices voisines Withdrawn EP1314201A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10043215 2000-09-01
DE10043215A DE10043215C1 (de) 2000-09-01 2000-09-01 Verfahren zur Herstellung einer Antifuse, Antifuse zur selektiven elektrischen Verbindung von benachbarten leitenden Bereichen und integrierte Schaltung mit einer Antifuse
PCT/EP2001/009427 WO2002019426A1 (fr) 2000-09-01 2001-08-16 Procede de realisation d'un anti-fusible et anti-fusible permettant la connexion electrique selective de zones conductrices voisines

Publications (1)

Publication Number Publication Date
EP1314201A1 true EP1314201A1 (fr) 2003-05-28

Family

ID=7654708

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01958074A Withdrawn EP1314201A1 (fr) 2000-09-01 2001-08-16 Procede de realisation d'un anti-fusible et anti-fusible permettant la connexion electrique selective de zones conductrices voisines

Country Status (7)

Country Link
US (1) US6716678B2 (fr)
EP (1) EP1314201A1 (fr)
JP (1) JP4007912B2 (fr)
KR (1) KR100508889B1 (fr)
DE (1) DE10043215C1 (fr)
TW (1) TWI226104B (fr)
WO (1) WO2002019426A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7067896B2 (en) * 2002-11-13 2006-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Microelectronic fabrication having edge passivated bond pad integrated with option selection device access aperture
US8030736B2 (en) * 2009-08-10 2011-10-04 International Business Machines Corporation Fin anti-fuse with reduced programming voltage
CN115811882A (zh) * 2021-09-14 2023-03-17 联华电子股份有限公司 半导体结构

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0590527A (ja) * 1991-09-27 1993-04-09 Fujitsu Ltd 半導体装置及びその製造方法
US5449947A (en) * 1993-07-07 1995-09-12 Actel Corporation Read-disturb tolerant metal-to-metal antifuse and fabrication method
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
US5759876A (en) * 1995-11-01 1998-06-02 United Technologies Corporation Method of making an antifuse structure using a metal cap layer
US5602053A (en) * 1996-04-08 1997-02-11 Chartered Semidconductor Manufacturing Pte, Ltd. Method of making a dual damascene antifuse structure
US5856213A (en) * 1996-07-25 1999-01-05 Vlsi Technology, Inc. Method of fabricating a programmable function system block using two masks and a sacrificial oxide layer between the bottom metal and an amorphous silicon antifuse structure
US5811870A (en) * 1997-05-02 1998-09-22 International Business Machines Corporation Antifuse structure
US5904507A (en) * 1998-02-23 1999-05-18 National Semiconductor Corporation Programmable anti-fuses using laser writing
US6245663B1 (en) * 1998-09-30 2001-06-12 Conexant Systems, Inc. IC interconnect structures and methods for making same
DE10121240C1 (de) * 2001-04-30 2002-06-27 Infineon Technologies Ag Verfahren zur Herstellung für eine integrierte Schaltung, insbesondere eine Anti-Fuse, und entsprechende integrierte Schaltung
TW508788B (en) * 2001-11-12 2002-11-01 United Microelectronics Corp Production method of anti-fuse

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO0219426A1 *

Also Published As

Publication number Publication date
TWI226104B (en) 2005-01-01
US6716678B2 (en) 2004-04-06
DE10043215C1 (de) 2002-04-18
JP4007912B2 (ja) 2007-11-14
WO2002019426A1 (fr) 2002-03-07
KR100508889B1 (ko) 2005-08-18
US20030157752A1 (en) 2003-08-21
KR20030020441A (ko) 2003-03-08
JP2004508715A (ja) 2004-03-18

Similar Documents

Publication Publication Date Title
DE68923305T2 (de) Elektrische Leitungen für elektronische Bauelemente.
DE69417725T2 (de) Micro-bearbeitetes relais und verfahren zur herstellung des relais
EP0698288B1 (fr) Procede de fabrication de composants semiconducteurs a interconnexions verticales
DE19727232C2 (de) Analoges integriertes Halbleiterbauelement und Verfahren zu dessen Herstellung
DE4320286A1 (de) Verfahren zum elektrischen Kontaktieren des Aktivbereichs einer Halbleiteranordnung
DE19501557C2 (de) CMOS-Halbleitervorrichtung und Verfahren zu deren Herstellung
WO2000031796A1 (fr) Procede de production d'un circuit integre traite sur ses deux faces
DE3783404T2 (de) Leitende aktivierungsverbindungen fuer halbleiteranordnungen.
DE69932472T2 (de) Halbleiter-Schmelzsicherung
DE3900654A1 (de) Drucksensoranordnung und verfahren zu deren herstellung
DE102005019702A1 (de) Schmelzsicherungsanordnung und Herstellungsverfahren
DE69031243T2 (de) Dynamische wahlfreie Speichereinrichtung
EP0753204A1 (fr) Procede de fabrication d'un composant semiconducteur pour integration verticale et utilisation pour test
DE2922016A1 (de) Vlsi-schaltungen
DE3856450T2 (de) Verfahren zur Herstellung von einer elektrisch programmierbaren integrierten Schaltung mit schmelzbaren Kontaktbrücken
EP0698293B1 (fr) Procede de fabrication d'un composant semi-conducteur a connexions electriques assurant une haute densite d'integration
DE19653614A1 (de) Verfahren zur Herstellung von Zwischenanschlüssen in Halbleitereinrichtungen
EP1198836B1 (fr) Fusible pour dispositif a semiconducteur
DE19618866B4 (de) Verfahren zur Herstellung einer Bauelementisolation in einem Halbleiterbauelement
DE3223619A1 (de) Halbleiteranordnung
DE10043215C1 (de) Verfahren zur Herstellung einer Antifuse, Antifuse zur selektiven elektrischen Verbindung von benachbarten leitenden Bereichen und integrierte Schaltung mit einer Antifuse
DE19983274B4 (de) Verfahren zum Herstellen eines nichtflüchtigen Halbleiterspeicherbauteils
DE3930622A1 (de) Statischer ram
DE10107666C1 (de) Herstellungsverfahren für eine integrierte Schaltung, insbesondere eine Antifuse
DE68906133T2 (de) Programmierbare schmelzbare Verbindungsstruktur, die Plasmametallätzen erlaubt.

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20021026

AK Designated contracting states

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

RBV Designated contracting states (corrected)

Designated state(s): AT BE CH CY FR GB IE IT LI

REG Reference to a national code

Ref country code: DE

Ref legal event code: 8566

17Q First examination report despatched

Effective date: 20080814

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: QIMONDA AG

19U Interruption of proceedings before grant

Effective date: 20090401

19W Proceedings resumed before grant after interruption of proceedings

Effective date: 20091123

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20100526