EP1269204A2 - Agencement de circuits de test et procede permettant de tester plusieurs transistors - Google Patents

Agencement de circuits de test et procede permettant de tester plusieurs transistors

Info

Publication number
EP1269204A2
EP1269204A2 EP01915081A EP01915081A EP1269204A2 EP 1269204 A2 EP1269204 A2 EP 1269204A2 EP 01915081 A EP01915081 A EP 01915081A EP 01915081 A EP01915081 A EP 01915081A EP 1269204 A2 EP1269204 A2 EP 1269204A2
Authority
EP
European Patent Office
Prior art keywords
transistors
tested
transistor
coupled
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP01915081A
Other languages
German (de)
English (en)
Inventor
Ute Kollmer
Ulrich Schaper
Carsten Linnenbank
Roland Thewes
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1269204A2 publication Critical patent/EP1269204A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/27—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements
    • G01R31/275—Testing of devices without physical removal from the circuit of which they form part, e.g. compensating for effects surrounding elements for testing individual semiconductor components within integrated circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2607—Circuits therefor
    • G01R31/2621—Circuits therefor for testing field effect transistors, i.e. FET's
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • the invention relates to a test circuit arrangement and a method for testing a plurality of transistors.
  • test circuit arrangement and such a method are known from [1] and [2].
  • a common electrical circuit element that is used in the field of semiconductor technology is a transistor, in particular a MOS field-effect transistor.
  • MOS field-effect transistors are used in m analog circuits, it is often necessary to have as precise a knowledge as possible of the properties of the circuit elements that are produced in a specific manufacturing process under specified manufacturing conditions and thus of their behavior in an analog circuit.
  • the transistors themselves have very different properties within a chip on the wafer. These different properties of the transistors are usually referred to as mismatching of the (MOS) field-effect transistors.
  • test structure which has reference transistors on a reference wafer, which was also manufactured under the manufacturing conditions to be examined.
  • the properties of the field-effect transistor or the field-effect transistors are determined by means of such a test structure and are made available to the circuit designer, who allows these properties to be incorporated into his design of a circuit can, whereby a more reliable and reliable design of an electrical, especially analog, circuit with such field effect transistors is possible.
  • test circuit arrangement known from [1] and [2] has transistors to be tested, which are arranged in a matrix m columns and rows.
  • a column decoder and a row decoder are coupled to the transistors to be tested, which together act as address decoders for selecting the - serve each transistor to be tested.
  • selection transistors for decoupling or selection of the transistors to be tested are connected between the column decoder and row decoder.
  • Each transistor to be tested is arranged in a diode circuit, that is to say the gate connection of the field-effect transistor to be tested is short-circuited to its dram connection.
  • V * denotes a drain voltage present at the drain terminal of the field effect transistor.
  • [5] describes how its electrical properties can be determined on the basis of the temporal successive application of a voltage pulse to the gate electrode and a voltage pulse to the source electrode.
  • [6] describes a circuit arrangement with which it can be tested whether an N-MOS field-effect transistor, which is connected to a P-MOS field-effect transistor, works or not. According to this circuit arrangement, a maximum of two transistors can be tested in terms of their functionality. It should also be pointed out that only the large signal behavior is determined in accordance with [6]. The circuit arrangement described cannot determine the clamp signal behavior.
  • the invention is therefore based on the problem of specifying a test circuit arrangement and a method for testing a multiplicity of transistors which are coupled to one another and with which an accurate determination of the clamp signal behavior of field effect transistors is possible in an automated manner.
  • test circuitry as well as by the method for testing a variety of test circuitry
  • Transistors are provided which are coupled together.
  • the test circuit arrangement also assigns one to the Tested transistors coupled electrical selection unit for selecting at least one transistor to be tested.
  • a gate voltage source is provided, which can be coupled to the gate connection of each transistor to be tested.
  • a source voltage source can be coupled to the source connection of each transistor to be tested.
  • a measuring unit coupled to the drain connections of the transistors to be tested is provided for measuring the dram current that flows through the respectively selected transistor.
  • a transistor to be tested is selected from the plurality of transistors to be tested by means of an electrical selection unit.
  • a gate voltage, a drain voltage or a source voltage is applied to the gate, the drain or the source of the selected transistor varying around a predetermined operating point of the transistor to be tested.
  • the drain current resulting from the applied gate voltage, dram voltage or source voltage and flowing through the selected transistor is measured.
  • the clamp signal behavior of the transistor to be investigated is determined from the measured dram currents and the associated applied gate voltages, Dra voltages or source voltages.
  • a voltage is usually varied in each case and the further voltages are usually kept constant at a predetermined operating point (for example, when determining the g ⁇ s, the Dra voltage is varied and the source voltage and the Gat voltage become constant at the selected operating point held) .
  • the invention makes it possible to automate
  • Small signal behavior means, for example, the slope g m , the differential output conductance gos', the threshold voltage Vp of the field effect transistor and the dynamic current gain of a field effect transistor in the emitter circuit ⁇ .
  • the further refinements of the invention relate both to the test circuit arrangement and to the method for testing a large number of transistors.
  • the transistors to be tested can be arranged in pairs, their gate connections being coupled to one another and the source connections being coupled to each other.
  • the paired arrangement of the transistors to be tested further compensates for possible store flows.
  • a paired arrangement of transistors corresponds to a common arrangement, the properties of which are of exceptional interest for circuit designers
  • Embodiment of the invention provided to arrange each transistor pair m a predetermined distance from each other.
  • the predetermined distance is preferably the same for all transistor pairs.
  • At least one selection transistor is provided for each transistor to be tested, for selecting the transistor to be tested, the at least one selection transistor being coupled to the electrical selection unit.
  • Four selection transistors are preferably provided for each transistor to be tested, in order to ensure reliable decoupling of the non-selected field effect transistors from the selected field effect transistor.
  • selection transistors are MOS field-effect transistors.
  • the transistors to be tested can be arranged in the form of a matrix with rows and columns, and the electrical selection unit can have a column decoder and a row decoder, which together form an addressing unit for selecting a transistor to be examined for a row and a column of the matrix. This configuration creates a very regular and thus compact and inexpensive test circuit arrangement.
  • the column decoder and / or the row decoder can be shift registers.
  • the automatic addressing that is to say the automatic selection of the field effect transistor to be tested as part of the overall selection, that is to say as part of the overall test, in which all field effect transistors of the test circuit arrangement to be tested must be tested , quickly and easily possible.
  • a complex addressing mechanism for addressing a transistor to be tested within a matrix is therefore not necessary.
  • any addressing mechanism can also be provided, for example the selection unit can be formed by means of free addressing registers, which are assigned by an external control unit with the corresponding addresses of the transistor to be tested within the matrix.
  • a first operational amplifier is provided, the non-inverting input of which is coupled to a drain reference voltage source.
  • the inverting input of the first operational amplifier is coupled to the drain connections of the transistors to be tested in such a way that a parasitic voltage drop at the selection transistors can be compensated for.
  • the first operational amplifier clearly makes it possible to self-compensate for interference within the To ensure circuit arrangement by means of the control loop formed by the first operational amplifier.
  • alternative control mechanisms and regulators can also be used in the test circuit arrangement according to the invention.
  • a second operational amplifier can be provided, the non-inverting input of which is coupled to the source voltage source as a reference voltage source.
  • the inverting input of the second operational amplifier is coupled to the source connections of the transistors to be tested in such a way that a parasitic voltage drop at the couplings between the transistors can be compensated for.
  • the output of the second operational amplifier is coupled to the source connections of the transistors to be examined.
  • This configuration further increases the accuracy of the test result, particularly in the case of a growing number of transistors to be tested which are contained in the test circuit arrangement.
  • FIG. 1 shows a test circuit arrangement according to an exemplary embodiment of the invention
  • Figure 2 shows a test circuit arrangement according to a
  • Figure 3 is a sketch with which the principle, a - f that the
  • Fig.l shows a test circuit arrangement 100 according to an exemplary embodiment of the invention.
  • the Tes circuit arrangement 100 has a row decoder 101 and a column decoder 102 as selection means.
  • the row decoder 101 and the column decoder 102 are each designed as shift registers.
  • the cell connections and column connections contained in the test circuit arrangement 100 are controlled successively in columns and / or rows by suitable control of the shift registers.
  • the test circuit arrangement 100 has n ⁇ m field effect transistors DUT ⁇ to be tested, with one
  • each field effect transistor to be tested is uniquely identified within the test circuit arrangement 100.
  • the field effect transistors DUT __- j to be tested are arranged in pairs in each case in a row such that the gate connections of all field effect transistors DUT 1 in the m row are coupled to one another and also to a gate voltage source 103 via a gate line 104. Furthermore, the source connections of all field effect transistors DUT 1 to be tested are coupled to one another within a row and to a source voltage source 105 via a source line 106.
  • Field effect transistor DUT ⁇ is coupled to a decoupling unit 107, which consists of 4 field effect transistors T sense / y flf , Tforce, y, l, j / T sen se, x, ⁇ ,.
  • Tforce, x, I has.
  • the source connection of a first field effect transistor Tsense, x, ⁇ is coupled to the source connection of a second field effect transistor Tf orce , ⁇ , ⁇ , and to the dram connection of the field effect transistor DUT ⁇ ] to be tested in each case.
  • the two gate connections of the first field effect transistor Tsense, x, ⁇ , j un of the second field effect transistor ⁇ force, x, ⁇ , j are coupled to one another and to the cell coupling 108, that is to say the address line I and above that to the row decoder 101.
  • the dram connection of the first field effect transistor ⁇ sense, x is with the source connection of a third field effect transistor T sense; f X / - j coupled.
  • the dram connection of the second field effect transistor Tforce, x, I , within the A-okoppelemheit 107 is coupled to the source connection of a fourth field effect transistor T force y 1 D.
  • the gate connections of the third field effect transistor ⁇ sense, y, ⁇ , and d of the fourth field effect transistor Tforce, y, ⁇ , j each of all decoupling units 107 of a line within the test circuit arrangement 100 are connected to one another and coupled to the column decoder 102 via a column coupling 109.
  • the source terminals ense the third field effect transistors T S, y, ⁇ , j of all Abkoppelritten 107 are coupled together and through a line 110 to an inverting input 111 of an operational amplifier 112th
  • the non-inverting input 115 of the operational amplifier 105 is coupled to a Dra reference voltage source 116, which supplies a dram reference voltage V ** - ⁇ re f.
  • a current measuring device 117 is connected between the output 1114 of the operational amplifier 112 and the further line 113 to determine the dram current 1 * 3 flowing through the field effect transistor DUT ⁇ to be tested in each case.
  • the operational amplifier 112 may be both in the test circuit arrangement 100 and outside the test circuit arrangement 100, that is to say that it may or may not form a chip with the test circuit arrangement.
  • the source monitoring unit is used as the current measuring device 117 and to implement the operational amplifier 112.
  • TM of a parameter analyzer from Hewlett-Packard HP4156B used.
  • a control circuit is implemented by the operational amplifier 112, by means of which the drain voltage V Q provided by the field effect transistors DUTj_j to be tested is regulated.
  • the operational amplifier 112 and its connection within the test circuit arrangement 100 ensure that the parasitic voltage drop across the field effect transistors Tforce, y, i, j and T force , x , i is automatically compensated for within the decoupling unit 107.
  • Field effect transistors DUTj_j are negligibly small.
  • the test circuit arrangement 100 is operated in the course of the measurement phase in such a way that for each field effect transistor DUTj_j to be tested for one or more operating points, in each case by varying the gate voltage or the drain voltage which is applied to the field effect transistor DUT j to be tested, is varied and for each changed voltage value, the drain current flowing through the selected field effect transistor DUT j to be tested is determined.
  • the threshold voltage V-p of the field effect transistor to be tested and the size ⁇ can also be determined.
  • FIG. 2 shows the test circuit arrangement 100 from FIG. 1 with an additional second operational amplifier 201, the non-inverting input 202 of which is coupled to the source voltage source 105.
  • Operational amplifier 201 is coupled to all source connections of all field effect transistors DUTi to be tested.
  • FIG. 3 shows the basic diagram of the test circuit arrangement 100 in the event that exactly one field effect transistor DUTi to be tested is selected.
  • the invention relates both to PMOS field-effect transistors and to NMOS field-effect transistors thereon.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

La présente invention concerne un agencement de circuits de test. Chaque borne de grille d'un transistor à tester est connectée à une source de tension de grille, de façon que la tension de grille à chaque borne de grille peut être mesurée et réglée de manière individuelle. De plus, la borne de source de chaque transistor à tester peut être connectée à la source de tension de source, de façon que la tension de source à chaque borne de source peut être mesurée et réglée de manière individuelle.
EP01915081A 2000-03-10 2001-03-05 Agencement de circuits de test et procede permettant de tester plusieurs transistors Withdrawn EP1269204A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10011657 2000-03-10
DE10011657 2000-03-10
PCT/DE2001/000835 WO2001067601A2 (fr) 2000-03-10 2001-03-05 Agencement de circuits de test et procede permettant de tester plusieurs transistors

Publications (1)

Publication Number Publication Date
EP1269204A2 true EP1269204A2 (fr) 2003-01-02

Family

ID=7634203

Family Applications (1)

Application Number Title Priority Date Filing Date
EP01915081A Withdrawn EP1269204A2 (fr) 2000-03-10 2001-03-05 Agencement de circuits de test et procede permettant de tester plusieurs transistors

Country Status (4)

Country Link
US (1) US6873173B2 (fr)
EP (1) EP1269204A2 (fr)
KR (1) KR20020081417A (fr)
WO (1) WO2001067601A2 (fr)

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JP2004219126A (ja) * 2003-01-10 2004-08-05 Agilent Technologies Japan Ltd 電流レンジを自動的に変更する方法
US8214169B2 (en) * 2003-08-18 2012-07-03 International Business Machines Corporation Circuits and methods for characterizing random variations in device characteristics in semiconductor integrated circuits
US7489151B2 (en) * 2005-10-03 2009-02-10 Pdf Solutions, Inc. Layout for DUT arrays used in semiconductor wafer testing
US7535021B2 (en) * 2005-11-01 2009-05-19 Alpha & Omega Semiconductor, Ltd. Calibration technique for measuring gate resistance of power MOS gate device at water level
CN100495057C (zh) * 2005-12-22 2009-06-03 中芯国际集成电路制造(上海)有限公司 利用阵列与解码器进行器件表征的方法与系统
KR100685886B1 (ko) * 2005-12-29 2007-02-26 동부일렉트로닉스 주식회사 트랜지스터의 테스트방법
US7394276B2 (en) * 2006-01-17 2008-07-01 International Business Machines Corporation Active cancellation matrix for process parameter measurements
US7423446B2 (en) * 2006-08-03 2008-09-09 International Business Machines Corporation Characterization array and method for determining threshold voltage variation
US7902852B1 (en) * 2007-07-10 2011-03-08 Pdf Solutions, Incorporated High density test structure array to support addressable high accuracy 4-terminal measurements
US8862426B2 (en) * 2007-12-20 2014-10-14 International Business Machines Corporation Method and test system for fast determination of parameter variation statistics
US7868640B2 (en) * 2008-04-02 2011-01-11 International Business Machines Corporation Array-based early threshold voltage recovery characterization measurement
TWI382425B (zh) * 2008-06-24 2013-01-11 United Microelectronics Corp 檢測缺陷之測試系統及其測試方法
US7859285B2 (en) * 2008-06-25 2010-12-28 United Microelectronics Corp. Device under test array for identifying defects
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US7952378B2 (en) * 2008-12-31 2011-05-31 Texas Instruments Incorporated Tunable stress technique for reliability degradation measurement
US8779796B2 (en) * 2010-09-29 2014-07-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method and apparatus for device parameter measurement
AU2017261852A1 (en) * 2016-05-13 2018-11-22 Weir Minerals Australia Ltd A wear indicating component and method of monitoring wear
DE102016114146A1 (de) * 2016-08-01 2018-02-01 Endress+Hauser Flowtec Ag Testsystem zur Überprüfung von elektronischen Verbindungen
JP6767713B2 (ja) * 2016-09-28 2020-10-14 Smc株式会社 位置検出スイッチ及びその製造方法
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Also Published As

Publication number Publication date
WO2001067601A3 (fr) 2002-04-25
WO2001067601A2 (fr) 2001-09-13
US6873173B2 (en) 2005-03-29
US20030112028A1 (en) 2003-06-19
KR20020081417A (ko) 2002-10-26

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