EP1113501B1 - MOSFET de puissance à électrode de grille en tranchée - Google Patents

MOSFET de puissance à électrode de grille en tranchée Download PDF

Info

Publication number
EP1113501B1
EP1113501B1 EP00128393A EP00128393A EP1113501B1 EP 1113501 B1 EP1113501 B1 EP 1113501B1 EP 00128393 A EP00128393 A EP 00128393A EP 00128393 A EP00128393 A EP 00128393A EP 1113501 B1 EP1113501 B1 EP 1113501B1
Authority
EP
European Patent Office
Prior art keywords
trench
region
mosfet
substrate
drift region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP00128393A
Other languages
German (de)
English (en)
Other versions
EP1113501A3 (fr
EP1113501A2 (fr
Inventor
Anup Bhalla
Jacek Dr. Korec
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Vishay Siliconix Inc
Original Assignee
Siliconix Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconix Inc filed Critical Siliconix Inc
Publication of EP1113501A2 publication Critical patent/EP1113501A2/fr
Publication of EP1113501A3 publication Critical patent/EP1113501A3/fr
Application granted granted Critical
Publication of EP1113501B1 publication Critical patent/EP1113501B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Claims (9)

  1. MOSFET, comprenant :
    une puce semi-conductrice (69) ayant des première et seconde surfaces principales, la puce semi-conductrice comprenant un substrat (63) et une couche épitaxiale (62) recouvrant le substrat (63) ;
    une tranchée (68) s'étendant à partir de la première surface principale de la puce semi-conductrice, la tranchée ayant des première et seconde sections qui définissent une mesa (72) ;
    une grille (61) disposée dans la tranchée et isolée par une couche diélectrique (70) de la puce semi-conductrice, la grille étant dopée avec des ions d'un premier type de conductivité ;
    une région source (65) du premier type de conductivité située dans la mesa (72) adjacente à la première surface principale de la puce semi-conductrice ;
    une région de corps (64) d'un second type de conductivité située dans la mesa sous la région source et adjacente à la tranchée (68) ; et
    une région de drain du premier type de conductivité située sous la région de corps (64), la région de drain comprenant une région de dérive (66) du premier type de conductivité, au moins une partie de la région de dérive étant située dans la couche épitaxiale,
    dans lequel la densité de charge nette des ions du premier type de conductivité dans une partie de la région de dérive (66) entre les tranchées n'est pas supérieure à 5 x 1012 cm-2, mesurée en référence à un plan perpendiculaire à la surface supérieure de la puce semi-conductrice et calculée comme un entier de la concentration de dopage nette à travers la mesa (72) à partir de la première section jusqu'à la seconde section de la tranchée ; et
    dans laquelle une concentration de dopage du premier type de conductivité dans la région de dérive (66) a un profil de dopage à gradient de type gaussien, linéaire sur une échelle logarithmique, augmentant progressivement en direction du substrat (63) de la jonction entre la région de dérive (66) et la région de corps (64) jusqu'à un endroit où la concentration de dopage commence à augmenter en conséquence d'une diffusion ascendante de dopant à partir du substrat ; et
    dans lequel au moins une partie de la région de dérive (66) est située dans la mesa (72).
  2. MOSFET selon la revendication 1, dans lequel la tranchée (68) s'étend jusqu'à l'endroit où le linéaire sur un profil de dopage à gradient à échelle logarithmique de la région de dérive se termine et la concentration de dopage commence à augmenter en conséquence de la diffusion ascendante de dopant à partir du substrat (63).
  3. MOSFET selon la revendication 1, dans lequel une partie de la région de dérive (66) est interposée entre un fond de la tranchée (68) et le substrat (63).
  4. MOSFET selon la revendication 1, dans lequel la couche épitaxiale a environ 2,5 µm d'épaisseur, la tranchée a environ 1,7 µm de profondeur, et la concentration de dopage de la région de dérive est à environ 7 x 1015 cm-3 au niveau de la jonction entre la région de dérive et la région de corps et environ 3,5 x 1016 cm-3 à un niveau où la concentration de dopage commence à augmenter à la suite de la diffusion ascendante de dopant à partir du substrat.
  5. MOSFET selon la revendication 1, dans lequel :
    la région de corps est implantée avec une dose d'implant de 3,0 x 1012 cm-2 à une énergie d'implant de 100 keV ou 120 keV ou 140 keV, la concentration de dopage de corps maximale étant de l'ordre de 5 x 1016 cm-3;
    la longueur du canal est de l'ordre de 0,4 µm ;
    le profil de dopage à gradient de type gaussien de la région de dérive (66), linéaire sur une échelle logarithmique, et augmentant dans la direction du substrat est d'environ 7 x 1015 cm-3 au niveau de la jonction entre la région de dérive (66) et la région de corps (64) et d'environ 4 x 1016 cm-3 à l'endroit où le linéaire sur un profil de dopage à gradient à échelle logarithmique se termine et la concentration de dopage commence à augmenter en conséquence de la diffusion ascendante de dopant à partir du substrat (63) ;
    la couche épitaxiale est du silicium de 2,5 µm d'épaisseur, la tranchée (68) a 1,7 µm de profondeur ;
    la région source a une concentration de dopage d'environ 2 x 1020 cm-3 à la première surface principale ; et
    la région de drain de substrat a une concentration de dopage d'environ 2 x 1019 cm-3.
  6. MOSFET selon la revendication 1, dans lequel :
    la couche diélectrique (70) est de l'oxyde et a une épaisseur de 50 nm ;
    la région de corps est implantée avec une dose d'implant de corps de 2,5 x 1012 cm-2 à une énergie d'implant de 120 keV ;
    la largeur de la tranchée (68) est de 0,8 µm ; et
    la largeur de la mesa (72) est de 1,2 µm.
  7. MOSFET selon la revendication 1, dans lequel :
    la couche diélectrique (70) est de l'oxyde et a une épaisseur de 50 nm ;
    la région de corps est implantée avec une dose d'implant de corps de 2,5 x 1012 cm-2 à une énergie d'implant de 140 keV ;
    la largeur de la tranchée (68) est de 0,8 µm ; et
    la largeur de la mesa (72) est de 1,6 µm.
  8. MOSFET selon la revendication 1, dans lequel une épaisseur de la couche diélectrique (70) au niveau d'un fond de la tranchée est d'environ 0,2 µm.
  9. MOSFET selon la revendication 1, dans lequel la couche diélectrique (70) a une épaisseur de 30 nm, et dans lequel la tension de seuil est d'environ 0,6 volt.
EP00128393A 1999-12-30 2000-12-22 MOSFET de puissance à électrode de grille en tranchée Expired - Lifetime EP1113501B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/476,320 US6285060B1 (en) 1999-12-30 1999-12-30 Barrier accumulation-mode MOSFET
US476320 1999-12-30

Publications (3)

Publication Number Publication Date
EP1113501A2 EP1113501A2 (fr) 2001-07-04
EP1113501A3 EP1113501A3 (fr) 2004-07-07
EP1113501B1 true EP1113501B1 (fr) 2011-07-27

Family

ID=23891378

Family Applications (1)

Application Number Title Priority Date Filing Date
EP00128393A Expired - Lifetime EP1113501B1 (fr) 1999-12-30 2000-12-22 MOSFET de puissance à électrode de grille en tranchée

Country Status (4)

Country Link
US (1) US6285060B1 (fr)
EP (1) EP1113501B1 (fr)
JP (1) JP2001210822A (fr)
AT (1) ATE518251T1 (fr)

Families Citing this family (74)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001085685A (ja) * 1999-09-13 2001-03-30 Shindengen Electric Mfg Co Ltd トランジスタ
US6348712B1 (en) * 1999-10-27 2002-02-19 Siliconix Incorporated High density trench-gated power MOSFET
GB0005650D0 (en) * 2000-03-10 2000-05-03 Koninkl Philips Electronics Nv Field-effect semiconductor devices
US7745289B2 (en) 2000-08-16 2010-06-29 Fairchild Semiconductor Corporation Method of forming a FET having ultra-low on-resistance and low gate charge
KR100338783B1 (en) * 2000-10-28 2002-06-01 Samsung Electronics Co Ltd Semiconductor device having expanded effective width of active region and fabricating method thereof
US6803626B2 (en) 2002-07-18 2004-10-12 Fairchild Semiconductor Corporation Vertical charge control semiconductor device
US6710403B2 (en) 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6818513B2 (en) 2001-01-30 2004-11-16 Fairchild Semiconductor Corporation Method of forming a field effect transistor having a lateral depletion structure
US6870220B2 (en) * 2002-08-23 2005-03-22 Fairchild Semiconductor Corporation Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses
US6916745B2 (en) 2003-05-20 2005-07-12 Fairchild Semiconductor Corporation Structure and method for forming a trench MOSFET having self-aligned features
JP2002270840A (ja) * 2001-03-09 2002-09-20 Toshiba Corp パワーｍｏｓｆｅｔ
US6639276B2 (en) 2001-07-05 2003-10-28 International Rectifier Corporation Power MOSFET with ultra-deep base and reduced on resistance
JP2003046085A (ja) * 2001-08-01 2003-02-14 Seiko Epson Corp 半導体装置及びその製造方法
US6486511B1 (en) * 2001-08-30 2002-11-26 Northrop Grumman Corporation Solid state RF switch with high cutoff frequency
GB0122122D0 (en) * 2001-09-13 2001-10-31 Koninkl Philips Electronics Nv Trench-gate semiconductor devices and their manufacture
US6657254B2 (en) * 2001-11-21 2003-12-02 General Semiconductor, Inc. Trench MOSFET device with improved on-resistance
DE10207309B4 (de) * 2002-02-21 2015-07-23 Infineon Technologies Ag MOS-Transistoreinrichtung
US6573561B1 (en) * 2002-03-11 2003-06-03 International Business Machines Corporation Vertical MOSFET with asymmetrically graded channel doping
US7701001B2 (en) * 2002-05-03 2010-04-20 International Rectifier Corporation Short channel trench power MOSFET with low threshold voltage
KR100642961B1 (ko) * 2002-05-10 2006-11-10 에프. 호프만-라 로슈 아게 골다공증 치료 및 예방용 비스포스폰산
US7576388B1 (en) 2002-10-03 2009-08-18 Fairchild Semiconductor Corporation Trench-gate LDMOS structures
US6710418B1 (en) 2002-10-11 2004-03-23 Fairchild Semiconductor Corporation Schottky rectifier with insulation-filled trenches and method of forming the same
JP2004304155A (ja) * 2003-03-19 2004-10-28 Seiko Instruments Inc 半導体装置の製造方法
JP2004342863A (ja) * 2003-05-16 2004-12-02 Shindengen Electric Mfg Co Ltd 半導体装置
US7652326B2 (en) 2003-05-20 2010-01-26 Fairchild Semiconductor Corporation Power semiconductor devices and methods of manufacture
GB0324313D0 (en) * 2003-10-17 2003-11-19 Koninkl Philips Electronics Nv Trench insulated gate field effect transistor
DE10355588B4 (de) * 2003-11-28 2006-06-14 Infineon Technologies Ag MOS-Transistoreinrichtung
KR100994719B1 (ko) 2003-11-28 2010-11-16 페어차일드코리아반도체 주식회사 슈퍼정션 반도체장치
US7368777B2 (en) 2003-12-30 2008-05-06 Fairchild Semiconductor Corporation Accumulation device with charge balance structure and method of forming the same
JP2005302925A (ja) * 2004-04-09 2005-10-27 Toshiba Corp 半導体装置
US7352036B2 (en) 2004-08-03 2008-04-01 Fairchild Semiconductor Corporation Semiconductor power device having a top-side drain using a sinker trench
KR100712989B1 (ko) 2005-03-14 2007-05-02 주식회사 하이닉스반도체 리세스 채널 및 비대칭접합 구조를 갖는 반도체 소자의제조방법
DE102005014743B4 (de) * 2005-03-31 2013-12-05 Infineon Technologies Austria Ag MOS-Feldplattentrench-Transistoreinrichtung
DE102005014744B4 (de) * 2005-03-31 2009-06-18 Infineon Technologies Ag Trenchtransistor mit erhöhter Avalanchefestigkeit und Herstellungsverfahren
JP2008536316A (ja) 2005-04-06 2008-09-04 フェアチャイルド・セミコンダクター・コーポレーション トレンチゲート電界効果トランジスタおよびその形成方法
KR101296922B1 (ko) 2005-06-10 2013-08-14 페어차일드 세미컨덕터 코포레이션 전하 균형 전계 효과 트랜지스터
US7385248B2 (en) * 2005-08-09 2008-06-10 Fairchild Semiconductor Corporation Shielded gate field effect transistor with improved inter-poly dielectric
US7446374B2 (en) 2006-03-24 2008-11-04 Fairchild Semiconductor Corporation High density trench FET with integrated Schottky diode and method of manufacture
US7319256B1 (en) 2006-06-19 2008-01-15 Fairchild Semiconductor Corporation Shielded gate trench FET with the shield and gate electrodes being connected together
US9437729B2 (en) * 2007-01-08 2016-09-06 Vishay-Siliconix High-density power MOSFET with planarized metalization
US9947770B2 (en) 2007-04-03 2018-04-17 Vishay-Siliconix Self-aligned trench MOSFET and method of manufacture
EP2208229A4 (fr) 2007-09-21 2011-03-16 Fairchild Semiconductor Structures à superjonction pour dispositifs de puissance et procédés de fabrication
US9484451B2 (en) 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US7772668B2 (en) * 2007-12-26 2010-08-10 Fairchild Semiconductor Corporation Shielded gate trench FET with multiple channels
JP5494474B2 (ja) * 2008-03-24 2014-05-14 日本電気株式会社 半導体装置及びその製造方法
US20120273916A1 (en) 2011-04-27 2012-11-01 Yedinak Joseph A Superjunction Structures for Power Devices and Methods of Manufacture
TWI435447B (zh) * 2009-01-09 2014-04-21 Niko Semiconductor Co Ltd 功率金氧半導體場效電晶體及其製造方法
US8426275B2 (en) 2009-01-09 2013-04-23 Niko Semiconductor Co., Ltd. Fabrication method of trenched power MOSFET
US7989293B2 (en) * 2009-02-24 2011-08-02 Maxpower Semiconductor, Inc. Trench device structure and fabrication
US9443974B2 (en) 2009-08-27 2016-09-13 Vishay-Siliconix Super junction trench power MOSFET device fabrication
US9431530B2 (en) * 2009-10-20 2016-08-30 Vishay-Siliconix Super-high density trench MOSFET
US10026835B2 (en) * 2009-10-28 2018-07-17 Vishay-Siliconix Field boosted metal-oxide-semiconductor field effect transistor
US8129778B2 (en) * 2009-12-02 2012-03-06 Fairchild Semiconductor Corporation Semiconductor devices and methods for making the same
US20110198689A1 (en) * 2010-02-17 2011-08-18 Suku Kim Semiconductor devices containing trench mosfets with superjunctions
US8432000B2 (en) 2010-06-18 2013-04-30 Fairchild Semiconductor Corporation Trench MOS barrier schottky rectifier with a planar surface using CMP techniques
JP2012204636A (ja) * 2011-03-25 2012-10-22 Toshiba Corp 半導体装置およびその製造方法
US8786010B2 (en) 2011-04-27 2014-07-22 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8836028B2 (en) 2011-04-27 2014-09-16 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8772868B2 (en) 2011-04-27 2014-07-08 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US8673700B2 (en) 2011-04-27 2014-03-18 Fairchild Semiconductor Corporation Superjunction structures for power devices and methods of manufacture
US10164043B2 (en) * 2012-01-11 2018-12-25 Infineon Technologies Ag Semiconductor diode and method for forming a semiconductor diode
US9842911B2 (en) 2012-05-30 2017-12-12 Vishay-Siliconix Adaptive charge balanced edge termination
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
US9887259B2 (en) 2014-06-23 2018-02-06 Vishay-Siliconix Modulated super junction power MOSFET devices
KR102026543B1 (ko) 2014-08-19 2019-09-27 비쉐이-실리코닉스 전자 회로
US9882044B2 (en) 2014-08-19 2018-01-30 Vishay-Siliconix Edge termination for super-junction MOSFETs
DE102014114230B4 (de) * 2014-09-30 2021-10-07 Infineon Technologies Ag Halbleitervorrichtung und Herstellungsverfahren hierfür
US9577073B2 (en) * 2014-12-11 2017-02-21 Infineon Technologies Ag Method of forming a silicon-carbide device with a shielded gate
DE102015208097B4 (de) * 2015-04-30 2022-03-31 Infineon Technologies Ag Herstellen einer Halbleitervorrichtung durch Epitaxie
DE102016109555A1 (de) * 2016-05-24 2017-11-30 Infineon Technologies Austria Ag Leistungshalbleiterbauelement und verfahren zur herstellung eines leistungshalbleiterbauelements
DE102017118352A1 (de) * 2017-08-11 2019-02-14 Infineon Technologies Ag Halbleiterbauelement mit grabenstrukturen und herstellungsverfahren hierfür
JP2019046991A (ja) * 2017-09-04 2019-03-22 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10847617B2 (en) 2017-12-14 2020-11-24 Fuji Electric Co., Ltd. Semiconductor device
JP7442932B2 (ja) * 2020-03-09 2024-03-05 三菱電機株式会社 半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4364072A (en) * 1978-03-17 1982-12-14 Zaidan Hojin Handotai Kenkyu Shinkokai Static induction type semiconductor device with multiple doped layers for potential modification
US4941026A (en) * 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US4903189A (en) * 1988-04-27 1990-02-20 General Electric Company Low noise, high frequency synchronous rectifier
US5072266A (en) * 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
JPH045A (ja) * 1990-04-17 1992-01-06 Takashi Kimura 空気シリンダにおけるピストンロッドの減速制御方法
US5326711A (en) * 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5405794A (en) * 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5688725A (en) * 1994-12-30 1997-11-18 Siliconix Incorporated Method of making a trench mosfet with heavily doped delta layer to provide low on-resistance
US5592005A (en) * 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5637898A (en) * 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5814858A (en) * 1996-03-15 1998-09-29 Siliconix Incorporated Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer
JP3216700B2 (ja) 1996-05-22 2001-10-09 サンケン電気株式会社 半導体発光素子
JP3505039B2 (ja) * 1996-07-12 2004-03-08 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6090716A (en) * 1996-12-17 2000-07-18 Siliconix Incorporated Method of fabricating a field effect transistor
JPH10256550A (ja) * 1997-01-09 1998-09-25 Toshiba Corp 半導体装置
GB9808234D0 (en) * 1998-04-17 1998-06-17 Koninkl Philips Electronics Nv Mnufacture of trench-gate semiconductor devices

Also Published As

Publication number Publication date
US6285060B1 (en) 2001-09-04
ATE518251T1 (de) 2011-08-15
EP1113501A3 (fr) 2004-07-07
EP1113501A2 (fr) 2001-07-04
JP2001210822A (ja) 2001-08-03

Similar Documents

Publication Publication Date Title
EP1113501B1 (fr) MOSFET de puissance à électrode de grille en tranchée
KR100628938B1 (ko) 개선된 고주파 스위칭 특성 및 항복 특성을 갖는 전력용반도체 장치들
EP1368837B1 (fr) Dispositifs a semi-conducteurs a regions de modelage de champ
US6566708B1 (en) Trench-gate field-effect transistors with low gate-drain capacitance and their manufacture
US6849880B1 (en) Power semiconductor device
JP4198469B2 (ja) パワーデバイスとその製造方法
US8466025B2 (en) Semiconductor device structures and related processes
US5917216A (en) Trenched field effect transistor with PN depletion barrier
US6218228B1 (en) DMOS device structure, and related manufacturing process
EP1168455B1 (fr) Element de commutation semiconducteur a puissance
US6359308B1 (en) Cellular trench-gate field-effect transistors
US10211333B2 (en) Scalable SGT structure with improved FOM
US20080246086A1 (en) Semiconductor devices having charge balanced structure
US20080085586A1 (en) Semiconductor device
KR100381845B1 (ko) 트렌치-게이트형파워mosfet
US6919599B2 (en) Short channel trench MOSFET with reduced gate charge
US7253459B2 (en) Semiconductor devices and methods of manufacture thereof
CN116031303B (zh) 超结器件及其制作方法和电子器件
EP4169076A1 (fr) Dispositifs d'alimentation dotés d'une structure de grille hybride
US20230163167A1 (en) Semiconductor device including a trench gate structure

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Free format text: AL;LT;LV;MK;RO;SI

RIC1 Information provided on ipc code assigned before grant

Ipc: 7H 01L 29/78 A

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

AX Request for extension of the european patent

Extension state: AL LT LV MK RO SI

17P Request for examination filed

Effective date: 20041028

AKX Designation fees paid

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

R17C First examination report despatched (corrected)

Effective date: 20061215

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 29/10 20060101ALN20101110BHEP

Ipc: H01L 29/06 20060101ALN20101110BHEP

Ipc: H01L 29/49 20060101ALN20101110BHEP

Ipc: H01L 29/78 20060101AFI20101110BHEP

Ipc: H01L 29/08 20060101ALN20101110BHEP

Ipc: H01L 29/423 20060101ALN20101110BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 60046258

Country of ref document: DE

Effective date: 20110915

REG Reference to a national code

Ref country code: NL

Ref legal event code: VDEP

Effective date: 20110727

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 518251

Country of ref document: AT

Kind code of ref document: T

Effective date: 20110727

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

Ref country code: BE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111128

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111028

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

26N No opposition filed

Effective date: 20120502

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111231

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 60046258

Country of ref document: DE

Effective date: 20120502

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111231

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111231

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111222

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20111107

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20111222

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20110727

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20151229

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20151217

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20151229

Year of fee payment: 16

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151222

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 60046258

Country of ref document: DE

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20161222

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20151222

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20151222

Year of fee payment: 16

PGRI Patent reinstated in contracting state [announced from national office to epo]

Ref country code: IT

Effective date: 20170710

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20170831

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170102

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161222

PGRI Patent reinstated in contracting state [announced from national office to epo]

Ref country code: IT

Effective date: 20170710

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20161222

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20170701