Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B12/00—Dynamic random access memory [DRAM] devices
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  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
  • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
  • H01L2224/10135—Alignment aids
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
  • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
  • H01L2224/10165—Alignment aids
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
  • H01L2224/10—Bump connectors; Manufacturing methods related thereto
  • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
  • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
  • H01L2224/161—Disposition
  • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
  • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
  • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
  • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/8112—Aligning
  • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
  • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
  • H01L2224/81139—Guiding structures on the body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/8112—Aligning
  • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
  • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
  • H01L2224/8114—Guiding structures outside the body
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
  • H01L2224/818—Bonding techniques
  • H01L2224/81801—Soldering or alloying
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01005—Boron [B]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01006—Carbon [C]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01033—Arsenic [As]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01038—Strontium [Sr]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/0104—Zirconium [Zr]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01041—Niobium [Nb]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01056—Barium [Ba]
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01073—Tantalum [Ta]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
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  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/01—Chemical elements
  • H01L2924/01082—Lead [Pb]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19041—Component type being a capacitor
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
  • H01L2924/1901—Structure
  • H01L2924/1904—Component type
  • H01L2924/19043—Component type being a resistor

Definitions

• the invention relates to a memory arrangement which has the following features:
• a transistor arrangement with a plurality of transistors, each of which is connected to a first contact
• capacitor arrangement with a plurality of capacitors, each having a first electrode and a second electrode, between which there is a storage dielectric, the first electrode having a second contact;
• the transistor arrangement and the capacitor arrangement are assembled in such a way that a first main surface of the transistor arrangement and a second main surface of the capacitor arrangement are arranged opposite, a first contact being connected to a second contact in each case;
• the second contacts are protruding in the second main surface.
• Such memory arrangements in which the transistor arrangement and the capacitor arrangement are produced separately from one another and then joined together, are mainly used when ferroelectric substances are to be used as storage dielectrics, since many of the ferroelectric substances which are suitable as storage dielectric are difficult in the manufacturing process can be included in which the transistor arrangement is manufactured.
• a known memory arrangement in which the transistor arrangement and capacitor arrangement are produced separately from one another, is designed in such a way that both the first contacts of the transistor arrangement and the second contacts of the capacitor arrangement are designed to protrude before the transistor arrangement and capacitor arrangement are joined together.
• a check as to whether first contacts and second contacts are connected to one another before the tempering step can only be carried out indirectly in such memory arrangements, for example via markings on the edges of the arrangements. Since this method involves a number of inaccuracies, it may be necessary to make the contact areas of the first and second contacts larger than would be necessary for a conductive connection.
• the aim of the invention is to further develop the memory arrangement mentioned at the outset so that when a transistor arrangement and a capacitor arrangement are put together, the connection of a first contact and a second contact in each case can be ensured in a simple manner, so that, in particular, the above-mentioned adjustment problems do not arise occur more.
• a structure of elevations is arranged in the first main surface, the protruding second contacts engaging between the elevations.
• the memory arrangement described it is possible in a simple manner to adjust the transistor arrangement and the capacitor arrangement so that a first contact comes to rest on a respective second contact, so that the two contacts conduct one another in one heat step can be connected so that one of the transistors is electrically conductively connected to one of the capacitors.
• the two arrangements are adjusted by the engagement of the protruding second contacts between the elevations formed between the first contacts. The adjustment takes place directly and does not require any markings on the edges of the transistor arrangement and the capacitor arrangement. Due to the more precise adjustment possibility that is possible with the memory arrangement described, it is possible to dimension the protruding contacts smaller than in previously known memory arrangements of this type and nevertheless to ensure adequate contacting between the first contact and the second contact.
• the second contacts of the capacitor arrangement are protruding in the second main area and that when the transistor arrangement and the capacitor arrangement are put together, the second contacts engage between bumps which are arranged between the first contacts in the first main area of the transistor arrangement. Since the protruding configuration of the second contacts on the capacitor arrangement and the presence of a corresponding structure from elevations on the transistor arrangement is only of importance for the contacting of transistors of the transistor arrangement with capacitors of the capacitor arrangement, it is obvious that the first contacts of the transistor can be configured protruding and the structure of elevations can be attached to the capacitor arrangement, so that when projecting, the protruding first contacts of the transistor arrangement engage between the elevations formed between the second contacts in the capacitor arrangement.
• the first contacts of the transistor arrangement protrude and that a structure of elevations be provided on the capacitor arrangement, the first contacts engaging when they are joined between the elevations, as a result of which a first contact of the transistor arrangement with a second contact in each case the capacitor arrangement can be connected.
• protruding contact in the following becomes synonymous with a protruding second contact, it being assumed that the structure from bumps is on the transistor arrangement, and for one protruding formed first contact, it is assumed that the structure of bumps is on the capacitor arrangement.
• protruding contact is used synonymously for the first contact, the second contact being protruding and the second contact being used, the first contact being protruding.
• An embodiment of the memory arrangement according to the invention provides that the structure consists of elevations from an insulating layer which has cutouts. From- Savings are dimensioned such that the protruding contacts can intervene between them and can be connected to the mating contact, which is located in the region of the cutouts.
• the edges which result on the insulating layer at the edges of the cutouts are preferably rounded in order to ensure that the protruding contacts engage more easily in the cutouts.
• One embodiment of the invention provides for the recesses to be rectangular, preferably square, while another embodiment provides for the recesses to be circular.
• every second mating contact is located within one of the annular elevations, while the respective other mating contact is surrounded by a number of annular elevations, preferably four.
• the annular elevations are preferably dome-shaped, in particular semicircular in cross section.
• the structure of elevations therefore consists of an electrically insulating material.
• One embodiment of the invention provides for the structure to be formed from elevations made of glass.
• ferroelectrics as memory devices. electronics.
• One embodiment of the invention therefore provides that a ferroelectric is used as the storage dielectric in the capacitors of the capacitor arrangement.
• Suitable materials of this type are, for example, oxidic dielectrics, such as PZT (Pb, Zr) Ti0 3 , BST (Ba, Sr) Ti0 3 , ST SrTi0 3 or SBTN
• a further embodiment of the invention therefore provides to use such oxidic dielectrics as storage dielectrics. Since the ferroelectric properties of such substances are temperature-dependent and the materials mentioned have paraelectric properties above a certain temperature, it is also envisaged to use a storage dielectric with paraelectric properties, the dielectric constant being greater than 10, preferably greater than 100.
• FIG. 1 shows a first embodiment of a memory arrangement according to the invention in cross section
• FIG. 2 shows a second exemplary embodiment of a memory arrangement according to the invention in cross section
• FIG. 3 shows a further exemplary embodiment of a memory arrangement according to the invention in plan view of a transistor arrangement and a capacitor arrangement
• Fig. 4 shows an embodiment of a transistor arrangement in plan view
• Fig. 5 shows another embodiment of a transistor arrangement in plan view.
• FIG. 1 shows a first exemplary embodiment of a memory arrangement 1 according to the invention in cross section, a transistor arrangement 2 and a capacitor arrangement 4 being shown before being joined together in FIG. 1 a, while in FIG 1 are shown.
• the transistor arrangement 2 has a plurality of transistors 8, each of which has a first contact 10, a first contact area 5 of each first contact 10 being arranged in a first main area 3 of the transistor arrangement 2.
• the first main area 3 of the transistor arrangement 2 there is a structure made up of elevations 20 which, in the present exemplary embodiment, are arranged as elevations which are semicircular in cross section between the first contact areas 5.
• the capacitor arrangement 4 has a multiplicity of capacitors 15, each of which has a first electrode 14, a storage dielectric 18 and a second electrode 16, the second electrode 16 being common to a number of capacitors 15 in the present exemplary embodiment.
• the first electrode 14 has a second contact 12 which, in the present exemplary embodiment, is formed in the form of a bulge.
• the protruding second contacts 12 engage in the structure of elevations 20 after the transistor arrangement 2 and capacitor arrangement 4 have been joined together, and a second contact 12 is in each case conductively connected to a first contact 10.
• a tempering step that is necessary to fuse first contacts 10 and second contacts 12, the originally protruding second contacts 12 are deformed, as can be seen from FIG. 1b.
• depressions 9 are in a second main surface 11 of the capacitor arrangement in the present exemplary embodiment 4 provided, in which the structure of elevations 20 of the transistor arrangement 2 engages, as a result of which two adjacent second contacts 12 are more reliably separated from one another.
• FIG. 2 shows a second exemplary embodiment of a memory arrangement according to the invention, a transistor arrangement 2 and a capacitor arrangement 4 being shown before the assembly in FIG. 2a, while the transistor arrangement 2 and the capacitor arrangement 4 are combined to form a memory arrangement 1 in FIG. 2b are shown.
• the first contacts 10 of the transistor arrangement 2 are designed to protrude and the capacitor arrangement 4 has a structure of elevations 20, first electrodes 14 of storage capacitors 15 being arranged between the structure of elevations 20.
• the second electrode 12 described in FIG. 1, which is protruding there, is omitted in the present exemplary embodiment, here the first electrode 14 of the storage capacitor 15 forms both the first electrode 14 and the second contact.
• 2b shows the transistor arrangement 2 and the capacitor arrangement 4 combined to form the memory arrangement 1.
• the protruding first contacts 10 are connected to the first electrode 14 of the storage capacitor 15 after assembly and are slightly deformed by the annealing step during assembly.
• 3 shows an embodiment of the memory arrangement according to the invention in a top view of a capacitor arrangement 4 and a transistor arrangement 2.
• the capacitor arrangement 4 shown in plan view has protruding second contacts 12 which are located in a second main surface 11 of the capacitor arrangement 4.
• the capacitor arrangement 4 shown corresponds to the capacitor arrangement 4 shown in cross section in FIG. 1 a.
• the transistor arrangement shown in FIG. 3 b has a number of first contacts 10, the first contact surfaces 5 of which are arranged in a first main surface 3 of the transistor arrangement 2.
• a structure comprising elevations on the transistor arrangement 2 consists of an insulation layer which has rectangular cutouts 22, the first contact surfaces 5 being arranged in the cutouts 22.
• the cross-section shown in FIG. 1 a results from a section along line AA ′ shown in FIG. 3b.
• FIG. 4 Another embodiment of a transistor arrangement, which has a structure of elevations 20, is shown in FIG. 4.
• the structure of elevations 20 in turn consists of an insulation layer which has cutouts 22, the cutouts 22 being circular in the present exemplary embodiment.
• the first contact areas 5 of the first contacts are located within the cutouts 22 of the insulation layer. If the edges of the insulation layer formed at the edges of the cutouts 22 are rounded off, the cross section shown in FIG. 1 a for the transistor arrangement 2 results from a section along the line BB ′ shown in FIG. 4. Rounding off the edges is useful in order to to facilitate sliding of the protruding second contacts 12 into the recesses 22.
• Another embodiment of a transistor arrangement is shown in plan view in FIG. 5.
• a structure consisting of elevations 20 consists of a number of annular elevations which are arranged next to one another. Every second first contact surface 5 of a first contact 10 is located within one of the annular elevations, while the other first contact surfaces 5 are each surrounded by four annular elevations 24.
• a dome-shaped, preferably semicircular, configuration of the annular elevations 24 in cross-section the cross-section of the transistor arrangement shown in FIG.
• the structures from elevations shown in FIGS. 3b, 4 and 5 do not necessarily have to be arranged on the transistor arrangement, but rather can also be arranged on the capacitor arrangement if the first contact of the transistor arrangement is formed above .
• the first contact or the second contact is in a protruding configuration, there is no need for a contact surface of the other contact to be flat, rather the contact surface, which is located between the structure of elevations, can also be designed to protrude as long as the elevations of the elevations the structure from surveys.

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• Engineering & Computer Science (AREA)
• Computer Hardware Design (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Power Engineering (AREA)
• Semiconductor Memories (AREA)
• Wire Bonding (AREA)
• Semiconductor Integrated Circuits (AREA)

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• 1996
  • 1996-09-30 DE DE19640213A patent/DE19640213C1/de not_active Expired - Fee Related
• 1997
  • 1997-08-07 WO PCT/DE1997/001664 patent/WO1998014996A1/de not_active Application Discontinuation
  • 1997-08-07 EP EP97937429A patent/EP0931337A1/de not_active Withdrawn
  • 1997-08-07 KR KR10-1999-7002690A patent/KR100414237B1/ko not_active Expired - Fee Related
  • 1997-08-07 JP JP51609198A patent/JP3280988B2/ja not_active Expired - Fee Related
  • 1997-08-07 CN CNB971983755A patent/CN1158700C/zh not_active Expired - Fee Related
  • 1997-08-12 IN IN1496CA1997 patent/IN192035B/en unknown
  • 1997-08-13 TW TW086111598A patent/TW369695B/zh not_active IP Right Cessation
• 1999
  • 1999-03-30 US US09/282,041 patent/US6097050A/en not_active Expired - Fee Related

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