EP0931337A1 - Storage assembly with self-aligning non-integrated capacitor arrangement - Google Patents

Storage assembly with self-aligning non-integrated capacitor arrangement

Info

Publication number
EP0931337A1
EP0931337A1 EP97937429A EP97937429A EP0931337A1 EP 0931337 A1 EP0931337 A1 EP 0931337A1 EP 97937429 A EP97937429 A EP 97937429A EP 97937429 A EP97937429 A EP 97937429A EP 0931337 A1 EP0931337 A1 EP 0931337A1
Authority
EP
European Patent Office
Prior art keywords
arrangement
contact
elevations
contacts
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97937429A
Other languages
German (de)
French (fr)
Inventor
Walter Hartner
Günther SCHINDLER
Carlos Mazure-Espejo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP0931337A1 publication Critical patent/EP0931337A1/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01038—Strontium [Sr]
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    • H01L2924/01—Chemical elements
    • H01L2924/0104—Zirconium [Zr]
    • H—ELECTRICITY
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    • H01L2924/01056—Barium [Ba]
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    • H01L2924/01073—Tantalum [Ta]
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/19043—Component type being a resistor

Definitions

  • the invention relates to a memory arrangement which has the following features:
  • a transistor arrangement with a plurality of transistors, each of which is connected to a first contact
  • capacitor arrangement with a plurality of capacitors, each having a first electrode and a second electrode, between which there is a storage dielectric, the first electrode having a second contact;
  • the transistor arrangement and the capacitor arrangement are assembled in such a way that a first main surface of the transistor arrangement and a second main surface of the capacitor arrangement are arranged opposite, a first contact being connected to a second contact in each case;
  • the second contacts are protruding in the second main surface.
  • Such memory arrangements in which the transistor arrangement and the capacitor arrangement are produced separately from one another and then joined together, are mainly used when ferroelectric substances are to be used as storage dielectrics, since many of the ferroelectric substances which are suitable as storage dielectric are difficult in the manufacturing process can be included in which the transistor arrangement is manufactured.
  • a known memory arrangement in which the transistor arrangement and capacitor arrangement are produced separately from one another, is designed in such a way that both the first contacts of the transistor arrangement and the second contacts of the capacitor arrangement are designed to protrude before the transistor arrangement and capacitor arrangement are joined together.
  • a check as to whether first contacts and second contacts are connected to one another before the tempering step can only be carried out indirectly in such memory arrangements, for example via markings on the edges of the arrangements. Since this method involves a number of inaccuracies, it may be necessary to make the contact areas of the first and second contacts larger than would be necessary for a conductive connection.
  • the aim of the invention is to further develop the memory arrangement mentioned at the outset so that when a transistor arrangement and a capacitor arrangement are put together, the connection of a first contact and a second contact in each case can be ensured in a simple manner, so that, in particular, the above-mentioned adjustment problems do not arise occur more.
  • a structure of elevations is arranged in the first main surface, the protruding second contacts engaging between the elevations.
  • the memory arrangement described it is possible in a simple manner to adjust the transistor arrangement and the capacitor arrangement so that a first contact comes to rest on a respective second contact, so that the two contacts conduct one another in one heat step can be connected so that one of the transistors is electrically conductively connected to one of the capacitors.
  • the two arrangements are adjusted by the engagement of the protruding second contacts between the elevations formed between the first contacts. The adjustment takes place directly and does not require any markings on the edges of the transistor arrangement and the capacitor arrangement. Due to the more precise adjustment possibility that is possible with the memory arrangement described, it is possible to dimension the protruding contacts smaller than in previously known memory arrangements of this type and nevertheless to ensure adequate contacting between the first contact and the second contact.
  • the second contacts of the capacitor arrangement are protruding in the second main area and that when the transistor arrangement and the capacitor arrangement are put together, the second contacts engage between bumps which are arranged between the first contacts in the first main area of the transistor arrangement. Since the protruding configuration of the second contacts on the capacitor arrangement and the presence of a corresponding structure from elevations on the transistor arrangement is only of importance for the contacting of transistors of the transistor arrangement with capacitors of the capacitor arrangement, it is obvious that the first contacts of the transistor can be configured protruding and the structure of elevations can be attached to the capacitor arrangement, so that when projecting, the protruding first contacts of the transistor arrangement engage between the elevations formed between the second contacts in the capacitor arrangement.
  • the first contacts of the transistor arrangement protrude and that a structure of elevations be provided on the capacitor arrangement, the first contacts engaging when they are joined between the elevations, as a result of which a first contact of the transistor arrangement with a second contact in each case the capacitor arrangement can be connected.
  • protruding contact in the following becomes synonymous with a protruding second contact, it being assumed that the structure from bumps is on the transistor arrangement, and for one protruding formed first contact, it is assumed that the structure of bumps is on the capacitor arrangement.
  • protruding contact is used synonymously for the first contact, the second contact being protruding and the second contact being used, the first contact being protruding.
  • An embodiment of the memory arrangement according to the invention provides that the structure consists of elevations from an insulating layer which has cutouts. From- Savings are dimensioned such that the protruding contacts can intervene between them and can be connected to the mating contact, which is located in the region of the cutouts.
  • the edges which result on the insulating layer at the edges of the cutouts are preferably rounded in order to ensure that the protruding contacts engage more easily in the cutouts.
  • One embodiment of the invention provides for the recesses to be rectangular, preferably square, while another embodiment provides for the recesses to be circular.
  • every second mating contact is located within one of the annular elevations, while the respective other mating contact is surrounded by a number of annular elevations, preferably four.
  • the annular elevations are preferably dome-shaped, in particular semicircular in cross section.
  • the structure of elevations therefore consists of an electrically insulating material.
  • One embodiment of the invention provides for the structure to be formed from elevations made of glass.
  • ferroelectrics as memory devices. electronics.
  • One embodiment of the invention therefore provides that a ferroelectric is used as the storage dielectric in the capacitors of the capacitor arrangement.
  • Suitable materials of this type are, for example, oxidic dielectrics, such as PZT (Pb, Zr) Ti0 3 , BST (Ba, Sr) Ti0 3 , ST SrTi0 3 or SBTN
  • a further embodiment of the invention therefore provides to use such oxidic dielectrics as storage dielectrics. Since the ferroelectric properties of such substances are temperature-dependent and the materials mentioned have paraelectric properties above a certain temperature, it is also envisaged to use a storage dielectric with paraelectric properties, the dielectric constant being greater than 10, preferably greater than 100.
  • FIG. 1 shows a first embodiment of a memory arrangement according to the invention in cross section
  • FIG. 2 shows a second exemplary embodiment of a memory arrangement according to the invention in cross section
  • FIG. 3 shows a further exemplary embodiment of a memory arrangement according to the invention in plan view of a transistor arrangement and a capacitor arrangement
  • Fig. 4 shows an embodiment of a transistor arrangement in plan view
  • Fig. 5 shows another embodiment of a transistor arrangement in plan view.
  • FIG. 1 shows a first exemplary embodiment of a memory arrangement 1 according to the invention in cross section, a transistor arrangement 2 and a capacitor arrangement 4 being shown before being joined together in FIG. 1 a, while in FIG 1 are shown.
  • the transistor arrangement 2 has a plurality of transistors 8, each of which has a first contact 10, a first contact area 5 of each first contact 10 being arranged in a first main area 3 of the transistor arrangement 2.
  • the first main area 3 of the transistor arrangement 2 there is a structure made up of elevations 20 which, in the present exemplary embodiment, are arranged as elevations which are semicircular in cross section between the first contact areas 5.
  • the capacitor arrangement 4 has a multiplicity of capacitors 15, each of which has a first electrode 14, a storage dielectric 18 and a second electrode 16, the second electrode 16 being common to a number of capacitors 15 in the present exemplary embodiment.
  • the first electrode 14 has a second contact 12 which, in the present exemplary embodiment, is formed in the form of a bulge.
  • the protruding second contacts 12 engage in the structure of elevations 20 after the transistor arrangement 2 and capacitor arrangement 4 have been joined together, and a second contact 12 is in each case conductively connected to a first contact 10.
  • a tempering step that is necessary to fuse first contacts 10 and second contacts 12, the originally protruding second contacts 12 are deformed, as can be seen from FIG. 1b.
  • depressions 9 are in a second main surface 11 of the capacitor arrangement in the present exemplary embodiment 4 provided, in which the structure of elevations 20 of the transistor arrangement 2 engages, as a result of which two adjacent second contacts 12 are more reliably separated from one another.
  • FIG. 2 shows a second exemplary embodiment of a memory arrangement according to the invention, a transistor arrangement 2 and a capacitor arrangement 4 being shown before the assembly in FIG. 2a, while the transistor arrangement 2 and the capacitor arrangement 4 are combined to form a memory arrangement 1 in FIG. 2b are shown.
  • the first contacts 10 of the transistor arrangement 2 are designed to protrude and the capacitor arrangement 4 has a structure of elevations 20, first electrodes 14 of storage capacitors 15 being arranged between the structure of elevations 20.
  • the second electrode 12 described in FIG. 1, which is protruding there, is omitted in the present exemplary embodiment, here the first electrode 14 of the storage capacitor 15 forms both the first electrode 14 and the second contact.
  • 2b shows the transistor arrangement 2 and the capacitor arrangement 4 combined to form the memory arrangement 1.
  • the protruding first contacts 10 are connected to the first electrode 14 of the storage capacitor 15 after assembly and are slightly deformed by the annealing step during assembly.
  • 3 shows an embodiment of the memory arrangement according to the invention in a top view of a capacitor arrangement 4 and a transistor arrangement 2.
  • the capacitor arrangement 4 shown in plan view has protruding second contacts 12 which are located in a second main surface 11 of the capacitor arrangement 4.
  • the capacitor arrangement 4 shown corresponds to the capacitor arrangement 4 shown in cross section in FIG. 1 a.
  • the transistor arrangement shown in FIG. 3 b has a number of first contacts 10, the first contact surfaces 5 of which are arranged in a first main surface 3 of the transistor arrangement 2.
  • a structure comprising elevations on the transistor arrangement 2 consists of an insulation layer which has rectangular cutouts 22, the first contact surfaces 5 being arranged in the cutouts 22.
  • the cross-section shown in FIG. 1 a results from a section along line AA ′ shown in FIG. 3b.
  • FIG. 4 Another embodiment of a transistor arrangement, which has a structure of elevations 20, is shown in FIG. 4.
  • the structure of elevations 20 in turn consists of an insulation layer which has cutouts 22, the cutouts 22 being circular in the present exemplary embodiment.
  • the first contact areas 5 of the first contacts are located within the cutouts 22 of the insulation layer. If the edges of the insulation layer formed at the edges of the cutouts 22 are rounded off, the cross section shown in FIG. 1 a for the transistor arrangement 2 results from a section along the line BB ′ shown in FIG. 4. Rounding off the edges is useful in order to to facilitate sliding of the protruding second contacts 12 into the recesses 22.
  • Another embodiment of a transistor arrangement is shown in plan view in FIG. 5.
  • a structure consisting of elevations 20 consists of a number of annular elevations which are arranged next to one another. Every second first contact surface 5 of a first contact 10 is located within one of the annular elevations, while the other first contact surfaces 5 are each surrounded by four annular elevations 24.
  • a dome-shaped, preferably semicircular, configuration of the annular elevations 24 in cross-section the cross-section of the transistor arrangement shown in FIG.
  • the structures from elevations shown in FIGS. 3b, 4 and 5 do not necessarily have to be arranged on the transistor arrangement, but rather can also be arranged on the capacitor arrangement if the first contact of the transistor arrangement is formed above .
  • the first contact or the second contact is in a protruding configuration, there is no need for a contact surface of the other contact to be flat, rather the contact surface, which is located between the structure of elevations, can also be designed to protrude as long as the elevations of the elevations the structure from surveys.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Storage assembly comprising a capacitor arrangement (4) and a transistor arrangement (2), which are self-aligned and so assembled that in each case a first contact (10) of a transistor (8) belonging to the transistor arrangement (2) is connected to a second contact (12) of a storage capacitor (15) belonging to the capacitor arrangement (4). The second contacts are designed to protrude in order to align both arrangements (2,4) and engage in a structure with elevations (20) when assembled.

Description

Beschreibungdescription
Speicheranordnung mit selbst ustierender nicht integrierter KondensatoranordnungStorage arrangement with self-adjusting non-integrated capacitor arrangement
Die Erfindung betrifft eine Speicheranordnung, die folgende Merkmale aufweist:The invention relates to a memory arrangement which has the following features:
eine Transistoranordnung mit einer Vielzahl Transisto- ren, die mit jeweils einem ersten Kontakt verbunden sind;a transistor arrangement with a plurality of transistors, each of which is connected to a first contact;
eine Kondensatoranordnung mit einer Vielzahl Kondensatoren, die jeweils eine erste Elektrode und eine zweite Elektrode aufweisen, zwischen denen sich ein Speicherdielektrikum befindet, wobei die erste Elektrode einen zweiten Kontakt aufweist;a capacitor arrangement with a plurality of capacitors, each having a first electrode and a second electrode, between which there is a storage dielectric, the first electrode having a second contact;
die Transistoranordnung und die Kondensatoranordnung sind derart zusammengefügt, daß eine erste Hauptfläche der Transistoranordnung und eine zweite Hauptfläche der Kondensatoranordnung gegenüberliegend angeordnet sind, wobei jeweils ein erster Kontakt mit jeweils einem zweiten Kontakt verbunden ist;the transistor arrangement and the capacitor arrangement are assembled in such a way that a first main surface of the transistor arrangement and a second main surface of the capacitor arrangement are arranged opposite, a first contact being connected to a second contact in each case;
die zweiten Kontakte sind hervorstehend in der zweiten Hauptfläche ausgebildet.the second contacts are protruding in the second main surface.
Derartige Speicheranordnungen, bei denen die Transistoranord- nung und die Kondensatoranordnung getrennt voneinander hergestellt und anschließend zusammengefügt werden, finden hauptsächlich Verwendung, wenn ferroelektrische Substanzen als Speicherdielektrika verwendet werden sollen, da viele der ferroelektrischen Substanzen, die als Speicherdielektrikum geeignet sind, nur schwer in den Herstellungsprozeß einbezogen werden können, in dem die Transistoranordnung hergestellt wird. Eine bekannte Speicheranordnung, bei der Transistoranordnung und Kondensatoranordnung getrennt voneinander hergestellt werden, ist derart ausgestaltet, daß sowohl die ersten Kon- takte der Transistoranordnung als auch die zweiten Kontakte der Kondensatoranordnung vor dem Zusammenfügen von Transistoranordnung und Kondensatoranordnung hervorstehend ausgebildet sind. Beim Zusammenfügen derartig ausgestalteter Transistoranordnungen und Kondensatoranordnungen ist darauf zu achten, daß jeweils ein erster Kontakt mit jeweils einem zweiten Kontakt in Verbindung gebracht wird, wobei die beiden Kontakte in einem kurzen Temperschritt miteinander verschmolzen werden und eine dauerhafte leitende Verbindung entsteht.Such memory arrangements, in which the transistor arrangement and the capacitor arrangement are produced separately from one another and then joined together, are mainly used when ferroelectric substances are to be used as storage dielectrics, since many of the ferroelectric substances which are suitable as storage dielectric are difficult in the manufacturing process can be included in which the transistor arrangement is manufactured. A known memory arrangement, in which the transistor arrangement and capacitor arrangement are produced separately from one another, is designed in such a way that both the first contacts of the transistor arrangement and the second contacts of the capacitor arrangement are designed to protrude before the transistor arrangement and capacitor arrangement are joined together. When assembling transistor arrangements and capacitor arrangements of this type, care must be taken that a first contact is connected to a second contact, the two contacts being fused together in a short annealing step and a permanent conductive connection being produced.
Eine Kontrolle, ob erste Kontakte und zweite Kontakte vor dem Temperschritt miteinander in Verbindung stehen, kann bei derartigen Speicheranordnungen nur indirekt, beispielsweise über Markierungen an den Rändern der Anordnungen, erfolgen. Da diese Methode eine Anzahl Ungenauigkeiten in sich birgt, ist es unter Umständen notwendig, die Kontaktflächen von ersten und zweiten Kontakten großflächiger auszuführen als für eine leitende Verbindung notwendig wäre.A check as to whether first contacts and second contacts are connected to one another before the tempering step can only be carried out indirectly in such memory arrangements, for example via markings on the edges of the arrangements. Since this method involves a number of inaccuracies, it may be necessary to make the contact areas of the first and second contacts larger than would be necessary for a conductive connection.
Die Erfindung hat das Ziel, die eingangs genannte Speicheran- Ordnung so weiterzubilden, daß beim Zusammenfügen von Transistoranordnung und Kondensatoranordnung die Verbindung von jeweils einem ersten Kontakt mit jeweils einem zweiten Kontakt auf einfache Art und Weise sichergestellt werden kann, so daß insbesondere oben genannte Justierungsprobleme nicht mehr auftreten.The aim of the invention is to further develop the memory arrangement mentioned at the outset so that when a transistor arrangement and a capacitor arrangement are put together, the connection of a first contact and a second contact in each case can be ensured in a simple manner, so that, in particular, the above-mentioned adjustment problems do not arise occur more.
Dieses Ziel wird für die eingangs genannte Speicheranordnung durch folgendes zusätzliches Merkmal erreicht:This goal is achieved for the storage arrangement mentioned at the outset by the following additional feature:
- in der ersten Hauptfläche ist eine Struktur aus Erhebungen angeordnet, wobei die hervorstehend ausgebildeten zweiten Kontakte zwischen die Erhebungen eingreifen. Bei der beschriebenen Speicheranordnung ist es in einfacher Art und Weise möglich, die Transistoranordnung und die Kondensatoranordnung beim Zusammenfügen so zu justieren, daß je- weils ein erster Kontakt über jeweils einem zweiten Kontakt zum Liegen kommt, so daß die beiden Kontakte in einem Temperschritt leitend miteinander verbunden werden können, so daß jeweils einer der Transistoren mit jeweils einem der Kondensatoren elektrisch leitend verbunden ist. Die Justierung der beiden Anordnungen erfolgt durch das Eingreifen der hervorstehend ausgebildeten zweiten Kontakte zwischen die zwischen den ersten Kontakten ausgebildeten Erhebungen. Die Justierung erfolgt direkt und kommt ohne Markierungen an den Rändern der Transistoranordnung und der Kondensatoranordnung aus. Auf- grund der bei der beschriebenen Speicheranordnung möglichen exakteren Justierungsmöglichkeit ist es möglich, die hervorstehenden Kontakte kleiner zu dimensionieren als bei bisher bekannten derartigen Speicheranordnungen und trotzdem eine ausreichende Kontaktierung zwischen erstem Kontakt und zwei- tem Kontakt zu gewährleisten.a structure of elevations is arranged in the first main surface, the protruding second contacts engaging between the elevations. In the memory arrangement described, it is possible in a simple manner to adjust the transistor arrangement and the capacitor arrangement so that a first contact comes to rest on a respective second contact, so that the two contacts conduct one another in one heat step can be connected so that one of the transistors is electrically conductively connected to one of the capacitors. The two arrangements are adjusted by the engagement of the protruding second contacts between the elevations formed between the first contacts. The adjustment takes place directly and does not require any markings on the edges of the transistor arrangement and the capacitor arrangement. Due to the more precise adjustment possibility that is possible with the memory arrangement described, it is possible to dimension the protruding contacts smaller than in previously known memory arrangements of this type and nevertheless to ensure adequate contacting between the first contact and the second contact.
Weiterbildungen der Erfindung sind Gegenstand der Unteransprüche.Developments of the invention are the subject of the dependent claims.
In der bisherigen Beschreibung wurde angenommen, daß die zweiten Kontakte der Kondensatoranordnung in der zweiten Hauptfläche hervorstehend ausgebildet sind und daß die zweiten Kontakte beim Zusammenfügen der Transistoranordnung und der Kondensatoranordnung zwischen Erhebungen eingreifen, die zwischen den ersten Kontakten in der ersten Hauptfläche der Transistoranordnung angeordnet sind. Da die hervorstehende Ausgestaltung der zweiten Kontakte auf der Kondensatoranordnung und das Vorhandensein einer korrespondierenden Struktur aus Erhebungen auf der Transistoranordnung lediglich für die Kontaktierung von Transistoren der Transistoranordnung mit Kondensatoren der Kondensatoranordnung von Bedeutung ist, ist es offensichtlich, daß ebenso die ersten Kontakte der Transi- storanordnung hervorstehend ausgebildet sein können und die Struktur aus Erhebungen auf der Kondensatoranordnung angebracht sein kann, so daß beim Zusammenfügen die hervorstehenden ersten Kontakte der Transistoranordnung zwischen die zwi- sehen den zweiten Kontakten ausgebildeten Erhebungen in der Kondensatoranordnung eingreifen. In einer zweiten Ausführungsform der Erfindung ist deshalb vorgeschlagen, die ersten Kontakte der Transistoranordnung hervorstehend auszubilden und auf der Kondenεatoranordnung eine Struktur aus Erhebungen vorzusehen, wobei die ersten Kontakte beim Zusammenfügen zwischen die Erhebungen eingreifen, wodurch jeweils ein erster Kontakt der Transistoranordnung mit jeweils einem zweiten Kontakt der Kondensatoranordnung in Verbindung gebracht werden kann .In the description so far, it has been assumed that the second contacts of the capacitor arrangement are protruding in the second main area and that when the transistor arrangement and the capacitor arrangement are put together, the second contacts engage between bumps which are arranged between the first contacts in the first main area of the transistor arrangement. Since the protruding configuration of the second contacts on the capacitor arrangement and the presence of a corresponding structure from elevations on the transistor arrangement is only of importance for the contacting of transistors of the transistor arrangement with capacitors of the capacitor arrangement, it is obvious that the first contacts of the transistor can be configured protruding and the structure of elevations can be attached to the capacitor arrangement, so that when projecting, the protruding first contacts of the transistor arrangement engage between the elevations formed between the second contacts in the capacitor arrangement. In a second embodiment of the invention, it is therefore proposed that the first contacts of the transistor arrangement protrude and that a structure of elevations be provided on the capacitor arrangement, the first contacts engaging when they are joined between the elevations, as a result of which a first contact of the transistor arrangement with a second contact in each case the capacitor arrangement can be connected.
Die im folgenden beschriebenen Ausführungsformen gelten sowohl für hervorstehend ausgebildete zweite Kontakte mit einer auf der Transistoranordnung angeordneten Struktur aus Erhebungen als auch für hervorstehend ausgebildete erste Kontakte mit einer auf der Kondensatoranordnung angeordneten Struktur aus Erhebungen. Da sich die folgenden Ausführungsformen stets auf beide der bereits genannten Ausführungsformen beziehen, wird der Begriff "hervorstehender Kontakt" im folgenden synonym für einen hervorstehend ausgebildeten zweiten Kontakt, wobei angenommen wird, daß die Struktur aus Erhebungen sich auf der Transistoranordnung befindet, und für einen hervorstehend ausgebildeten ersten Kontakt, wobei angenommen wird, daß sich die Struktur aus Erhebungen auf der Kondensatoranordnung befindet, verwendet. Ebenso wird der Begriff "Gegenkontakt" synonym für den ersten Kontakt verwendet, wobei der zweite Kontakt hervorstehend ausgebildet ist und den zweiten Kontakt verwendet, wobei der erste Kontakt hervorstehend ausgebildet ist.The embodiments described below apply both to protruding second contacts with a structure of elevations arranged on the transistor arrangement and to protruding first contacts with a structure arranged on the capacitor arrangement from elevations. Since the following embodiments always relate to both of the previously mentioned embodiments, the term "protruding contact" in the following becomes synonymous with a protruding second contact, it being assumed that the structure from bumps is on the transistor arrangement, and for one protruding formed first contact, it is assumed that the structure of bumps is on the capacitor arrangement. Likewise, the term “mating contact” is used synonymously for the first contact, the second contact being protruding and the second contact being used, the first contact being protruding.
Eine Ausführungsform der Speicheranordnung nach der Erfindung sieht vor, daß die Struktur aus Erhebungen aus einer isolierenden Schicht besteht, die Aussparungen aufweist. Die Aus- sparungen sind derart bemessen, daß die hervorstehenden Kontakte zwischen sie eingreifen können und mit dem Gegenkontakt, der sich im Bereich der Aussparungen befindet, in Verbindung gebracht werden können. Vorzugsweise sind die Kanten, die sich an der isolierenden Schicht an den Rändern der Aussparungen ergeben, abgerundet, um ein leichteres Eingreifen der hervorstehenden Kontakte in die Aussparungen zu gewährleisten.An embodiment of the memory arrangement according to the invention provides that the structure consists of elevations from an insulating layer which has cutouts. From- Savings are dimensioned such that the protruding contacts can intervene between them and can be connected to the mating contact, which is located in the region of the cutouts. The edges which result on the insulating layer at the edges of the cutouts are preferably rounded in order to ensure that the protruding contacts engage more easily in the cutouts.
Eine Ausführungsform der Erfindung sieht vor, die Aussparungen rechteckig, vorzugsweise quadratisch auszubilden, während eine weitere Ausführungsform vorsieht, die Aussparungen kreisförmig auszubilden.One embodiment of the invention provides for the recesses to be rectangular, preferably square, while another embodiment provides for the recesses to be circular.
In einer weiteren Ausführungsform der Erfindung ist vorgesehen, die Struktur aus Erhebungen aus nebeneinander angeordneten ringförmigen Erhebungen zu gestalten. Jeder zweite Gegenkontakt befindet sich bei einer derartigen Ausgestaltung innerhalb einer der ringförmigen Erhebungen, während der je- weils andere Gegenkontakt von einer Anzahl ringförmiger Erhebungen, vorzugsweise vier, umgeben sind. Um ein einfaches Eingreifen der hervorstehenden Kontakte zwischen die ringförmigen Erhebungen zu gewährleisten, sind die ringförmigen Erhebungen vorzugsweise kalottenförmig, im besonderen halb- kreisförmig im Querschnitt.In a further embodiment of the invention, it is provided to design the structure from elevations from annular elevations arranged next to one another. In such a configuration, every second mating contact is located within one of the annular elevations, while the respective other mating contact is surrounded by a number of annular elevations, preferably four. In order to ensure simple engagement of the protruding contacts between the annular elevations, the annular elevations are preferably dome-shaped, in particular semicircular in cross section.
Da nach dem Zusammenfügen von Kondensatoranordnung und Transistoranordnung die hervorstehenden Kontakte an der Struktur aus Erhebungen anliegen können, muß verhindert werden, daß jeweils zwei Kontakte durch die Erhebungen leitend in Verbindung gebracht werden können. Die Struktur aus Erhebungen besteht daher aus einem elektrisch isolierenden Material. Eine Ausführungsform der Erfindung sieht vor, die Struktur aus Erhebungen aus Glas zu bilden.Since, after the capacitor arrangement and transistor arrangement have been put together, the protruding contacts can rest against the structure of elevations, it must be prevented that two contacts can be conductively connected by the elevations. The structure of elevations therefore consists of an electrically insulating material. One embodiment of the invention provides for the structure to be formed from elevations made of glass.
Die beschriebene Speicheranordnung findet insbesondere Anwendung bei der Verwendung von Ferroelektrika als Speicherdie- lektrika. Eine Ausführungsform der Erfindung sieht daher vor, als Speicherdielektrikum in den Kondensatoren der Kondensatoranordnung ein Ferroelektriku zu verwenden. Geeignete derartige Materialien sind beispielsweise oxidische Dielektrika, wie PZT (Pb, Zr)Ti03, BST (Ba,Sr)Ti03, ST SrTi03 oder SBTNThe memory arrangement described is used in particular when using ferroelectrics as memory devices. electronics. One embodiment of the invention therefore provides that a ferroelectric is used as the storage dielectric in the capacitors of the capacitor arrangement. Suitable materials of this type are, for example, oxidic dielectrics, such as PZT (Pb, Zr) Ti0 3 , BST (Ba, Sr) Ti0 3 , ST SrTi0 3 or SBTN
SrBi2 (Ta1_xNbx)2θ9, wobei die Formeln (Pb,Zr)TiC>3 und (Ba,Sr)Ti03 für PbχZr1_χTi03 bzw. BaxSr1_χTi03 stehen.SrBi 2 (Ta 1 _ x Nb x ) 2 θ9, where the formulas (Pb, Zr) TiC> 3 and (Ba, Sr) Ti0 3 for Pb χ Zr 1 _ χ Ti0 3 or Ba x Sr 1 _ χ Ti0 3 stand.
Eine weitere Ausführungsform der Erfindung sieht daher vor, derartige oxidische Dielektrika als Speicherdielektrika zu verwenden. Da die ferroelektrischen Eigenschaften derartiger Substanzen temperaturabhängig sind und die genannten Materialien oberhalb einer bestimmten Temperatur paraelektrische Ei- genschaften aufweisen, ist es ebenso vorgesehen, ein Speicherdielektrikum mit paraelektrischen Eigenschaften zu verwenden, wobei die Dielektrizitätskonstante größer als 10, vorzugsweise größer als 100 ist.A further embodiment of the invention therefore provides to use such oxidic dielectrics as storage dielectrics. Since the ferroelectric properties of such substances are temperature-dependent and the materials mentioned have paraelectric properties above a certain temperature, it is also envisaged to use a storage dielectric with paraelectric properties, the dielectric constant being greater than 10, preferably greater than 100.
Die Erfindung wird nachfolgend im Zusammenhang mit Ausfüh- rungsbeispielen anhand von Figuren näher erläutert. Es zeigen:The invention is explained in more detail below in connection with exemplary embodiments with reference to figures. Show it:
Fig. 1 ein erstes Ausführungsbeispiel einer Speicher- anordnung nach der Erfindung im Querschnitt,1 shows a first embodiment of a memory arrangement according to the invention in cross section,
Fig. 2 ein zweites Ausführungsbeispiel einer Speicheranordnung nach der Erfindung im Querschnitt,2 shows a second exemplary embodiment of a memory arrangement according to the invention in cross section,
Fig. 3 ein weiteres Ausführungsbeispiel einer Speicheranordnung nach der Erfindung in Draufsicht auf eine Transistoranordnung und eine Kondensatoranordnung,3 shows a further exemplary embodiment of a memory arrangement according to the invention in plan view of a transistor arrangement and a capacitor arrangement,
Fig. 4 ein Ausführungsbeispiel einer Transistoranordnung in Draufsicht, und Fig. 5 ein weiteres Ausführungsbeispiel einer Transistoranordnung in Draufsicht.Fig. 4 shows an embodiment of a transistor arrangement in plan view, and Fig. 5 shows another embodiment of a transistor arrangement in plan view.
In den nachfolgenden Figuren bezeichnen, sofern nicht anders angegeben, gleiche Bezugszeichen gleiche Teile mit gleicher Bedeutung .In the following figures, unless otherwise stated, the same reference symbols designate the same parts with the same meaning.
Fig. 1 zeigt ein erstes Ausführungsbeispiel einer Speicheranordnung 1 nach der Erfindung im Querschnitt, wobei in Fig. la eine Transistoranordnung 2 und eine Kondensatoranordnung 4 vor dem Zusammenfügen dargestellt sind, während in Fig. lb die Transistoranordnung 2 und die Kondensatoranordnung 4 zusammengefügt zu der Speicheranordnung 1 dargestellt sind. Wie aus Fig. 1 ersichtlich, weist die Transistoranordnung 2 eine Vielzahl Transistoren 8 auf, die jeweils einen ersten Kontakt 10 besitzen, wobei eine erste Kontaktfläche 5 jedes ersten Kontakts 10 in einer ersten Hauptfläche 3 der Transistoranordnung 2 angeordnet ist. Weiterhin befindet sich in der ersten Hauptfläche 3 der Transistoranordnung 2 eine Struktur aus Erhebungen 20, die im vorliegenden Ausführungsbeispiel als im Querschnitt halbkreisförmige Erhebungen zwischen den ersten Kontaktflächen 5 angeordnet sind.1 shows a first exemplary embodiment of a memory arrangement 1 according to the invention in cross section, a transistor arrangement 2 and a capacitor arrangement 4 being shown before being joined together in FIG. 1 a, while in FIG 1 are shown. 1, the transistor arrangement 2 has a plurality of transistors 8, each of which has a first contact 10, a first contact area 5 of each first contact 10 being arranged in a first main area 3 of the transistor arrangement 2. Furthermore, in the first main area 3 of the transistor arrangement 2 there is a structure made up of elevations 20 which, in the present exemplary embodiment, are arranged as elevations which are semicircular in cross section between the first contact areas 5.
Die Kondensatoranordnung 4 weist eine Vielzahl von Kondensa- toren 15 auf, die jeweils eine erste Elektrode 14, ein Speicherdielektrikum 18 und eine zweite Elektrode 16 aufweisen, wobei die zweite Elektrode 16 im vorliegenden Ausführungsbeispiel einer Anzahl von Kondensatoren 15 gemeinsam ist. Die erste Elektrode 14 weist einen zweiten Kontakt 12 auf,, der im vorliegenden Ausführungsbeispiel hervorstehend in Form einer Beule ausgebildet ist.The capacitor arrangement 4 has a multiplicity of capacitors 15, each of which has a first electrode 14, a storage dielectric 18 and a second electrode 16, the second electrode 16 being common to a number of capacitors 15 in the present exemplary embodiment. The first electrode 14 has a second contact 12 which, in the present exemplary embodiment, is formed in the form of a bulge.
Wie aus Fig. lb ersichtlich, greifen die hervorstehend ausgebildeten zweiten Kontakte 12 nach dem Zusammenfügen von Tran- sistoranordnung 2 und Kondensatoranordnung 4 in die Struktur aus Erhebungen 20 ein und jeweils ein zweiter Kontakt 12 ist mit jeweils einem ersten Kontakt 10 leitend verbunden. Durch einen Temperschritt, der notwendig ist, um erste Kontakte 10 und zweite Kontakte 12 miteinander zu verschmelzen, werden die ursprünglich hervorstehend ausgebildeten zweiten Kontakte 12 deformiert, wie aus Fig. lb ersichtlich. Um zu verhindern, daß leitendes Material, aus dem die zweiten Kontakte 12 bestehen, während des Temperschrittes in Richtung benachbarter Kontakte gedrückt wird und somit eine leitende Verbindung zwischen zwei benachbarten Kontakten herstellt, sind in dem vorliegenden Ausführungsbeispiel Vertiefungen 9 in einer zweiten Hauptfläche 11 der Kondensatoranordnung 4 vorgesehen, in die die Struktur aus Erhebungen 20 der Transistoranordnung 2 eingreift, wodurch zwei benachbarte zweite Kontakte 12 sicherer voneinander getrennt sind.As can be seen from FIG. 1 b, the protruding second contacts 12 engage in the structure of elevations 20 after the transistor arrangement 2 and capacitor arrangement 4 have been joined together, and a second contact 12 is in each case conductively connected to a first contact 10. By a tempering step that is necessary to fuse first contacts 10 and second contacts 12, the originally protruding second contacts 12 are deformed, as can be seen from FIG. 1b. In order to prevent conductive material, from which the second contacts 12 are made, from being pressed in the direction of adjacent contacts during the tempering step and thus to establish a conductive connection between two adjacent contacts, depressions 9 are in a second main surface 11 of the capacitor arrangement in the present exemplary embodiment 4 provided, in which the structure of elevations 20 of the transistor arrangement 2 engages, as a result of which two adjacent second contacts 12 are more reliably separated from one another.
In Fig. 2 ist ein zweites Ausführungsbeispiel einer Speicheranordnung nach der Erfindung dargestellt, wobei in Fig. 2a eine Transistoranordnung 2 und eine Kondensatoranordnung 4 vor dem Zusammenfügen dargestellt sind, während in Fig. 2b die Transistoranordnung 2 und die Kondensatoranordnung 4 zu einer Speicheranordnung 1 zusammengefügt dargestellt sind. In dem dargestellten Ausführungsbeispiel sind die ersten Kontakte 10 der Transistoranordnung 2 hervorstehend ausgebildet und die Kondensatoranordnung 4 weist eine Struktur aus Erhebungen 20 auf, wobei erste Elektroden 14 von Speicherkondensatoren 15 zwischen der Struktur aus Erhebungen 20 angeordnet sind. Die in Fig. 1 beschriebene zweite Elektrode 12, die dort hervorstehend ausgebildet ist, ist in dem vorliegenden Ausführungsbeispiel weggelassen, hier bildet die erste Elektrode 14 des Speicherkondensators 15 sowohl die erste Elektrode 14 als auch den zweiten Kontakt. In Fig. 2b sind die Transistoranordnung 2 und die Kondensatoranordnung 4 zu der Speicheranordnung 1 zusammengefügt dargestellt. Die hervorstehend ausgebildeten ersten Kontakte 10 sind nach dem Zusammenfügen mit der ersten Elektrode 14 des Speicherkondensators 15 verbunden und durch den Temperschritt beim Zusammenfügen leicht deformiert . In Fig. 3 ist eine Ausführungsform der Speicheranordnung nach der Erfindung in Draufsicht auf eine Kondensatoranordnung 4 und eine Transistoranordnung 2 dargestellt. Die in Draufsicht dargestellte Kondensatoranordnung 4 weist hervorstehend aus- gebildete zweite Kontakte 12 auf, die sich in einer zweiten Hauptfläche 11 der Kondensatoranordnung 4 befinden. Die dargestellte Kondensatoranordnung 4 korrespondiert zu der in Fig. la im Querschnitt dargestellten Kondensatoranordnung 4. Die in Fig. 3b dargestellte Transistoranordnung weist eine Anzahl erster Kontakte 10 auf, deren erste Kontaktflächen 5 in einer ersten Hauptfläche 3 der Transistoranordnung 2 angeordnet sind. Eine auf der Transistoranordnung 2 befindliche Struktur aus Erhebungen besteht in dem dargestellten Ausführungsbeispiel aus einer Isolationsschicht, die rechteckförmi- ge Aussparungen 22 aufweist, wobei die ersten Kontaktflächen 5 in den Aussparungen 22 angeordnet sind. Im Falle einer Ab- rundung der Kanten, die am Rand der Aussparungen an der Isolationsschicht entstehen, ergibt sich bei einem Schnitt entlang der in Fig. 3b eingezeichneten Linie A-A' der in Fig. la dargestellte Querschnitt.FIG. 2 shows a second exemplary embodiment of a memory arrangement according to the invention, a transistor arrangement 2 and a capacitor arrangement 4 being shown before the assembly in FIG. 2a, while the transistor arrangement 2 and the capacitor arrangement 4 are combined to form a memory arrangement 1 in FIG. 2b are shown. In the exemplary embodiment shown, the first contacts 10 of the transistor arrangement 2 are designed to protrude and the capacitor arrangement 4 has a structure of elevations 20, first electrodes 14 of storage capacitors 15 being arranged between the structure of elevations 20. The second electrode 12 described in FIG. 1, which is protruding there, is omitted in the present exemplary embodiment, here the first electrode 14 of the storage capacitor 15 forms both the first electrode 14 and the second contact. 2b shows the transistor arrangement 2 and the capacitor arrangement 4 combined to form the memory arrangement 1. The protruding first contacts 10 are connected to the first electrode 14 of the storage capacitor 15 after assembly and are slightly deformed by the annealing step during assembly. 3 shows an embodiment of the memory arrangement according to the invention in a top view of a capacitor arrangement 4 and a transistor arrangement 2. The capacitor arrangement 4 shown in plan view has protruding second contacts 12 which are located in a second main surface 11 of the capacitor arrangement 4. The capacitor arrangement 4 shown corresponds to the capacitor arrangement 4 shown in cross section in FIG. 1 a. The transistor arrangement shown in FIG. 3 b has a number of first contacts 10, the first contact surfaces 5 of which are arranged in a first main surface 3 of the transistor arrangement 2. In the exemplary embodiment shown, a structure comprising elevations on the transistor arrangement 2 consists of an insulation layer which has rectangular cutouts 22, the first contact surfaces 5 being arranged in the cutouts 22. In the case of a rounding of the edges that arise at the edge of the cutouts on the insulation layer, the cross-section shown in FIG. 1 a results from a section along line AA ′ shown in FIG. 3b.
Eine weitere Ausführungsform einer Transistoranordnung, die eine Struktur aus Erhebungen 20 aufweist, ist in Fig. 4 dargestellt. Die Struktur aus Erhebungen 20 besteht wiederum aus einer Isolationsschicht, die Aussparungen 22 aufweist, wobei die Aussparungen 22 im vorliegenden Ausführungsbeispiel kreisförmig ausgestaltet sind. Die ersten Kontaktflächen 5 der ersten Kontakte befinden sich innerhalb der Aussparungen 22 der Isolationsschicht. Im Falle einer Abrundung der an den Rändern der Aussparungen 22 entstehenden Kanten der Isolationsschicht ergibt sich bei einem Schnitt entlang der in Fig. 4 dargestellten Linie BB' der in Fig. la dargestellte Querschnitt für die Transistoranordnung 2. Eine Abrundung der Kanten ist sinnvoll, um ein Hineingleiten der hervorstehend ausgebildeten zweiten Kontakte 12 in die Aussparungen 22 zu erleichtern. Ein weiteres Ausführungsbeispiel einer Transistoranordnung ist in Fig. 5 in Draufsicht dargestellt. Eine Struktur aus Erhebungen 20 besteht im vorliegenden Ausführungsbeispiel aus einer Anzahl ringförmiger Erhebungen, die nebeneinander ange- ordnet sind. Jede zweite erste Kontaktfläche 5 eines ersten Kontakts 10 befindet sich innerhalb einer der ringförmigen Erhebungen, während die anderen ersten Kontaktflächen 5 von jeweils vier ringförmigen Erhebungen 24 umgeben sind. Bei einer kalottenförmigen, vorzugsweise halbkreisförmigen Ausge- staltung der ringförmigen Erhebungen 24 im Querschnitt ergibt sich bei einem Schnitt entlang der in Fig. 5 eingezeichneten Linie C-C die in Fig. la dargestellte Transistoranordnung im Querschnitt .Another embodiment of a transistor arrangement, which has a structure of elevations 20, is shown in FIG. 4. The structure of elevations 20 in turn consists of an insulation layer which has cutouts 22, the cutouts 22 being circular in the present exemplary embodiment. The first contact areas 5 of the first contacts are located within the cutouts 22 of the insulation layer. If the edges of the insulation layer formed at the edges of the cutouts 22 are rounded off, the cross section shown in FIG. 1 a for the transistor arrangement 2 results from a section along the line BB ′ shown in FIG. 4. Rounding off the edges is useful in order to to facilitate sliding of the protruding second contacts 12 into the recesses 22. Another embodiment of a transistor arrangement is shown in plan view in FIG. 5. In the present exemplary embodiment, a structure consisting of elevations 20 consists of a number of annular elevations which are arranged next to one another. Every second first contact surface 5 of a first contact 10 is located within one of the annular elevations, while the other first contact surfaces 5 are each surrounded by four annular elevations 24. In the case of a dome-shaped, preferably semicircular, configuration of the annular elevations 24 in cross-section, the cross-section of the transistor arrangement shown in FIG.
Es sei darauf hingewiesen, daß die in den Fig. 3b, 4 und 5 dargestellten Strukturen aus Erhebungen nicht notwendigerweise auf der Transistoranordnung angeordnet sein müssen, vielmehr können sie ebenso auf der Kondensatoranordnung angeordnet sein, wenn der erste Kontakt der Transistoranordnung her- vorstehend ausgebildet ist. Ebenso besteht keine Notwendigkeit, bei hervorstehender Ausgestaltung des ersten Kontakts oder des zweiten Kontakts eine Kontaktfläche des jeweils anderen Kontakts eben auszuführen, vielmehr kann auch die Kontaktfläche, die sich zwischen der Struktur aus Erhebungen be- findet, hervorstehend ausgebildet sein, solange deren Höhe die Erhebungen der Struktur aus Erhebungen nicht übersteigt. It should be pointed out that the structures from elevations shown in FIGS. 3b, 4 and 5 do not necessarily have to be arranged on the transistor arrangement, but rather can also be arranged on the capacitor arrangement if the first contact of the transistor arrangement is formed above . Likewise, if the first contact or the second contact is in a protruding configuration, there is no need for a contact surface of the other contact to be flat, rather the contact surface, which is located between the structure of elevations, can also be designed to protrude as long as the elevations of the elevations the structure from surveys.
BezugszeichenlisteReference list
1 Speicheranordnung 2 Transistoranordnung1 memory arrangement 2 transistor arrangement
3 erste Hauptfläche3 first main surface
4 Kondensatoranordnung4 capacitor arrangement
5 erste Kontaktfläche 8 Transistor 9 Vertiefung5 first contact surface 8 transistor 9 recess
10 erster Kontakt10 first contact
11 zweite Hauptfläche11 second main area
12 zweiter Kontakt 14 erste Elektrode 15 Kondensator12 second contact 14 first electrode 15 capacitor
16 zweite Elektrode16 second electrode
18 Speicherdielektrikum18 storage dielectric
20 Struktur aus Erhebungen 22 Aussparungen 24 ringförmige Erhebung 20 structure from elevations 22 recesses 24 ring-shaped elevation

Claims

Patentansprüche claims
1. Speicheranordnung, die folgende Merkmale aufweist:1. Storage arrangement which has the following features:
1.1. eine Transistoranordnung (2) mit einer Vielzahl Transistoren (8) , die mit jeweils einem ersten Kontakt (10) verbunden sind;1.1. a transistor arrangement (2) having a plurality of transistors (8) which are each connected to a first contact (10);
1.2. eine Kondensatoranordnung (4) mit einer Vielzahl Kondensatoren (15) , die jeweils eine erste Elektrode (14) und eine zweite Elektrode (16) aufweisen, zwischen denen sich ein Speicherdielektrikum (18) befindet, wobei die erste Elektrode (14) einen zweiten Kontakt (12) aufweist.1.2. a capacitor arrangement (4) with a plurality of capacitors (15), each having a first electrode (14) and a second electrode (16), between which there is a storage dielectric (18), the first electrode (14) having a second contact (12).
1.3. die Transistoranordnung (2) und die Kondensatoranordnung (4) sind derart zusammengefügt, daß eine erste Hauptfläche (3) der Transistoranordnung (2) und eine zweite Hauptfläche (11) der Kondensatoranordnung (4) gegenüberliegend angeordnet sind, wobei jeweils ein erster Kontakt (10) mit jeweils einem zweitem Kontakt (12) ver- bunden ist;1.3. the transistor arrangement (2) and the capacitor arrangement (4) are joined together in such a way that a first main surface (3) of the transistor arrangement (2) and a second main surface (11) of the capacitor arrangement (4) are arranged opposite one another, a first contact (10 ) is connected to a second contact (12);
1.4. die zweiten Kontakte (12) sind hervorstehend aus der zweiten Hauptfläche (11) ausgebildet;1.4. the second contacts (12) protrude from the second main surface (11);
gekennzeichnet durch das weitere Merkmal:characterized by the further characteristic:
1.5. in der ersten Hauptfläche ist eine Struktur aus Erhebungen (20) angeordnet, wobei die hervorstehend ausgebildeten zweiten Kontakte (12) zwischen die Erhebungen eingreifen.1.5. A structure of elevations (20) is arranged in the first main surface, the protruding second contacts (12) engaging between the elevations.
2. Speicheranordnung, die folgende Merkmale aufweist: 2. Storage arrangement which has the following features:
2.1. eine Transistoranordnung (2) mit einer Vielzahl Transistoren (8) , die mit jeweils einem ersten Kontakt (10) verbunden sind;2.1. a transistor arrangement (2) having a plurality of transistors (8) which are each connected to a first contact (10);
2.2. eine Kondensatoranordnung (4) mit einer Vielzahl Kondensatoren (15) , die jeweils eine erste Elektrode (14) und eine zweite Elektrode (16) aufweisen, zwischen denen sich ein Speicherdielektrikum (18) befindet, wobei die erste Elektrode (14) einen zweiten Kontakt (12) aufweist.2.2. a capacitor arrangement (4) with a plurality of capacitors (15), each having a first electrode (14) and a second electrode (16), between which there is a storage dielectric (18), the first electrode (14) having a second contact (12).
2.3. die Transistoranordnung (2) und die Kondensatoranordnung (4) sind derart zusammengefügt, daß eine erste Hauptfläche (3) der Transistoranordnung (2) und eine zweite Hauptfläche (11) der Kondensatoranordnung (4) gegenüberliegend angeordnet sind, wobei jeweils ein erster Kontakt (10) mit jeweils einem zweitem Kontakt (12) ver- bunden ist;2.3. the transistor arrangement (2) and the capacitor arrangement (4) are joined together in such a way that a first main surface (3) of the transistor arrangement (2) and a second main surface (11) of the capacitor arrangement (4) are arranged opposite one another, a first contact (10 ) is connected to a second contact (12);
2.4. die ersten Kontakte (10) sind hervorstehend aus der ersten Hauptfläche (3) ausgebildet;2.4. the first contacts (10) protrude from the first main surface (3);
gekennzeichnet durch das weitere Merkmal:characterized by the further characteristic:
2.5. in der zweiten Hauptfläche (11) ist eine Struktur aus Erhebungen (20) angeordnet, wobei die hervorstehend ausgebildeten ersten Kontakte (10) zwi- sehen die Erhebungen eingreifen.2.5. a structure of elevations (20) is arranged in the second main surface (11), the protruding first contacts (10) engaging between the elevations.
3. Speicheranordnung nach einem der Ansprüche 1 oder 2, dadurch gekennzeichnet, daß die Struktur aus Erhebungen (20) aus einer isolierenden Schicht besteht, die Ausspa- rungen (22) aufweist. 3. Storage arrangement according to one of claims 1 or 2, characterized in that the structure of elevations (20) consists of an insulating layer which has recesses (22).
4. Speicheranordnung nach Anspruch 3, dadurch gekennzeichnet, daß die Aussparungen (22) kreisförmig ausgebildet sind.4. Storage arrangement according to claim 3, characterized in that the recesses (22) are circular.
5. Speicheranordnung nach Anspruch 3, dadurch gekennzeichnet, daß die Aussparungen (22) rechteckig, insbesondere quadratisch ausgebildet sind.5. Storage arrangement according to claim 3, characterized in that the recesses (22) are rectangular, in particular square.
6. Speicheranordnung nach einem der Ansprüche 1 oder 2, da- durch gekennzeichnet, daß die Struktur aus Erhebungen6. Storage arrangement according to one of claims 1 or 2, characterized in that the structure of surveys
(20) aus nebeneinander angeordneten ringförmigen Erhebungen besteht .(20) consists of juxtaposed annular elevations.
7. Speicheranordnung nach einem der vorangehenden Ansprü- ehe, dadurch gekennzeichnet, daß die Struktur aus Erhebungen (20) aus Isolationsmaterial besteht.7. Storage arrangement according to one of the preceding claims, characterized in that the structure consists of elevations (20) made of insulation material.
8. Speicheranordnung nach Anspruch 7, dadurch gekennzeichnet, daß das Isolationsmaterial Glas ist.8. Storage arrangement according to claim 7, characterized in that the insulation material is glass.
9. Speicheranordnung nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, daß das Speicherdielektrikum (18) ein Ferroelektrikum ist.9. Storage arrangement according to one of the preceding claims, characterized in that the storage dielectric (18) is a ferroelectric.
10. Speicheranordnung nach einem der vorangehenden Ansprüche, dadurch gekennzeichnet, daß das Speicherdielektrikum (18) eine Dielektrizitätskonstante größer als 10 aufweist .10. Memory arrangement according to one of the preceding claims, characterized in that the storage dielectric (18) has a dielectric constant greater than 10.
11. Speicheranordnung nach einem der Ansprüche 9 oder 10, dadurch gekennzeichnet, daß das Speicherdielektrikum (18) ein oxidisches Dielektrikum ist.11. Memory arrangement according to one of claims 9 or 10, characterized in that the storage dielectric (18) is an oxidic dielectric.
12. Speicheranordnung nach Anspruch 11, dadurch gekennzeich- net, daß das Speicherdielektrikum (18) PZT(Pb, Zr) Ti03 ,12. Memory arrangement according to claim 11, characterized in that the storage dielectric (18) PZT (Pb, Zr) Ti0 3 ,
BST(Ba, Sr)Ti03, ST SrTi03 oder SBTN SrBi2 (Ta1--χNbχ) 0g ist. BST (Ba, Sr) Ti0 3 , ST SrTi0 3 or SBTN SrBi 2 (Ta 1 - χ Nb χ ) 0g.
EP97937429A 1996-09-30 1997-08-07 Storage assembly with self-aligning non-integrated capacitor arrangement Withdrawn EP0931337A1 (en)

Applications Claiming Priority (3)

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DE19640213A DE19640213C1 (en) 1996-09-30 1996-09-30 Memory arrangement with self-adjusting, non-integrated capacitor arrangement
DE19640213 1996-09-30
PCT/DE1997/001664 WO1998014996A1 (en) 1996-09-30 1997-08-07 Storage assembly with self-aligning non-integrated capacitor arrangement

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