EP0899788A2 - Dispositif semiconducteur et procédé avec une surface plane améliorée - Google Patents

Dispositif semiconducteur et procédé avec une surface plane améliorée Download PDF

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Publication number
EP0899788A2
EP0899788A2 EP98116236A EP98116236A EP0899788A2 EP 0899788 A2 EP0899788 A2 EP 0899788A2 EP 98116236 A EP98116236 A EP 98116236A EP 98116236 A EP98116236 A EP 98116236A EP 0899788 A2 EP0899788 A2 EP 0899788A2
Authority
EP
European Patent Office
Prior art keywords
insulating film
interlayer insulating
formation region
element formation
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98116236A
Other languages
German (de)
English (en)
Other versions
EP0899788A3 (fr
Inventor
Naoto Yamada
Naoyuki Yoshida
Atsushi Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of EP0899788A2 publication Critical patent/EP0899788A2/fr
Publication of EP0899788A3 publication Critical patent/EP0899788A3/fr
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a structure and a manufacturing method of a semiconductor device such as a dynamic RAM.
  • a SOG (SPIN on GLASS) film is used.
  • the SOG film is formed by introducing SOG material on the surface of the semiconductor wafer which is spinning, and flowing the SOG material from the central to the peripheral of the semiconductor wafer.
  • multi-layer interlayer insulating film structure is used.
  • a metal wiring layer is used for preventing the edge of the multi-layer insulating films from peeling off each other.
  • Figs. 4A to 4H are sectional views for explaining a manufacturing process of a semiconductor device of the related art.
  • a field oxidation film 2 is formed in a chip region 13 to create an element formation region on a surface of a substrate 1, for example, by selective oxidation (LOCOS: Local Oxidation of Silicon).
  • LOCOS Local Oxidation of Silicon
  • a scribe line region 12 is a cutting region necessary for dicing a semiconductor wafer into separate chips.
  • interlayer insulating films, 3 to 5 are sequentially formed by, for example, a CVD method so as to cover the entire of the substrate 1 on which the field oxidation film 2 has been formed. Although omitted here, wiring layers and element films are formed between the respective interlayer insulating films. Thereafter, as shown in Fig. 4E, a resist is applied to the entire surface, and is exposed and developed to form a resist pattern 6. Then the respective interlayer insulating films, 3 to 5, are etched by using the resist pattern 6 as a mask to form an opening portion 7 and patterned interlayer insulating films, 3' to 5'.
  • metal material for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method, and it is selectively etched by RIE (reactive Ion Etching) to form a metal wiring layer 8.
  • the metal wiring layer 8 is formed to prevent peeling of end portions of the respective interlayer insulating films 3' to 5'.
  • an insulating film 9, for example, an oxide film is formed by, for example, a CVD method, so as to cover the entire surface.
  • a SOG (SPIN on GLASS) film 10 is formed on the entire surface by a spin coating method.
  • an arrow Z denotes a flow of, for example, silicon dioxide at the time when the SOG film is formed by applying silicon dioxide (such a flow of silicon dioxide will be hereinafter referred to as flow of SOG).
  • flow of SOG silicon dioxide
  • the SOG film 10 is formed by applying a spin coating.
  • the surrounding portion where the metal wiring layer has been formed is higher, the flow of SOG is blocked by the stepped portion.
  • a thick SOG is accumulated in the vicinity of a corner portion of the metal wiring layer (which means that, for example, when silicon dioxide is applied to form a SOG film, thick silicon dioxide is accumulated), so that a SOG puddle 100 is formed.
  • the SOG puddle 100 forms, since the SOG paddle 100 is not completely etched back and remains when the surface is flattened, flattening damaged may occur. Moreover, when the SOG puddle 100 can not be completely etched back and some bump remains, for the through hole forming a contact hole 200, for making contact with a wiring layer just below that portion, can not be opened completely and the contact can not be properly made to the wiring layer.
  • a semiconductor device of the present invention comprises: a semiconductor substrate; an interlayer insulating film formed over the semiconductor substrate; and a metal wiring layer formed so as to cover an end portion of the interlayer insulating film over the periphery of an element formation region of the semiconductor substrate, the metal wiring layer having at least one cut portion formed at the vicinity of a corner of the element formation region.
  • a semiconductor device of the present invention comprises: a semiconductor substrate having at least a recess located in the vicinity of a corner of an element formation region; a first interlayer insulating film formed over the element formation region of the semiconductor substrate; a second interlayer insulating film formed to cover from the first interlayer insulating film over the element formation region to the semiconductor substrate exposed by the recess; and a metal wiring layer covering an end portion of the second interlayer insulating film, the metal wiring layer having an end portion formed on the interlayer insulating film in the recess.
  • a method of manufacturing a semiconductor device of the present invention comprises the steps of:
  • a method of manufacturing a semiconductor device of the present invention comprises the steps of:
  • the SOG flows out through the cut portion to the scribe line region.
  • the SOG does not excessively accumulate in the vicinity of the corner portion of the metal wiring layer.
  • the metal wiring layer has an end portion formed on the interlayer insulating film in the recess portion, since the stepped portion of the metal wiring layer is lessened by the recess portion, for example, when the SOG film is formed by spin coating, it becomes possible for the SOG to flow out to the scribe line region. Thus, it is possible to eliminate the SOG from being blocked by a stepped portion of the metal wiring layer.
  • Figs. 1A to 1C illustrate a semiconductor device of a first embodiment of the present invention.
  • the basic manufacturing process of this semiconductor device is the same as the manufacturing process shown in Figs. 4A to 4I, when a metal wiring layer 8 is formed for preventing the end portion of interlayer insulating films 3 to 5 from peeling off, cut portions 14a and 14b are formed in the vicinity of a corner portion of the metal wiring layer 8 as shown in Fig. 1A.
  • the cut portions 14a and 14b are formed in such a manner that metal material, for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method, and when it is selectively etched by RIE to form the metal wiring layer 8, places which become the cut portions 14a and 14b are also etched at the same time.
  • metal material for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method, and when it is selectively etched by RIE to form the metal wiring layer 8, places which become the cut portions 14a and 14b are also etched at the same time.
  • SOG is applied by spin coating.
  • the SOG flows out to the scribe line region 12 through the cut portions 14a and 14b.
  • the cut portions 14a and 14b have size enough to flow out material of the SOG film through the cut portions 14a and 14b to flatten the SOG film 10 efficiently.
  • the cut portions 14a and 14b make it possible to eliminate excessive accumulation of SOG in the vicinity of the corner portion of the metal wiring layer 8.
  • a flat SOG film 10 is formed as shown in Figs. 1B and 1C.
  • the flat SOG film can be formed, there is no problem properly forming an opened contact hole (through hole) in the vicinity of the corner portion of the metal wiring layer 8.
  • the number of cut portions is not limited, so long as it is possible to flow the SOG out to the side of the scribe line region so that the SOG does not thickly accumulate.
  • the number of the cut portions may be one.
  • it could be merely a drain hole in the metal by layer.
  • Fig. 2 shows a second embodiment of a semiconductor device of the present invention.
  • a cut portion is directly provided at the corner of the metal wiring layer 8.
  • the SOG can therefore be effectively flown out to the scribe line region so that the SOG film can be made more flat.
  • Metal material for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method and it is then selectively etched by RIE to form the metal wiring layer 8. At that time, the corner of the metal wiring layer 8 is simultaneously etched to form a cut portion 14' for flowing the SOG out to the side of a scribe line region.
  • Figs. 3A to 3I show a third embodiment of a semiconductor device of the present invention.
  • a field oxidation film 22 for element separation is formed by selective oxidation (LOCOS) in the chip region 33 of the surface of a substrate 21.
  • LOCS selective oxidation
  • a scribe line region 32 is a cutting region necessary for dicing the wafer into separate chips.
  • an interlayer insulating film 23 is formed so as to cover the entire surface of the substrate 21 by, for example, a CVD method.
  • a resist is applied to the entire surface of the substrate, and is exposed and developed to form a resist pattern 26.
  • the interlayer insulating film 23 and the field oxidation film 22 are etched to form an opening portion 27 recess (cavity) in the substrate and to form patterned interlayer insulating film 23' and patterned field oxidation film 22'.
  • a silicide layer for example, including tungsten, is deposited by, for example, a sputtering method, and this layer is selectively etched by RIE to form a conductive layer 31 so as to cover the end portions of the patterned interlayer insulating film 23' and the patterned field oxidation film 22'.
  • the conductive layer 31 performs the function of preventing peeling off of the end portions of films 22' and 23'.
  • interlayer insulating films 24 and 25 are sequentially formed so as to cover the entire surface of the substrate by, for example, a CVD method. Although omitted here, a wiring layer and an element electrode are formed between the respective interlayer insulating films 23 to 25.
  • a resist is applied to the entire surface, and is exposed and developed to form a resist pattern 26'.
  • the resist pattern 26' as a mask, the respective interlayer insulating films 24 and 25 are etched to form an opening portion 27' and to form patterned interlayer insulating films 24' and 25'.
  • metal material for example, aluminum (Al) is deposited on the entire surface by, for example, a sputtering method, and selectively etched by the RIE to form a metal wiring layer 28 for preventing peeling off the end portions of the respective patterned interlayer insulating films 24' and 25'.
  • an insulating film 29 is formed so as to cover the entire surface of the substrate by, for example, a CVD method.
  • an SOG film 30 is formed on the entire surface by a spin coating method.
  • an arrow Z indicates the flow of SOG by the spin coating.
  • surface flattening is carried out by etch-back.
  • a contact hole 40 is formed to expose the surface of a conductive film (not shown), which is located between the layers 24' and 25', and is used as an element electrode.
  • a contact hole located at a portion in the chip region except the corner of the chip region, for example, center portion of the chip region, can be formed to expose the surface of a conductive film, which is located between the layers 24' and 25', and is used as element electrode.
  • Both contact holes are formed by the same forming condition. It should be noted that, regarding the embodiments 1 and 2 of the present invention, such a contact hole as mentioned above can also be formed at the corner portion of the chip region such that a contact hole having substantially the same depth as the contact formed at center portion of the chip region is formed.
  • this embodiment since this embodiment has the structure that the recess portion is formed by etching the field oxidation film 22 until the substrate 21 is exposed and the end portions of the interlayer insulating films 24' and 25' are formed near to the place where the recess portion has been formed, a stepped portion of the metal wiring layer 28, formed at the end portions of the interlayer insulating films 24' and 25', becomes less as a result of the recess portion. That is, compared with the first and second embodiment, the edge potion of the metal wiring layer 28 is not formed on the interlayer insulating films 24' and 25' over the films 22' and 23' but on the interlayer insulating films 24' and 25' on the surface of the semiconductor substrate 21 exposed by the recess.
  • the difference between the top surface height of the edge of the metal wiring layer 28 and the top surface height of the interlayer insulating film 29 formed over the film 22 becomes small enough to flow SOG by the spin coating without preventing SOG from flowing by the edge of the metal wiring layer 28.
  • the end portions of the interlayer insulating films 24' and 25' are covered with the metal wiring layer 28.
  • the metal wiring layers 31 and 28 are formed so as not to overlap with each other. As compared with the case where the end portions of a plurality of interlayer insulating films are covered with one metal wiring layer, a stepped portion of the metal wiring layer becomes less because the stepped portion of the metal wiring layer 28 becomes less by the removed interlayer insulating film 23'.
  • the film thickness of the conductive layer 31 can be made thin because the layer 31 only holds the layers 22' and 23'. The stepped portion thereof therefore becomes small. Thus, an SOG puddle due to the stepped portion of the conductive layer 31 does not occur.
  • a flat interlayer insulating film can be formed by a BPSG film in place of the SOG.
  • the BPSG film does not produce a puddle such as the SOG puddle. That is, the BPSG film is flatten by heat treatment.
  • Such silicon film or polycrystalline silicon films which electrically connects between one of those films and a conductive film in the chip region do not cause short circuit even though the BPSG film is used.
  • the metal wiring layer 28 is made by Al rather than a refractory metal, the tendency to form short circuit electrical connects between the metal wiring layer 28 and a conductive film used as a portion of a semiconductor element in the chip region is rare even though the BPSG film is used because the metal wiring layer 28 is far enough from the conductive film.
  • the conductive layer 31 is formed so as to cover the end portions of the interlayer insulating film 23 and the field oxidation film 22, the invention is not limited to this.
  • the conductive layer is arranged so as to cover only the end portion of the field oxidation film 22, or the end portions of a plurality of interlayer insulating films.
  • the recess portion formed by etching the field oxidation film 22 until the substrate 21 is exposed may be formed over the entire periphery of a portion on the surface of the substrate where the end of the interlayer insulating film is covered with the metal wiring layer, or may be formed at a part of the periphery. In any cases, the above described effect can be obtained. However, in the case where the recess portion is formed on a part of the periphery, like the cut formation position as described in the first and second embodiments, it is desirable to provide it at the corner portion of the metal wiring layer.
  • the invention results in a semiconductor device having a flat surface and high reliability can be provided.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
EP98116236A 1997-08-29 1998-08-27 Dispositif semiconducteur et procédé avec une surface plane améliorée Withdrawn EP0899788A3 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP234385/97 1997-08-29
JP23438597 1997-08-29
JP23438597A JP3156765B2 (ja) 1997-08-29 1997-08-29 半導体装置、および半導体装置の製造方法

Publications (2)

Publication Number Publication Date
EP0899788A2 true EP0899788A2 (fr) 1999-03-03
EP0899788A3 EP0899788A3 (fr) 2000-09-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP98116236A Withdrawn EP0899788A3 (fr) 1997-08-29 1998-08-27 Dispositif semiconducteur et procédé avec une surface plane améliorée

Country Status (5)

Country Link
US (1) US6538301B1 (fr)
EP (1) EP0899788A3 (fr)
JP (1) JP3156765B2 (fr)
KR (1) KR100304753B1 (fr)
TW (1) TW399232B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4742407B2 (ja) * 2000-07-17 2011-08-10 ソニー株式会社 半導体装置とその製造方法
US20030173648A1 (en) * 2002-03-16 2003-09-18 Sniegowski Jeffry Joseph Multi-die chip and method for making the same
JP3989761B2 (ja) 2002-04-09 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
US7038239B2 (en) 2002-04-09 2006-05-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and display device using the same
JP3989763B2 (ja) 2002-04-15 2007-10-10 株式会社半導体エネルギー研究所 半導体表示装置
US7411215B2 (en) * 2002-04-15 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Display device and method of fabricating the same
US7242021B2 (en) * 2002-04-23 2007-07-10 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and display element using semiconductor device
TWI272556B (en) 2002-05-13 2007-02-01 Semiconductor Energy Lab Display device
TWI263339B (en) 2002-05-15 2006-10-01 Semiconductor Energy Lab Light emitting device and method for manufacturing the same
US7256421B2 (en) 2002-05-17 2007-08-14 Semiconductor Energy Laboratory, Co., Ltd. Display device having a structure for preventing the deterioration of a light emitting device
JP2004296905A (ja) * 2003-03-27 2004-10-21 Toshiba Corp 半導体装置
KR100604903B1 (ko) * 2004-09-30 2006-07-28 삼성전자주식회사 단차피복성을 향상시킨 반도체 웨이퍼 및 그 제조방법
JP4302720B2 (ja) * 2006-06-28 2009-07-29 株式会社沖データ 半導体装置、ｌｅｄヘッド及び画像形成装置
KR101757781B1 (ko) 2015-04-17 2017-07-14 김진영 지속 방출형 약제가 함침된 방역 및 방제용 항균 부직포 시트
US20180190549A1 (en) * 2016-12-30 2018-07-05 John Jude O'Donnell Semiconductor wafer with scribe line conductor and associated method

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JPS6018934A (ja) * 1983-07-13 1985-01-31 Hitachi Micro Comput Eng Ltd 半導体装置
JPH03116946A (ja) * 1989-09-29 1991-05-17 Fujitsu Ltd 半導体装置の製造方法
JPH03270007A (ja) * 1990-03-19 1991-12-02 Fujitsu Ltd 半導体装置の製造方法
JPH0541450A (ja) * 1991-08-06 1993-02-19 Sony Corp 半導体ウエハ
JPH06260554A (ja) * 1993-03-08 1994-09-16 Seiko Epson Corp 半導体装置
JPH0714806A (ja) * 1993-06-15 1995-01-17 Nec Yamaguchi Ltd 半導体集積回路装置
EP0874398A2 (fr) * 1997-04-21 1998-10-28 Nec Corporation Circuit intégré semi-conducteur

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JPH065715A (ja) * 1992-06-18 1994-01-14 Sony Corp 配線層の形成方法
JP3158749B2 (ja) * 1992-12-16 2001-04-23 ヤマハ株式会社 半導体装置
JP2894165B2 (ja) * 1993-07-24 1999-05-24 ヤマハ株式会社 半導体装置
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JP2940432B2 (ja) 1995-04-27 1999-08-25 ヤマハ株式会社 半導体装置とその製造方法
JP3697776B2 (ja) 1996-04-30 2005-09-21 ヤマハ株式会社 半導体装置とその製造方法
TW325576B (en) * 1996-12-12 1998-01-21 Winbond Electronics Corp The manufacturing methods for die seal

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6018934A (ja) * 1983-07-13 1985-01-31 Hitachi Micro Comput Eng Ltd 半導体装置
JPH03116946A (ja) * 1989-09-29 1991-05-17 Fujitsu Ltd 半導体装置の製造方法
JPH03270007A (ja) * 1990-03-19 1991-12-02 Fujitsu Ltd 半導体装置の製造方法
JPH0541450A (ja) * 1991-08-06 1993-02-19 Sony Corp 半導体ウエハ
JPH06260554A (ja) * 1993-03-08 1994-09-16 Seiko Epson Corp 半導体装置
JPH0714806A (ja) * 1993-06-15 1995-01-17 Nec Yamaguchi Ltd 半導体集積回路装置
EP0874398A2 (fr) * 1997-04-21 1998-10-28 Nec Corporation Circuit intégré semi-conducteur

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Also Published As

Publication number Publication date
US6538301B1 (en) 2003-03-25
KR100304753B1 (ko) 2001-11-30
JPH1174347A (ja) 1999-03-16
EP0899788A3 (fr) 2000-09-13
JP3156765B2 (ja) 2001-04-16
TW399232B (en) 2000-07-21
KR19990024021A (ko) 1999-03-25

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