EP0812114A1 - Detecteur d'image a semi-conducteurs, procede d'actionnement de celui-ci, dispositif pour camera a semi-conducteurs et camera a semi-conducteurs - Google Patents

Detecteur d'image a semi-conducteurs, procede d'actionnement de celui-ci, dispositif pour camera a semi-conducteurs et camera a semi-conducteurs Download PDF

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Publication number
EP0812114A1
EP0812114A1 EP96941828A EP96941828A EP0812114A1 EP 0812114 A1 EP0812114 A1 EP 0812114A1 EP 96941828 A EP96941828 A EP 96941828A EP 96941828 A EP96941828 A EP 96941828A EP 0812114 A1 EP0812114 A1 EP 0812114A1
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Prior art keywords
signal
transfer pulses
horizontal
group
pixels
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Granted
Application number
EP96941828A
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German (de)
English (en)
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EP0812114A4 (fr
EP0812114B1 (fr
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Tomio-Sony Corporation Ishigami
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Sony Corp
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Sony Corp
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Publication of EP0812114A4 publication Critical patent/EP0812114A4/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14806—Structural or functional details thereof
    • H01L27/14812—Special geometry or disposition of pixel-elements, address lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/148—Charge coupled imagers
    • H01L27/14868—CCD or CID colour imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H04N23/84—Camera processing pipelines; Components thereof for processing colour signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
    • H04N25/13—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
    • H04N25/134—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements based on three different wavelength filter elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N2209/00—Details of colour television systems
    • H04N2209/04—Picture signal generators
    • H04N2209/041—Picture signal generators using solid-state devices
    • H04N2209/048—Picture signal generators using solid-state devices having several pick-up sensors
    • H04N2209/049—Picture signal generators using solid-state devices having several pick-up sensors having three pick-up sensors

Definitions

  • the present invention relates to a solid-state imaging device which includes a charge transfer unit comprising a CCD, for example, for producing an image output signal based on all-pixel reading principles or noninterlaced principles, the solid-state imaging device being capable of selectively producing an output image signal based on noninterlaced principles, a method of driving the solid-state imaging device for such a charge transfer process, a camera device incorporating the solid-state imaging device, and a camera system for storing an image signal based on the noninterlaced principles (hereinafter referred to as a "noninterlaced signal”) from the camera device into an external memory and displaying a noninterlaced signal from the camera device on a monitor screen.
  • a charge transfer unit comprising a CCD
  • the solid-state imaging device being capable of selectively producing an output image signal based on noninterlaced principles
  • a method of driving the solid-state imaging device for such a charge transfer process a camera device incorporating the solid-state imaging device, and a camera system for storing
  • camera devices for imaging and displaying subjects on monitor devices have solid-state imaging devices for producing an output image signal based on interlaced principles because the monitor devices usually employ interlaced principles such as NTSC or the like.
  • an CCD image sensor of the interline transfer type has an imaging unit 103 comprising a matrix of photodetectors 101 for photoelectrically converting incident light into electric charges depending on the amount of the incident light and a number of vertical shift registers 102 shared by columns of photodetectors 101 and arranged along rows of photodetectors 101.
  • the image sensor also has a horizontal shift register 104 shared by the vertical shift registers 102.
  • the horizontal shift register 104 has a final stage connected to an output unit 105 which has a charge-to-voltage converter comprising a floating-diffusion device or a floating-gate device and an output amplifier for amplifying an output signal from the charge-to-voltage converter.
  • first and second lines and third and fourth lines are mixed with each other in the vertical shift registers 102, and transferred to the horizontal shift register 104.
  • second and third lines and fourth and fifth lines are mixed with each other in the vertical shift registers 102, and transferred to the horizontal shift register 104.
  • FIG. 2 One proposed image sensor for reading all pixels has a vertical transfer unit comprising a 3-layer, 3-phase CCD as shown in FIG. 2 of the accompanying drawings. Those parts shown in FIG. 2 which are identical to those shown in FIG. 1 are denoted by identical reference numerals, and will not be described below.
  • a signal charge "e” is transferred to and stored in a potential well formed beneath a second vertical transfer electrode 111b at a time t1.
  • a potential well is formed beneath a first vertical transfer electrode 111a.
  • the signal charge "e” after it is read is transferred to and stored in the potential wells that are consecutively formed beneath the first and second vertical transfer electrodes 111a, 111b.
  • a potential well is formed beneath a third vertical transfer electrode 111c.
  • the signal charge "e” is transferred to and stored in the potential wells that are consecutively formed beneath the first and third vertical transfer electrodes 111a, 111c.
  • the signal charge "e” that has been stored in the second vertical transfer electrode 111b in the previous stage is transferred to the second vertical transfer electrode 111b in the next stage.
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 are applied respectively to the vertical transfer electrodes 11a ⁇ 111c, independently transferring the signal charges "e" of all the pixels successively in the vertical direction.
  • imaged information is displayed on a monitor device to determine an image angle.
  • a monitor device for use with such a solid-state imaging device should preferably be of a noninterlaced type.
  • an imaging signal of one frame is stored in a memory (frame memory), and thereafter an interlaced signal is outputted.
  • the signal charges of the pixels are supplied in each line to the horizontal shift register, so that signal charges of an nth line, for example, are transferred to and stored in the horizontal shift register.
  • the horizontal transfer pulses are supplied to the horizontal shift register to shift the signal charges in the horizontal shift register by pixels corresponding to a horizontal shift of the color filters. Consequently, the repetitive pattern of colors of signal charges in a range corresponding to the imaging unit and the repetitive pattern of colors of signal charges of an (n + 1)th line stored in a final stage, for example, of the imaging unit, out of the signal charges of the nth line stored in the horizontal shift register, become the same as each other.
  • the group of first transfer pulses is supplied from the first timing generating circuit to the solid-state imaging device in a horizontal blanking period, causing the solid-state imaging device to output a noninterlaced signal.
  • the group of second transfer pulses is supplied from the second timing generating circuit to the solid-state imaging device in a horizontal blanking period, causing the solid-state imaging device to output an interlaced signal. Therefore, the camera device which incorporates an all-pixel reading image sensor or an image sensor for outputting a noninterlaced signal is capable of selectively outputting an interlaced signal without the use of a frame memory or the like as an external circuit.
  • the camera device comprises a solid-state imaging device having an imaging unit comprising a matrix of photodetectors as pixels for photoelectrically converting incident light from a subject into signal charges depending on the amount of the incident light, and color filters arranged on the imaging unit in a predetermined pattern corresponding to the pixels, a first timing generating circuit for generating a group of first transfer pulses for transferring signals charges stored in the respective pixels in a horizontal blanking period in each line to a horizontal shift register, based on a reference clock signal, a second timing generating circuit for generating a group of second transfer pulses for transferring signals charges stored in the respective pixels in the horizontal blanking period in each two lines to the horizontal shift register, based on the reference clock signal, and selecting means for selecting the group of second transfer pulses as a group of transfer pulses to be supplied to the solid-state imaging device in normal operation, and selecting the group of first transfer pulses as a group of transfer pulses to be supplied to the solid-state imaging device based on an interrupt signal from an external shutter control key.
  • the external memory device has a memory for storing an imaging signal of at least one frame which is outputted from the solid-state imaging device, and the display device is arranged to convert the imaging signal outputted from the solid-state imaging device into a video signal and displaying the video signal on a screen.
  • the photodetectors as the pixels photoelectrically convert incident light from a subject into signal charges depending on the amount of the incident light. Thereafter, in a horizontal blanking period, the signal charges stored in the photodetectors are successively transferred to the horizontal shift register.
  • the group of second transfer pulses from the second timing generating circuit is selected by the selecting means, and supplied to the solid-state imaging device.
  • the solid-state imaging device based on the group of second transfer pulses supplied from the second timing generating circuit through the selecting means, the signal charges stored in the pixels are successively transferred in each line to the horizontal shift register, and the solidstate imaging device outputs a noninterlaced imaging signal.
  • the solid-state imaging device outputs an interlaced imaging signal having odd- and even-numbered fields.
  • an image sensor has an imaging unit 3 comprising a matrix of photodetectors 1 for photoelectrically converting incident light into electric charges depending on the amount of the incident light and a number of vertical shift registers 2 shared by columns of photodetectors 1 and arranged along rows of photodetectors 1.
  • the image sensor also has a horizontal shift register 4 disposed adjacent to the imaging unit 3 and shared by the vertical shift registers 2.
  • the p-type well region 22 is formed on a surface of the n-type silicon substrate 21, and the n-type impurity-diffused region 23 which constitutes the photodetector 1 is formed in a position shallower than the well region 22.
  • the image sensor thus constructed functions as a so-called electronic shutter.
  • a potential barrier (overflow barrier) in the p-type well region 22 is lowered, allowing a charge (in this case, electrons) stored in the photodetector 1 to flow over the overflow barrier vertically, i.e., drain to the silicon substrate 21. Therefore, a period from the time when the shutter pulse is finally applied to the time when the charge is read serves as a virtual exposure period thereby to prevent a drawback such as an afterimage lag or the like.
  • the n-type impurity-diffused region 23 and the p-type well region 22 jointly form a pn junction serving as a photodiode.
  • the n-type impurity-diffused region 23 and the readout gate 28 jointly form a pn junction serving as a photodiode.
  • the n-type impurity-diffused region 23 and the channel stopper region 25 jointly form a pn junction serving as a photodiode.
  • the n-type impurity-diffused region 23 and the p-type hole storage region 26 jointly form a pn junction serving as a photodiode.
  • the image sensor includes a three-layer gate insulating film 29 comprising an SiO2 film, an Si3N4 film, and an SiO2 film, for example, and disposed on the transfer channel region 24, the channel stopper region 25, and the readout gate 28, and three transfer electrodes (only a representative transfer electrode 30 as a first polycrystalline silicon layer is shown in FIG. 6) as first through third polycrystalline silicon layers are disposed on the gate insulating film 29.
  • the transfer channel region 24, the channel stopper region 25, and the readout gate 28 jointly serve as the vertical shift register 2.
  • a planarization film, color filters, and a micro condensing lens on the protective film 34 are omitted from illustration for the sake of brevity.
  • a process of reading signal charges from the image sensor particularly, a process of transferring signal charges vertically after the signal charges have been read into the vertical shift registers 2, will be described below with reference to timing charts and diagrams shown in FIGS. 8 through 12.
  • the signal charge "e” that has been stored in the second vertical transfer electrode 41b in the previous stage is transferred to the second vertical transfer electrode 41b in the next stage.
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 are applied respectively to the vertical transfer electrodes 41a ⁇ 41c, independently transferring the signal charges "e” of all the pixels successively in the vertical direction.
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 that are supplied to the vertical transfer electrodes 41a ⁇ 41c have two signal configurations.
  • the first signal configuration as shown in FIG. 10
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 shown in FIG. 8 are outputted only once in a horizontal blanking period.
  • the second signal configuration as shown in FIG. 11, the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 shown in FIG. 8 are outputted twice in a horizontal blanking period.
  • the first and second horizontal transfer pulses ⁇ H1, ⁇ H2 are outputted, two pulses each, after the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 are outputted in a first cycle.
  • the signal charges of two pixels stored in the horizontal shift register 4 are transferred (shifted) to the output unit 5.
  • a process of transferring the signal charges according to the second signal configuration will specifically be described below with reference to FIGS. 11 and 12. Since the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 in the first cycle are supplied to the imaging unit 3, the signal charges of the pixels are transferred independently of each other in each line to the horizontal shift register 4 at a time t11 in FIG. 11. As shown in FIG. 12A, signal charges of an nth line, for example, are transferred to and stored in the horizontal shift register 4.
  • "R” represents a signal charge of a red pixel
  • "B” a signal charge of a blue pixel
  • G a signal charge of a green pixel.
  • the color filters used in the image sensor are of the G-stripe R/B grid coding pattern as shown in FIG. 7. It can be seen that when the color filters along the odd-numbered line are spatially shifted two pixels toward the output unit 5, the repetitive pattern of the colors along the odd-numbered line becomes the same as the repetitive pattern of the colors along the even-numbered line.
  • the output unit 5 outputs an R signal, a G signal, a B signal, and a G signal in the order named, making it possible to generate a color signal to produce a video signal in a subsequent signal processing stage. Accordingly, it is possible to output a field image with half as many as scanning lines in the vertical direction by employing the image sensor driving system according to the second signal configuration.
  • signal charges from the first and second lines are mixed with each other in horizontal shift register 4.
  • signal charges from the second and third lines are mixed with each other in horizontal shift register 4.
  • the output terminal 9 of the output unit 3 outputs an interlaced imaging signal S having odd- and even-numbered fields.
  • a transfer pulse supply circuit system for supplying various transfer pulses to the image sensor according to the embodiment will be described with reference to FIG. 13.
  • the transfer pulse supply circuit system, an image sensor 51, and an imaging lens 52 serve as main components of a camera device according to an embodiment of the present invention.
  • the transfer pulse supply circuit system further has, in addition to the above circuits, a shutter pulse reference signal generating circuit 60 for generating a reference signal Ps to produce an electronic shutter pulse in synchronism with a horizontal blanking period, and a substrate application signal generating circuit 61 for generating a shutter pulse based on the reference signal Ps from the shutter pulse reference signal generating circuit 60, the reference clock signal Pc, and a shutter control signal Ss from the system controller 58, and generating a substrate application signal Vs by adding the shutter pulse to a substrate potential.
  • a shutter pulse reference signal generating circuit 60 for generating a reference signal Ps to produce an electronic shutter pulse in synchronism with a horizontal blanking period
  • a substrate application signal generating circuit 61 for generating a shutter pulse based on the reference signal Ps from the shutter pulse reference signal generating circuit 60, the reference clock signal Pc, and a shutter control signal Ss from the system controller 58, and generating a substrate application signal Vs by adding the shutter pulse to a substrate potential
  • control keys on a control panel 63 external to the camera device through an interface circuit 62. While the control keys include many various control keys, only an NIL control key 64A for indicating a noninterlaced signal and an IL control key 64B for indicating an interlaced signal are illustrated in FIG. 13.
  • the first switching circuit 59A selects the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 from the first vertical timing generating circuit 54A.
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 are supplied through the vertical drive circuit 56 to the image sensor 51.
  • the image sensor 51 now outputs a noninterlaced signal SNIL.
  • an interrupt signal S2 produced by the IL control key 64B is supplied through the interface circuit 62 to the system controller 58.
  • the system controller 58 outputs a low-level switching control signal Ssw.
  • the first through third vertical transfer pulses ⁇ V1 ⁇ ⁇ V3 having the first signal configuration from the first vertical timing generating circuit 54A are supplied to the image sensor 51 in a horizontal blanking period, whereupon the image sensor 51 outputs a noninterlaced signal SNIL.
  • FIG. 14 An electronic camera system according to an embodiment of the present invention to which the above camera device is applied will be described below with reference to FIG. 14. Those parts of the camera system which are identical to those of the camera device shown in FIG. 13 are denoted by identical reference characters, and will not be described below.
  • the camera system has, in addition to a camera device 71 of the above structure, an external memory device 72, a display device 73, and a switching means 74.
  • the switching means 74 is incorporated in the camera device 71, for example.
  • the system controller 58 of the camera device 71 incorporated in the camera system differs partly from the system controller of the camera device shown in FIG. 13 in that it normally outputs a low-level switching control signal Ssw, and changes the level of the switching control signal Ssw to a high level when a shutter control key 75 of the control panel 63 is operated.
  • the external memory device 72 has a memory for storing at least a noninterlaced imaging signal SNIL of one frame which is outputted from the image sensor 51 of the camera device 71.
  • an A/D converter 75 for converting an imaging signal SNIL outputted from the image sensor 51 into digital imaging data DNIL
  • an image processing circuit 79 for adding a horizontal synchronizing signal, etc. to the imaging data DNIL from the A/D converter 75 and converting the imaging data DNIL into data for various image display modes, and outputting the data as image data VNIL.
  • a sampling process in the A/D converter 75 and an image data converting process in the image processing circuit 79 are carried out under timing control by a memory controller 76, for example.
  • the display device 73 comprises an image processing circuit 77 for converting an interlaced imaging signal SIL outputted from the image sensor 51 of the camera device 71 into a video signal, and a monitor 78 for displaying the video signal from the image processing circuit 77 on a screen thereof.
  • the image processing circuit 77 effects gamma correction and aperture correction on the imaging signal SIL and adding a horizontal synchronizing signal to the imaging signal SIL for thereby converting the imaging signal SIL into the video signal.
  • the movable contact 74c when the switching control signal Ssw is of a low level, the movable contact 74c is shifted to supply the interlaced signal SIL outputted from the image sensor 51 to the display device 73, and when the switching control signal Ssw is of a high level, the movable contact 74c is shifted to supply the noninterlaced signal SNIL outputted from the image sensor 51 to the A/D converter 75.
  • an interrupt signal produced by the shutter control key 65 is supplied through the interface circuit 62 to the system controller 58.
  • the system controller 58 outputs a high-level switching control signal Ssw.
  • the camera device has basically been described as comprising a single-panel camera device.
  • the camera device may comprise a two-panel camera device having two image sensors (first and second image sensors 51A, 51B).
  • first and second image sensors 51A, 51B are denoted by identical reference numerals.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Color Television Image Signal Generators (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
EP96941828A 1995-12-21 1996-12-11 Detecteur d'image a semi-conducteurs, procede d'actionnement de celui-ci, dispositif pour camera a semi-conducteurs et camera a semi-conducteurs Expired - Lifetime EP0812114B1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP33364495 1995-12-21
JP33364495A JP3511772B2 (ja) 1995-12-21 1995-12-21 固体撮像素子、固体撮像素子の駆動方法、カメラ装置及びカメラシステム
JP333644/95 1995-12-21
PCT/JP1996/003609 WO1997023999A1 (fr) 1995-12-21 1996-12-11 Detecteur d'image a semi-conducteurs, procede d'actionnement de celui-ci, dispositif pour camera a semi-conducteurs et camera a semi-conducteurs

Publications (3)

Publication Number Publication Date
EP0812114A1 true EP0812114A1 (fr) 1997-12-10
EP0812114A4 EP0812114A4 (fr) 2001-05-09
EP0812114B1 EP0812114B1 (fr) 2003-03-26

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EP96941828A Expired - Lifetime EP0812114B1 (fr) 1995-12-21 1996-12-11 Detecteur d'image a semi-conducteurs, procede d'actionnement de celui-ci, dispositif pour camera a semi-conducteurs et camera a semi-conducteurs

Country Status (10)

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US (1) US6198507B1 (fr)
EP (1) EP0812114B1 (fr)
JP (1) JP3511772B2 (fr)
KR (1) KR19980702357A (fr)
CN (1) CN1104804C (fr)
BR (1) BR9607044A (fr)
CA (1) CA2213250A1 (fr)
DE (1) DE69626970T2 (fr)
RU (1) RU2182405C2 (fr)
WO (1) WO1997023999A1 (fr)

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US7701476B2 (en) 2002-09-13 2010-04-20 Samsung Electronics Co., Ltd. Four color arrangements of emitters for subpixel rendering
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US7728802B2 (en) 2000-07-28 2010-06-01 Samsung Electronics Co., Ltd. Arrangements of color pixels for full color imaging devices with simplified addressing
US7755649B2 (en) 2001-05-09 2010-07-13 Samsung Electronics Co., Ltd. Methods and systems for sub-pixel rendering with gamma adjustment
US7755652B2 (en) 2002-01-07 2010-07-13 Samsung Electronics Co., Ltd. Color flat panel display sub-pixel rendering and driver configuration for sub-pixel arrangements with split sub-pixels
US7864194B2 (en) 2003-03-04 2011-01-04 Samsung Electronics Co., Ltd. Systems and methods for motion adaptive filtering
US7969456B2 (en) 2001-05-09 2011-06-28 Samsung Electronics Co., Ltd. Methods and systems for sub-pixel rendering with adaptive filtering
US8022969B2 (en) 2001-05-09 2011-09-20 Samsung Electronics Co., Ltd. Rotatable display with sub-pixel rendering
US8134583B2 (en) 2002-01-07 2012-03-13 Samsung Electronics Co., Ltd. To color flat panel display sub-pixel arrangements and layouts for sub-pixel rendering with split blue sub-pixels
US8144094B2 (en) 2003-06-06 2012-03-27 Samsung Electronics Co., Ltd. Liquid crystal display backplane layouts and addressing for non-standard subpixel arrangements
US8378947B2 (en) 2003-03-04 2013-02-19 Samsung Display Co., Ltd. Systems and methods for temporal subpixel rendering of image data
US8405692B2 (en) 2001-12-14 2013-03-26 Samsung Display Co., Ltd. Color flat panel display arrangements and layouts with reduced blue luminance well visibility

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JPH11234569A (ja) * 1998-02-13 1999-08-27 Sony Corp 固体撮像装置の駆動方法及び固体撮像素子、並びにカメラ
JP4140077B2 (ja) * 1998-02-18 2008-08-27 ソニー株式会社 固体撮像素子の駆動方法及び固体撮像素子、並びにカメラ
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JP4171137B2 (ja) * 1999-06-08 2008-10-22 富士フイルム株式会社 固体撮像装置及びその制御方法
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JP4342095B2 (ja) * 1999-10-07 2009-10-14 富士フイルム株式会社 電荷転送装置、それを用いた固体撮像装置及びその制御方法
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DE69626970T2 (de) 2003-11-27
EP0812114A4 (fr) 2001-05-09
CA2213250A1 (fr) 1997-07-03
EP0812114B1 (fr) 2003-03-26
WO1997023999A1 (fr) 1997-07-03
KR19980702357A (ko) 1998-07-15
CN1176037A (zh) 1998-03-11
JP3511772B2 (ja) 2004-03-29
DE69626970D1 (de) 2003-04-30
BR9607044A (pt) 1997-12-30
RU2182405C2 (ru) 2002-05-10
JPH09182091A (ja) 1997-07-11
CN1104804C (zh) 2003-04-02

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