EP0767969A1 - Preparation de substrats semi-conducteurs - Google Patents
Preparation de substrats semi-conducteursInfo
- Publication number
- EP0767969A1 EP0767969A1 EP95923462A EP95923462A EP0767969A1 EP 0767969 A1 EP0767969 A1 EP 0767969A1 EP 95923462 A EP95923462 A EP 95923462A EP 95923462 A EP95923462 A EP 95923462A EP 0767969 A1 EP0767969 A1 EP 0767969A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- substrate
- buffer layer
- doped
- iron
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000002360 preparation method Methods 0.000 title abstract description 11
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims abstract description 44
- 239000012535 impurity Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims description 43
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 claims description 34
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical group [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims description 25
- 238000000137 annealing Methods 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 18
- 229910000073 phosphorus hydride Inorganic materials 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 10
- 229910052742 iron Inorganic materials 0.000 claims description 10
- 230000008569 process Effects 0.000 claims description 9
- FAIAAWCVCHQXDN-UHFFFAOYSA-N phosphorus trichloride Chemical compound ClP(Cl)Cl FAIAAWCVCHQXDN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052804 chromium Inorganic materials 0.000 claims description 2
- 239000011651 chromium Substances 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000005693 optoelectronics Effects 0.000 claims description 2
- 230000007935 neutral effect Effects 0.000 claims 1
- 238000009825 accumulation Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 48
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 17
- 125000004429 atom Chemical group 0.000 description 12
- 239000007789 gas Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 239000002019 doping agent Substances 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 125000004437 phosphorous atom Chemical group 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- 238000005389 semiconductor device fabrication Methods 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- RWSOTUBLDIXVET-UHFFFAOYSA-N Dihydrogen sulfide Chemical compound S RWSOTUBLDIXVET-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- MODGUXHMLLXODK-UHFFFAOYSA-N [Br].CO Chemical compound [Br].CO MODGUXHMLLXODK-UHFFFAOYSA-N 0.000 description 1
- 239000003570 air Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000875 corresponding effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- KTWOOEGAPBSYNW-UHFFFAOYSA-N ferrocene Chemical compound [Fe+2].C=1C=C[CH-]C=1.C=1C=C[CH-]C=1 KTWOOEGAPBSYNW-UHFFFAOYSA-N 0.000 description 1
- -1 hydride group Chemical group 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 125000002496 methyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000009419 refurbishment Methods 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02505—Layer structure consisting of more than two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02392—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02461—Phosphides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02455—Group 13/15 materials
- H01L21/02463—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02581—Transition metal or rare earth elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02658—Pretreatments
Definitions
- the present invention relates to the production of semiconductor devices and in particular to the preparation of indium phosphide semiconductor substrates for use in the production of semiconductor devices using MOVPE techniques.
- MOVPE Metal Organic Vapour Phase Epitaxy
- MOVPE Metal Organic Vapour Phase Epitaxy
- FETs InP based field effect transistors
- Fe-doped InP substrates because it prevents pinch-off by providing a parallel conduction path that cannot be controlled by gate voltage. This also raises output conductance, device-to-device leakage and can add a parasitic capacitance affecting high frequency performance.
- Interfacial impurities have been variously attributed to out diffusion from the substrate, residues from substrate preparation solutions and contamination from ambient air.
- the inventors have observed Si accumulation in an MOVPE kit for several weeks following refurbishment of the vent-run gas switching manifold. Even when below detection limits in grown layers, this is another potential source of surface contamination during wafer heat-up. In practice, it is quite likely that several of these mechanisms may contribute to contamination simultaneously, varying in degree of severity depending on factors such as the substrate batch or manufacturer, its handling and preparation procedure, chemical batches and the history of the growth kit.
- Ishikawa et al proposed a method of removing the atoms from the InP substrate by annealing it in a PH 3 atmosphere, The process involved heating the InP to a temperature of around 700 °C for 20 minutes with a PH 3 flow rate of 1200sccm. The results indicated that a high proportion of the Si atoms adsorbed into the InP 5 surface were desorbed, which reduced the effect of n-type Si conduction.
- the present invention provides a method of preparing a semiconductor substrate for subsequent growth of epitaxial layers, the method comprising the steps of, annealing the substrate to reduce the concentration of impurity atoms present on or in the substrate, and thereafter, growing one or more buffer layers on the substrate, the or at least one of the buffer layers comprising a semiconductor material doped with metal atoms.
- the annealing step promotes any tendency for surface accumulation of impurities, for example silicon atoms, by diffusion from the bulk substrate. Also, annealing promotes impurity atom removal from the substrate surface.
- impurity atoms for example silicon atoms
- phosphorus atoms in or on the substrate are replaced with phosphorus atoms.
- the annealing is carried out at a temperature which is high enough to promote high mobility of surface atoms on the substrate.
- the phosphorus atoms are transported in a flow of gaseous phosphine, or other suitable phosphorus containing compound which yields phosphorus atoms, the flow rate being great enough to maintain an overpressure which prevents net loss of phosphorus atoms due to heating. It has been shown [2] that the rate of removal of silicon impurity atoms is proportional to the heating time, the heating temperature and the flow rate of phosphine.
- the maximum benefit from annealing can be achieved by maximising the values in the annealing process.
- the values should in practice be set for practicality, i.e. so that the annealing step does not take too long, phosphine flow is not so high that filters become blocked, etc. It is expected that some benefit would accrue at a temperature as low as 600°C, for a time as short as 5 minutes and with the minimum phosphine flow sufficient to stabilise the InP surface at the anneal temperature.
- Substrates other than InP are typically annealed in atmospheres comprising other suitable conditions. For example, for a GaAs substrate, the annealing step is carried out in an atmosphere typically comprising arsine.
- the buffer layer (or layers) provide(s) a semi-insulating barrier between the substrate and subsequently grown epitaxial layers to reduce the influence the substrate has over the nature and performance of the subsequently grown epitaxial layers.
- semi-insulating layers can be epitaxially grown by MOVPE by varying the lll/V ratio.
- GaAIAs GaAIAs, and vice versa. Near the point of conversion, the GaAs or GaAIAs exhibits high resistivity and can thus act as a semi-insulating layer.
- At least one buffer layer is deposited on the semiconductor substrate using MOVPE growth techniques.
- the buffer layer is doped with iron to increase the resistance of the buffer layer by allowing the electrically active iron atoms to act as deep carrier traps for the n-type carriers.
- other semi-insulating dopants such as cobalt (Co) and rhodium (Rh) are expected to be effective alternatives dopants to iron to act as n-type carrier traps, although, in most cases the resistivity of the InP will be lower.
- dopants for example chromium
- chromium have been seen to act as p-type carrier traps in InP and GaAs.
- a dopant to act as an effective carrier trap it is a requirement that it sits as closely as possible to the centre of the band- gap of the base material in which it is doped. Then, the dopant, and hence any trapped carriers, are as far away as possible from both the valance and conduction bands of the base material making carrier escape through thermal or electrical excitation difficult.
- the doped base material increases greatly in resistivity.
- a dopant is selected for its ability to act either as a p-type carrier trap or as an n-type carrier trap in dependence on the type of conduction, for example due to the presence of impurities, exhibited by the base material.
- a combination of annealing and a subsequently grown semi-insulating buffer layer is an effective method of greatly reducing the effects of conducting interfacial layers, in most cases.
- a further step is included in the preparatory stages of a substrate to offer greater protection against the vagaries of substrate quality.
- the further step is an etch step, which is carried out between the annealing step and the buffer layering step.
- the etch step removes any surface contaminants from the substrate, for example oxygen or oxides which may have contaminated the substrate from the atmosphere in which the boule is stored or transported, and provides a clean, flat surface on which subsequent epitaxial layers can be grown.
- any etching process and indeed any etchant, for example phosphorus trichloride to etch InP, which is shown to provide non-preferential etching (i.e. polish etching), without unduly roughening the substrate surface, is suitable for the etching step.
- gas-etching provides better results than wet-etching because gas-etching is carried out in-situ, providing exclusion of impurities that may re-contaminate the surface of the substrate.
- no more than about 1 mm (that is to say, the first few monolayers) of surface substrate is removed to provide a substrate surface of the required cleanliness.
- Figure 1 shows a typical HFET structure
- Figure 2 shows typical capacitance/voltage depth profiles of HFETs tested in the course of experiment; and Figure 3 shows a typical set of HFET characteristics obtained from an HFET fabricated on a substrate prepared according to the present invention.
- An iron-doped InP substrate was prepared for subsequent epitaxial HFET device growth as follows.
- the iron-doped InP substrate was installed in an atmospheric pressure
- MOVPE reactor For the annealing stage, the substrate was heated to a temperature of around 750°C, in the reactor, in an atmosphere of phosphine and highly pure hydrogen.
- phosphine flow should be present during the whole substrate heating process, or at least from around 400°C upwards.
- the rate of impurity silicon atom removal from a substrate due to the annealing step has been reported to be proportional to the heating time and substrate temperature [2].
- the substrate was annealed at 750°C for 30 minutes with a phosphine flow of 46sccm (standard cubic centimetres per minute), to provide a partial overpressure of 7x10 "3 atm.
- This temperature, time and phosphine flow were all set to the maximum practical levels which the MOVPE reactor could sustain to maximise the promotion of any tendency for surface accumulation of impurities from the bulk substrate, and also to promote Si removal by exchange of impurity atoms on the substrate surface with those of phosphine.
- the phosphine flow was switched off and replaced with a 50sccm phosphorus trichloride flow diluted with a high purity hydrogen carrier having a flow rate of 6.3 litres/minute.
- the phosphorus trichloride was contained in a bubbler held at 0°C and its vapour transported into the reactor at a rate of 9.5x10 "5 mole per minute by the hydrogen (carrier) gas.
- the flows and etching temperature were determined by calibration and were those found optimal for non-preferential etching at a controlled and reproducible rate of 1 mm per hour.
- the flow of phosphine was re-instated to maintain the surface of the substrate in a stable state during a period taken to heat the substrate from 400°C to 650°C.
- the buffer layers were grown at 650°C using a conventional MOVPE process.
- buffer layers There are three buffer layers - a bottom layer of iron-doped AllnAs, a middle layer of iron-doped InP and a top, capping, layer of undoped InP.
- the iron-doped AllnAs was grown, at 650°C, in an atmosphere of: trimethylaluminium @ 6.7x10 "6 mol/cm 3 ; trimethylindium @ 2.4x10 "5 mol/ cm 3 ; and, arsine (100%) @ 3x10 "3 mol/cm 3 , providing a growth rate of 3.0 ⁇ m per hour.
- HFET structures were grown on substrates prepared according to conventional methods and also according to the present method. The HFETs were then tested for their pinch-off characteristics.
- the typical structure of the HFETs tested is shown in Figure 1 .
- the HFET structures were grown by atmospheric pressure MOVPE using conventional methyl metal group III and hydride group V precursors.
- the basic HFET structure grown on top of the buffer layer 1 1 , lattice matched to a semi-insulating iron-doped ( 100) InP substrate 10, consisted of the following layers: 0.3mm undoped InP 1 2, 70nm S doped GalnAs (2x10 17 cm 3 n-type) 13, 5nm undoped GaAIAs 14, 50nm undoped AllnAs 1 5, 5nm undoped InP 1 6.
- the element ratios should be those which give lattice matching to InP to ⁇ l OOOppm.
- the HFETs were fabricated with 100mm wide, 1 mm long gates using the process which is described in detail in D. J. Newson et al, "Damage-free passivation of InAIAs/lnGaAs HFETs by use of ECR-deposited SiN", Electronics letters 1 993, 29, pp472-474, the contents of which are incorporated herein by reference. The results of the experimental pinch-off tests are correlated in Table 1 .
- the table also shows the conditions from which the results were derived.
- the devices were designed to pinch-off fully before -2V gate bias.
- the criterion used in the table is pinch-off before -5V as such gross deviations are well outside doping control limits of the MOVPE kit used and must be substrate interface related.
- the first test approach (batches 1 to 9) was to load substrates as supplied because experience indicated that almost anything done to the Fe-doped material led to poorer epilayer morphology. However, this approach, even when combined with a variety of buffer layer types, only once led to good pinch-off (batch 6), and this was not reproducible.
- Table 1 showing the pinch-off performance of various HFETs fabricated on substrates prepared in various ways (u indicates undoped, Fe indicates iron-doped)
- batches 1 2 to 16 all used a gas etch, the invention does extend to the use of a wet or other type of etch.
- Figure 3 shows a set of HFET characteristics obtained from HFETs fabricated on substrates prepared by the method according to the present invention. From the graph it can be seen that pinch-off occurs at less than 2V.
- the method of substrate preparation described above finds particular application in the field of HFET fabrication on InP substrates, it will be apparent that the technique finds important application in the general field of semiconductor device fabrication.
- the method is not limited to the steps described above for fabricating a standard HFET.
- the method finds application in the fabrication of other types of semiconductor devices such as HEMTs (high electron mobility transistors) and optical devices such as lasers, and photo-detectors, or indeed any type of semiconductor device which requires high quality InP substrate preparation.
- HEMTs high electron mobility transistors
- optical devices such as lasers, and photo-detectors
- the precise details of layer composition, doping, thickness and of overall device dimensions are given by way of example only.
- Other devices, whether HFETs or otherwise, according to the invention will typically have very different characteristics to that described above. Nevertheless, the application of the present invention to the fabrication of semiconductor devices will be clear to those skilled in the art.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- Inorganic Chemistry (AREA)
- Junction Field-Effect Transistors (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Substrat semi-conducteur en phosphure d'indium (10) préparé en vue d'une croissance ultérieure de couches épitaxiales (12 à 16) formant un dispositif à semi-conducteurs (5). Lors de la préparation de ce substrat, on procède d'abord au recuit du substrat (10) afin de favoriser toute tendance à l'accumulation superficielle d'atomes d'impureté par diffusion à partir du substrat, et de favoriser l'évacuation des atomes d'impureté à partir de la surface du substrat. Ensuite, on procède à la gravure de la surface du substrat (10) afin d'éliminer d'autres impuretés et d'obtenir une surface propre et plate permettant la croissance ultérieure de couches épitaxiales. L'ultime étape de préparation consiste à réaliser la croissance sur le substrat d'une couche intermédiaire semi-isolante (11) isolant du substrat les couches épitaxiales (12 à 16) du dispositif.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP95923462A EP0767969A1 (fr) | 1994-06-29 | 1995-06-29 | Preparation de substrats semi-conducteurs |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP94304754 | 1994-06-29 | ||
EP94304754 | 1994-06-29 | ||
EP95923462A EP0767969A1 (fr) | 1994-06-29 | 1995-06-29 | Preparation de substrats semi-conducteurs |
PCT/GB1995/001541 WO1996000979A1 (fr) | 1994-06-29 | 1995-06-29 | Preparation de substrats semi-conducteurs |
Publications (1)
Publication Number | Publication Date |
---|---|
EP0767969A1 true EP0767969A1 (fr) | 1997-04-16 |
Family
ID=8217756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP95923462A Withdrawn EP0767969A1 (fr) | 1994-06-29 | 1995-06-29 | Preparation de substrats semi-conducteurs |
Country Status (6)
Country | Link |
---|---|
EP (1) | EP0767969A1 (fr) |
JP (1) | JPH10504685A (fr) |
KR (1) | KR970704246A (fr) |
CN (1) | CN1092839C (fr) |
CA (1) | CA2193098C (fr) |
WO (1) | WO1996000979A1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6462361B1 (en) | 1995-12-27 | 2002-10-08 | Showa Denko K.K. | GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure |
TW522574B (en) * | 1999-09-28 | 2003-03-01 | Showa Denko Kk | GaInP epitaxial stacking structure, a GaInP epitaxial stacking structure for FETs and a fabrication method thereof |
US6956237B2 (en) | 2002-12-28 | 2005-10-18 | Lg.Philips Lcd Co., Ltd. | Thin film transistor array substrate and method for manufacturing the same |
CN100364063C (zh) * | 2004-06-21 | 2008-01-23 | 中国科学院半导体研究所 | 电化学腐蚀制备多孔磷化铟半导体材料的方法 |
CN106972058B (zh) * | 2016-12-15 | 2020-02-11 | 苏州能讯高能半导体有限公司 | 一种半导体器件及其制备方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01226796A (ja) * | 1988-03-04 | 1989-09-11 | Sumitomo Electric Ind Ltd | インジウムリン基板の処理方法 |
CN1040401A (zh) * | 1989-04-14 | 1990-03-14 | 吉林大学 | 砷化镓/磷化铟异质气相外延技术 |
JPH03161922A (ja) * | 1989-11-20 | 1991-07-11 | Nec Corp | 異種基板上への3―5族化合物半導体のヘテロエピタキシャル成長法 |
CN1053146A (zh) * | 1991-02-04 | 1991-07-17 | 中国科学院西安光学精密机械研究所 | 砷化镓衬底上的混合并质外延 |
-
1995
- 1995-06-29 KR KR1019960707298A patent/KR970704246A/ko not_active Application Discontinuation
- 1995-06-29 CA CA002193098A patent/CA2193098C/fr not_active Expired - Fee Related
- 1995-06-29 CN CN95194628A patent/CN1092839C/zh not_active Expired - Fee Related
- 1995-06-29 JP JP8502952A patent/JPH10504685A/ja active Pending
- 1995-06-29 EP EP95923462A patent/EP0767969A1/fr not_active Withdrawn
- 1995-06-29 WO PCT/GB1995/001541 patent/WO1996000979A1/fr not_active Application Discontinuation
Non-Patent Citations (1)
Title |
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See references of WO9600979A1 * |
Also Published As
Publication number | Publication date |
---|---|
JPH10504685A (ja) | 1998-05-06 |
WO1996000979A1 (fr) | 1996-01-11 |
KR970704246A (ko) | 1997-08-09 |
CN1155353A (zh) | 1997-07-23 |
CA2193098C (fr) | 2001-02-20 |
CN1092839C (zh) | 2002-10-16 |
CA2193098A1 (fr) | 1996-01-11 |
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