Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/14—Protection against unauthorised use of memory or access to memory
  • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
  • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
  • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
  • G06F11/0751—Error or fault detection not based on redundancy
  • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
  • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Definitions

• the invention relates to a method for control ⁇ ling writing to a memory, in which method a memory write operation is permitted only within a predetermined time interval from the writing of a predetermined key code to a predetermined memory location.
• Random-access memory is a semiconductor memory to which information can be rapidly stored, wherefore RAM is used in microcomputers when rapid storing or reading of information is required. On the other hand, it is also characteristic of RAM that the information written into it is erased when supply voltage is shut off. However, the types of RAM that require only a little power to store information can be used to store information even during a power failure if they are provided with a standby power supply, e.g. a battery or an accumulator.
• a standby power supply e.g. a battery or an accumulator.
• a slot machine RAM can be used, for example, for storing information on money and failures. This information is important for the operation of the whole machine, since without reliable information the opera ⁇ tion of the machine can stop. The same information can be stored simultaneously in several different memory circuits so that when a failure occurs, the operation can be continued with proper information. When several memory circuits are used, the likelihood that the same information would be erroneously treated reduces if an interrupted writing operation is considered to have caused the error.
• a so-called chip enable signal CE is used for this purpose in such a manner that the CE signal can be activated only by such memory write sequences addressed to RAM that are written within a fixed interval of time from the writing of a key code word to a memory location outside the RAM storage space.
• the copying rate is of great significance: the supply voltage of the apparatus may be shut off any time, and the copying may be left uncompleted.
• the faster the copying can be per- formed the smaller is the likelihood that the copying would be left uncompleted and fail.
• the object of the present invention is to provide a memory control enabling more rapid writing to a memory.
• This object is achieved by a method of the type described in the introductory portion, said method being characterized in that after a successful memory write operation following the writing of each key code, a new memory write operation is permitted within a predeter- mined time interval from the previous one without re ⁇ writing of the key code.
• a property which enables a new write operation is connected with the giving of a key code: after each successful write operation to RAM, memory protection permits a new write operation without a new key code within a fixed time interval.
• the first write operation is correctly per ⁇ formed, the following write operation can be performed without separate opening of the time window by a key code.
• Time control is, however, maintained in the inven- tion. Due to the invention, a long data block can be written to RAM as rapidly as the apparatus controlling the memory can - provided, however, that there is not too long a pause between the write operations - without the time consuming operation of giving the key code in connection with each write operation.
• a further object of the invention is an apparatus for controlling writing to a memory, compris ⁇ ing control means for forming a memory activation signal in response to the applying of a predetermined key code to the control means, the control means comprising timer means which are started by applying the key code and which prevent the formation of the memory activation signal when a predetermined time has elapsed since the applying of the key code.
• the apparatus is characterized in that the control means further comprise means for restarting the timer means within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.
• Still another object of the invention is the use of the apparatus according to the invention in a slot machine for copying cash and operation data from one memory to another for backup storage of the data.
• the inven ⁇ tion which generates one of the signals, in this case a chip enable signal CE.
• the signal CE can control a memory formed by one or several memory circuits.
• the circuitry shown in the figure generates the chip enable signal CE for both read and write opera ⁇ tions.
• Information can be read without restrictions from a semiconductor RAM: when the storage space con ⁇ trolled by the circuitry is addressed for a RAM memory read operation, a decoder circuit 4 sets its output signal RAMREAD in an active state or 0, whereby an out ⁇ put signal of an AND gate 8, i.e. the chip enable signal CE, also changes to its active state 0, activating the memory.
• Writing to the memory is started by addressing a RAM enable register 1 located in a memory location outside the RAM memory space to be written into and writing a key code word of at least two bits, preferably eight bits, to the register.
• the correct key code word activates an output signal RAMOK of the enable register 1 by setting it in state 0.
• the signal RAMOK is passed by an AND gate 5 to a time control timer 2, which sets its output signal TIMEOK in an active state 0 and starts to count the time interval.
• the TIMEOK signal is fed to a second input of an OR gate 7.
• a signal RAMWR is fed to the second input of the OR gate 7 from a decoder circuit 3, which sets the signal RAMWR in an active state 0 when the RAM memory space controlled by the circuitry is addressed for RAM memory write. If a write operation is performed within a certain time interval, i.e. when the signal TIMEOK is 0, the output of the OR gate 7 changes its state to active or 0 and thereby activates even the signal CE. If a write operation is not performed within the given time interval, the time control timer 2 forces the signal TIMEOK to assume a state 1, which prevents the activation of the output of the OR gate 7 and there ⁇ by the activation of the signal CE, even though RAMWR would activate as a result of a write attempt.
• the signals RAMWR and TIMEOK are also applied to the inputs of an OR gate 6.
• the output of the OR gate 6 is connected to an input of an AND gate 5, another input of which receives the signal RAMOK. If a write operation is performed within the given time interval, i.e. when the signal TIMEOK is in state 0, both of the inputs of the OR gate 6 are simul ⁇ taneously in state 0, which activates the output of the gate 6 and resets the timer 2 through the AND gate 5. It is then again possible, within the given time interval, to perform a new write operation, which again resets the timer 2. If a read operation is not performed within the time interval and the signal TIMEOK changes its state, the setting of the timer 2 through the OR gate 6 is prevented. In this case, a write operation can be performed only by rewriting the key code word to the register 1.
• the invention is particularly suitable for a system which is provided with at least two RAM circuits for storing information and in which one RAM circuit is used for copying the information in the other RAM circuit(s).
• the information to be stored is thereby copied as blocks from a memory circuit to another.
• Several memory circuit write operations are used for the copying of each block.
• it is necessary to write a key code word of at least two bits to an external register in order that copying might be started. There must not be a delay exceeding the given time interval between the instants of writing two pieces of information to be copied subsequently, or otherwise the key code word must be given again.
• the time interval is the time required for the control apparatus to read information out of one memory circuit and to write information into another memory circuit plus the time taken by the additional measures needed in copying. In the preferred embodiment of the inven ⁇ tion, the time interval is of the magnitude 5 ⁇ m.
• the invention is particularly well suitable for use in the copying of cash and operation data in a slot machine or the like.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Computer Security & Cryptography (AREA)
• Theoretical Computer Science (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Techniques For Improving Reliability Of Storages (AREA)
• Storage Device Security (AREA)
• Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Applications Claiming Priority (2)

Publications (1)

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ID=8529649

Family Applications (1)

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• 1990
  • 1990-01-05 FI FI900063A patent/FI86922C/fi active IP Right Grant
• 1991
  • 1991-01-02 AU AU69738/91A patent/AU640442B2/en not_active Ceased
  • 1991-01-02 WO PCT/FI1991/000005 patent/WO1991010192A1/en not_active Application Discontinuation
  • 1991-01-02 CA CA002070986A patent/CA2070986A1/en not_active Abandoned
  • 1991-01-02 JP JP3501832A patent/JPH05502957A/ja active Pending
  • 1991-01-02 HU HU9202106A patent/HU207593B/hu not_active IP Right Cessation
  • 1991-01-02 PL PL29201391A patent/PL292013A1/xx unknown
  • 1991-01-02 EP EP91901421A patent/EP0507811A1/de not_active Ceased
• 1992
  • 1992-07-03 NO NO92922652A patent/NO922652L/no unknown

Non-Patent Citations (1)

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