WO1991010192A1 - Method and apparatus for controlling writing to memory - Google Patents

Method and apparatus for controlling writing to memory Download PDF

Info

Publication number
WO1991010192A1
WO1991010192A1 PCT/FI1991/000005 FI9100005W WO9110192A1 WO 1991010192 A1 WO1991010192 A1 WO 1991010192A1 FI 9100005 W FI9100005 W FI 9100005W WO 9110192 A1 WO9110192 A1 WO 9110192A1
Authority
WO
WIPO (PCT)
Prior art keywords
memory
key code
write operation
writing
control means
Prior art date
Application number
PCT/FI1991/000005
Other languages
French (fr)
Inventor
Jouko Laatikainen
Original Assignee
Raha-Automaattiyhdistys
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raha-Automaattiyhdistys filed Critical Raha-Automaattiyhdistys
Publication of WO1991010192A1 publication Critical patent/WO1991010192A1/en
Priority to NO92922652A priority Critical patent/NO922652L/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/20—Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs

Definitions

  • the invention relates to a method for control ⁇ ling writing to a memory, in which method a memory write operation is permitted only within a predetermined time interval from the writing of a predetermined key code to a predetermined memory location.
  • Random-access memory is a semiconductor memory to which information can be rapidly stored, wherefore RAM is used in microcomputers when rapid storing or reading of information is required. On the other hand, it is also characteristic of RAM that the information written into it is erased when supply voltage is shut off. However, the types of RAM that require only a little power to store information can be used to store information even during a power failure if they are provided with a standby power supply, e.g. a battery or an accumulator.
  • a standby power supply e.g. a battery or an accumulator.
  • a slot machine RAM can be used, for example, for storing information on money and failures. This information is important for the operation of the whole machine, since without reliable information the opera ⁇ tion of the machine can stop. The same information can be stored simultaneously in several different memory circuits so that when a failure occurs, the operation can be continued with proper information. When several memory circuits are used, the likelihood that the same information would be erroneously treated reduces if an interrupted writing operation is considered to have caused the error.
  • a so-called chip enable signal CE is used for this purpose in such a manner that the CE signal can be activated only by such memory write sequences addressed to RAM that are written within a fixed interval of time from the writing of a key code word to a memory location outside the RAM storage space.
  • the copying rate is of great significance: the supply voltage of the apparatus may be shut off any time, and the copying may be left uncompleted.
  • the faster the copying can be per- formed the smaller is the likelihood that the copying would be left uncompleted and fail.
  • the object of the present invention is to provide a memory control enabling more rapid writing to a memory.
  • This object is achieved by a method of the type described in the introductory portion, said method being characterized in that after a successful memory write operation following the writing of each key code, a new memory write operation is permitted within a predeter- mined time interval from the previous one without re ⁇ writing of the key code.
  • a property which enables a new write operation is connected with the giving of a key code: after each successful write operation to RAM, memory protection permits a new write operation without a new key code within a fixed time interval.
  • the first write operation is correctly per ⁇ formed, the following write operation can be performed without separate opening of the time window by a key code.
  • Time control is, however, maintained in the inven- tion. Due to the invention, a long data block can be written to RAM as rapidly as the apparatus controlling the memory can - provided, however, that there is not too long a pause between the write operations - without the time consuming operation of giving the key code in connection with each write operation.
  • a further object of the invention is an apparatus for controlling writing to a memory, compris ⁇ ing control means for forming a memory activation signal in response to the applying of a predetermined key code to the control means, the control means comprising timer means which are started by applying the key code and which prevent the formation of the memory activation signal when a predetermined time has elapsed since the applying of the key code.
  • the apparatus is characterized in that the control means further comprise means for restarting the timer means within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.
  • Still another object of the invention is the use of the apparatus according to the invention in a slot machine for copying cash and operation data from one memory to another for backup storage of the data.
  • the inven ⁇ tion which generates one of the signals, in this case a chip enable signal CE.
  • the signal CE can control a memory formed by one or several memory circuits.
  • the circuitry shown in the figure generates the chip enable signal CE for both read and write opera ⁇ tions.
  • Information can be read without restrictions from a semiconductor RAM: when the storage space con ⁇ trolled by the circuitry is addressed for a RAM memory read operation, a decoder circuit 4 sets its output signal RAMREAD in an active state or 0, whereby an out ⁇ put signal of an AND gate 8, i.e. the chip enable signal CE, also changes to its active state 0, activating the memory.
  • Writing to the memory is started by addressing a RAM enable register 1 located in a memory location outside the RAM memory space to be written into and writing a key code word of at least two bits, preferably eight bits, to the register.
  • the correct key code word activates an output signal RAMOK of the enable register 1 by setting it in state 0.
  • the signal RAMOK is passed by an AND gate 5 to a time control timer 2, which sets its output signal TIMEOK in an active state 0 and starts to count the time interval.
  • the TIMEOK signal is fed to a second input of an OR gate 7.
  • a signal RAMWR is fed to the second input of the OR gate 7 from a decoder circuit 3, which sets the signal RAMWR in an active state 0 when the RAM memory space controlled by the circuitry is addressed for RAM memory write. If a write operation is performed within a certain time interval, i.e. when the signal TIMEOK is 0, the output of the OR gate 7 changes its state to active or 0 and thereby activates even the signal CE. If a write operation is not performed within the given time interval, the time control timer 2 forces the signal TIMEOK to assume a state 1, which prevents the activation of the output of the OR gate 7 and there ⁇ by the activation of the signal CE, even though RAMWR would activate as a result of a write attempt.
  • the signals RAMWR and TIMEOK are also applied to the inputs of an OR gate 6.
  • the output of the OR gate 6 is connected to an input of an AND gate 5, another input of which receives the signal RAMOK. If a write operation is performed within the given time interval, i.e. when the signal TIMEOK is in state 0, both of the inputs of the OR gate 6 are simul ⁇ taneously in state 0, which activates the output of the gate 6 and resets the timer 2 through the AND gate 5. It is then again possible, within the given time interval, to perform a new write operation, which again resets the timer 2. If a read operation is not performed within the time interval and the signal TIMEOK changes its state, the setting of the timer 2 through the OR gate 6 is prevented. In this case, a write operation can be performed only by rewriting the key code word to the register 1.
  • the invention is particularly suitable for a system which is provided with at least two RAM circuits for storing information and in which one RAM circuit is used for copying the information in the other RAM circuit(s).
  • the information to be stored is thereby copied as blocks from a memory circuit to another.
  • Several memory circuit write operations are used for the copying of each block.
  • it is necessary to write a key code word of at least two bits to an external register in order that copying might be started. There must not be a delay exceeding the given time interval between the instants of writing two pieces of information to be copied subsequently, or otherwise the key code word must be given again.
  • the time interval is the time required for the control apparatus to read information out of one memory circuit and to write information into another memory circuit plus the time taken by the additional measures needed in copying. In the preferred embodiment of the inven ⁇ tion, the time interval is of the magnitude 5 ⁇ m.
  • the invention is particularly well suitable for use in the copying of cash and operation data in a slot machine or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Storage Device Security (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)

Abstract

The invention relates to a method and apparatus for controlling writing to a memory. The apparatus comprises control means (1-8) for the formation of a memory activation signal (C^¨B7E^¨B7) in response to the applying of a predetermined key code to the control means, the control means comprising timer means (2) which are started by applying the key code and which prevent the formation of the memory activation signal (C^¨B7E^¨B7) when a predetermined time has elapsed from the applying of the key code. In order to speed up the writing of long data blocks into a memory, the invention is characterized in that the control means further comprise means (3, 5, 6) for restarting the time means (2) within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.

Description

Method and apparatus for controlling writing to memory
The invention relates to a method for control¬ ling writing to a memory, in which method a memory write operation is permitted only within a predetermined time interval from the writing of a predetermined key code to a predetermined memory location.
Random-access memory (RAM) is a semiconductor memory to which information can be rapidly stored, wherefore RAM is used in microcomputers when rapid storing or reading of information is required. On the other hand, it is also characteristic of RAM that the information written into it is erased when supply voltage is shut off. However, the types of RAM that require only a little power to store information can be used to store information even during a power failure if they are provided with a standby power supply, e.g. a battery or an accumulator.
In a slot machine RAM can be used, for example, for storing information on money and failures. This information is important for the operation of the whole machine, since without reliable information the opera¬ tion of the machine can stop. The same information can be stored simultaneously in several different memory circuits so that when a failure occurs, the operation can be continued with proper information. When several memory circuits are used, the likelihood that the same information would be erroneously treated reduces if an interrupted writing operation is considered to have caused the error.
In a known solution, unintentional alteration of RAM contents is prevented by keeping one of the signals controlling the memory write operation in a state preventing writing to a memory. In this known solution, a so-called chip enable signal CE is used for this purpose in such a manner that the CE signal can be activated only by such memory write sequences addressed to RAM that are written within a fixed interval of time from the writing of a key code word to a memory location outside the RAM storage space. Thus, the likelihood that the right code word is inadvertently given to the right memory location and erroneous writing to RAM takes place is extremely small.
When the information is secured by copying the memory contents to another memory circuit, functioning as a so-called backup memory, the copying rate is of great significance: the supply voltage of the apparatus may be shut off any time, and the copying may be left uncompleted. However, the faster the copying can be per- formed, the smaller is the likelihood that the copying would be left uncompleted and fail.
The object of the present invention is to provide a memory control enabling more rapid writing to a memory. This object is achieved by a method of the type described in the introductory portion, said method being characterized in that after a successful memory write operation following the writing of each key code, a new memory write operation is permitted within a predeter- mined time interval from the previous one without re¬ writing of the key code.
In the invention, a property which enables a new write operation is connected with the giving of a key code: after each successful write operation to RAM, memory protection permits a new write operation without a new key code within a fixed time interval. In other words, if the first write operation is correctly per¬ formed, the following write operation can be performed without separate opening of the time window by a key code. Time control is, however, maintained in the inven- tion. Due to the invention, a long data block can be written to RAM as rapidly as the apparatus controlling the memory can - provided, however, that there is not too long a pause between the write operations - without the time consuming operation of giving the key code in connection with each write operation.
A further object of the invention is an apparatus for controlling writing to a memory, compris¬ ing control means for forming a memory activation signal in response to the applying of a predetermined key code to the control means, the control means comprising timer means which are started by applying the key code and which prevent the formation of the memory activation signal when a predetermined time has elapsed since the applying of the key code. The apparatus is characterized in that the control means further comprise means for restarting the timer means within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.
Still another object of the invention is the use of the apparatus according to the invention in a slot machine for copying cash and operation data from one memory to another for backup storage of the data. In the following the invention will be described, by way of example, in greater detail by means of an embodiment with reference to the attached drawing. The figure shows an embodiment of the inven¬ tion, which generates one of the signals, in this case a chip enable signal CE. The signal CE can control a memory formed by one or several memory circuits.
The circuitry shown in the figure generates the chip enable signal CE for both read and write opera¬ tions. Information can be read without restrictions from a semiconductor RAM: when the storage space con¬ trolled by the circuitry is addressed for a RAM memory read operation, a decoder circuit 4 sets its output signal RAMREAD in an active state or 0, whereby an out¬ put signal of an AND gate 8, i.e. the chip enable signal CE, also changes to its active state 0, activating the memory.
Writing to RAM is, however, protected accord- ing to the invention.
Writing to the memory is started by addressing a RAM enable register 1 located in a memory location outside the RAM memory space to be written into and writing a key code word of at least two bits, preferably eight bits, to the register. The correct key code word activates an output signal RAMOK of the enable register 1 by setting it in state 0. The signal RAMOK is passed by an AND gate 5 to a time control timer 2, which sets its output signal TIMEOK in an active state 0 and starts to count the time interval. The TIMEOK signal is fed to a second input of an OR gate 7.
A signal RAMWR is fed to the second input of the OR gate 7 from a decoder circuit 3, which sets the signal RAMWR in an active state 0 when the RAM memory space controlled by the circuitry is addressed for RAM memory write. If a write operation is performed within a certain time interval, i.e. when the signal TIMEOK is 0, the output of the OR gate 7 changes its state to active or 0 and thereby activates even the signal CE. If a write operation is not performed within the given time interval, the time control timer 2 forces the signal TIMEOK to assume a state 1, which prevents the activation of the output of the OR gate 7 and there¬ by the activation of the signal CE, even though RAMWR would activate as a result of a write attempt. The signals RAMWR and TIMEOK are also applied to the inputs of an OR gate 6. The output of the OR gate 6 is connected to an input of an AND gate 5, another input of which receives the signal RAMOK. If a write operation is performed within the given time interval, i.e. when the signal TIMEOK is in state 0, both of the inputs of the OR gate 6 are simul¬ taneously in state 0, which activates the output of the gate 6 and resets the timer 2 through the AND gate 5. It is then again possible, within the given time interval, to perform a new write operation, which again resets the timer 2. If a read operation is not performed within the time interval and the signal TIMEOK changes its state, the setting of the timer 2 through the OR gate 6 is prevented. In this case, a write operation can be performed only by rewriting the key code word to the register 1.
The invention is particularly suitable for a system which is provided with at least two RAM circuits for storing information and in which one RAM circuit is used for copying the information in the other RAM circuit(s). The information to be stored is thereby copied as blocks from a memory circuit to another. Several memory circuit write operations are used for the copying of each block. According to the invention, it is necessary to write a key code word of at least two bits to an external register in order that copying might be started. There must not be a delay exceeding the given time interval between the instants of writing two pieces of information to be copied subsequently, or otherwise the key code word must be given again. The time interval is the time required for the control apparatus to read information out of one memory circuit and to write information into another memory circuit plus the time taken by the additional measures needed in copying. In the preferred embodiment of the inven¬ tion, the time interval is of the magnitude 5 μm.
The invention is particularly well suitable for use in the copying of cash and operation data in a slot machine or the like.
The figure and the description pertaining thereto are intended merely to illustrate the invention. In its details the invention can vary within the scope of the attached claims.

Claims

Claims:
1. A method for controlling writing to a memory, in which method a memory write operation is permitted only within a predetermined time interval from the writing of a predetermined key code to a predeter¬ mined memory location, c h a r a c t e r i z e d in that after a successful memory write operation following the writing of each key code, a new memory write opera- tion is permitted within a predetermined time interval from the previous one without rewriting of the key code.
2. A method according to claim 1, c h a r a c ¬ t e r i z e d in that the key code is written in a memory space into an area different from the one to which the memory write operation is to be addressed.
3. An apparatus for controlling writing to a memory, comprising control means (1-8) for forming a memory activation signal (CE) in response to the apply¬ ing of a predetermined key code to the control means, the control means comprising timer means (2) which are started by applying a key code and which prevent the formation of the memory activation signal (CE) when a predetermined time has elapsed since the applying of the key code, c h a r a c t e r i z e d in that the control means further comprise means (3, 5, 6) for restarting the timer means (2) within a predetermined time interval from the applying of the key code or the previous memory write operation as a result of a performed memory write operation.
4. Use of the apparatus according to claim 3 in a slot machine for copying cash and operation data from one memory to another for backup storage of the data.
PCT/FI1991/000005 1990-01-05 1991-01-02 Method and apparatus for controlling writing to memory WO1991010192A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
NO92922652A NO922652L (en) 1990-01-05 1992-07-03 PROCEDURE AND APPARATUS FOR CHECKING WRITING TO A COMPUTER

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI900063A FI86922C (en) 1990-01-05 1990-01-05 FOERFARANDE OCH ANORDNING FOER KONTROLLERING AV INSKRIVNING I ETT MINNE
FI900063 1990-01-05

Publications (1)

Publication Number Publication Date
WO1991010192A1 true WO1991010192A1 (en) 1991-07-11

Family

ID=8529649

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FI1991/000005 WO1991010192A1 (en) 1990-01-05 1991-01-02 Method and apparatus for controlling writing to memory

Country Status (9)

Country Link
EP (1) EP0507811A1 (en)
JP (1) JPH05502957A (en)
AU (1) AU640442B2 (en)
CA (1) CA2070986A1 (en)
FI (1) FI86922C (en)
HU (1) HU207593B (en)
NO (1) NO922652L (en)
PL (1) PL292013A1 (en)
WO (1) WO1991010192A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681965A1 (en) * 1991-10-01 1993-04-02 Motorola Inc MEMORY WRITE PROTECTION METHOD AND APPARATUS.

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493031A (en) * 1982-08-25 1985-01-08 At&T Bell Laboratories Memory write protection using timers
WO1985000719A1 (en) * 1983-07-19 1985-02-14 Robert Bosch Gmbh Method and device for protecting data entered in a ram memory by means of a keyboard
US4796235A (en) * 1987-07-22 1989-01-03 Motorola, Inc. Write protect mechanism for non-volatile memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493031A (en) * 1982-08-25 1985-01-08 At&T Bell Laboratories Memory write protection using timers
WO1985000719A1 (en) * 1983-07-19 1985-02-14 Robert Bosch Gmbh Method and device for protecting data entered in a ram memory by means of a keyboard
US4796235A (en) * 1987-07-22 1989-01-03 Motorola, Inc. Write protect mechanism for non-volatile memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681965A1 (en) * 1991-10-01 1993-04-02 Motorola Inc MEMORY WRITE PROTECTION METHOD AND APPARATUS.

Also Published As

Publication number Publication date
PL292013A1 (en) 1992-03-23
FI86922B (en) 1992-07-15
FI900063A0 (en) 1990-01-05
CA2070986A1 (en) 1991-07-06
AU6973891A (en) 1991-07-24
AU640442B2 (en) 1993-08-26
HU9202106D0 (en) 1992-10-28
HUT61109A (en) 1992-11-30
EP0507811A1 (en) 1992-10-14
NO922652D0 (en) 1992-07-03
JPH05502957A (en) 1993-05-20
NO922652L (en) 1992-07-03
FI86922C (en) 1992-10-26
HU207593B (en) 1993-04-28
FI900063A (en) 1991-07-06

Similar Documents

Publication Publication Date Title
US4612640A (en) Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
US5159671A (en) Data transfer unit for small computer system with simultaneous transfer to two memories and error detection and rewrite to substitute address
US5793774A (en) Flash memory controlling system
US5353256A (en) Block specific status information in a memory device
US5592641A (en) Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status
EP0420994B1 (en) Memory cartridge
US5778440A (en) Floating gate memory device and method for terminating a program load cycle upon detecting a predetermined address/data pattern
US4603406A (en) Power backed-up dual memory system
US5226006A (en) Write protection circuit for use with an electrically alterable non-volatile memory card
KR19990036312A (en) Fixed-safe nonvolatile memory programming system and method
EP0398545A1 (en) Method and apparatus for storing data in a non-volatile memory
EP0990987B1 (en) Electrical device with flash memory built-in
US7200759B2 (en) Method and device for making information contents of a volatile semiconductor memory irretrievable
JP3376306B2 (en) Data processing apparatus and data processing method
US5765002A (en) Method and apparatus for minimizing power consumption in a microprocessor controlled storage device
JP2002108713A (en) Memory device and memory access control method
AU640442B2 (en) Method and apparatus for controlling writing to memory
JPH0822422A (en) Memory device
JPS60117340A (en) Electron system with trouble protecting function
JPH0778231A (en) Memory card
JP3028567B2 (en) Microcomputer with built-in EEPROM
JPS6217299B2 (en)
JP3190421B2 (en) IC memory card system
JP2001014872A (en) Erroneous write prevention system for nonvolatile semiconductor memory
JPH11242889A (en) Non-volatile semiconductor storage device and its erasing method

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AT AU BB BG BR CA CH DE DK ES FI GB HU JP KP KR LK LU MC MG MW NL NO PL RO SD SE SU US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE BF BJ CF CG CH CM DE DK ES FR GA GB GR IT LU ML MR NL SE SN TD TG

WWE Wipo information: entry into national phase

Ref document number: 2070986

Country of ref document: CA

WWE Wipo information: entry into national phase

Ref document number: 1991901421

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

WWP Wipo information: published in national office

Ref document number: 1991901421

Country of ref document: EP

WWR Wipo information: refused in national office

Ref document number: 1991901421

Country of ref document: EP

WWW Wipo information: withdrawn in national office

Ref document number: 1991901421

Country of ref document: EP