EP0506287B1 - Verfahren zur Herstellung von Halbleiteranordnungen und integrierten Schaltkreisen mit Verwendung von Seitenwand-Abstandsstücken - Google Patents

Verfahren zur Herstellung von Halbleiteranordnungen und integrierten Schaltkreisen mit Verwendung von Seitenwand-Abstandsstücken Download PDF

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EP0506287B1
EP0506287B1 EP92302308A EP92302308A EP0506287B1 EP 0506287 B1 EP0506287 B1 EP 0506287B1 EP 92302308 A EP92302308 A EP 92302308A EP 92302308 A EP92302308 A EP 92302308A EP 0506287 B1 EP0506287 B1 EP 0506287B1
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layer
oxide
oxide layer
oxygen
forming
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French (fr)
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EP0506287A1 (de
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Min-Liang Chen
Sailesh Chittipeddi
Taeho Kook
Richard Allyn Powell
Pradip Kumar Roy
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AT&T Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • This invention relates to a method of fabrication semiconductor devices and integrated circuits using sidewall spacer technology.
  • LDD structure which positions a relatively lightly doped region under the gate and a more heavily doped region between the lightly doped region and the field oxide.
  • the processing technology commonly used to realize such LDD structures follows the general prescription of U.S. patent 4,038,107 granted to G. Marr and G. E.
  • the principal steps include forming source and drain openings to allow one or more first ion implantation steps; reducing the size of the openings by forming (e.g., by oxidation) spacers on the sidewalls of the gate stack; and then by means of one or more second ion implantation steps, implanting additional impurities through the reduced size openings.
  • the spacer serves to prevent any substantial implantation in the region thereunder, thus preserving the desired lightly-doped region.
  • Spacer technology has become very common in 1.25 ⁇ m and 0.8 ⁇ m technology where a quadrant-like spacer typically comprises a single L-shaped base layer adjacent both the gate stack and the substrate and also includes a filler layer disposed between the legs of the L-shaped base layer.
  • a quadrant-like spacer typically comprises a single L-shaped base layer adjacent both the gate stack and the substrate and also includes a filler layer disposed between the legs of the L-shaped base layer.
  • use of a single layer grown oxide for the base layer and a deposited oxide for the filler layer has been found to be adequate for many applications.
  • design rules shrink to well below 1 ⁇ m e.g., 0.5 ⁇ m or 0. 35 ⁇ m
  • a number of problems arise or are exacerbated: (1) As the spacer gets very thin, the dielectric quality and the Si/SiO 2 interfacial substructure of the spacer material become more and more important.
  • the surface of the sidewalls on which the base layer is formed is typically a polysilicon surface, not a single crystal silicon surface;
  • a well-known micro bird's beak (e.g., feature 10 of FIG. 10) forms at the edges of the gate during the thermal oxidation step used to grow the base layer.
  • the bird's beak itself reduces the localized electric field at the edges of the gate, which is beneficial.
  • the thickness of the gate oxide may become too nonuniform. Consequently, the threshold voltage characteristics of the FET may be degraded and the source/drain series resistance may increase.
  • an etch-resistant cap layer is formed on the dielectric layer which itself is preferably a deposited oxide. The latter is densified during the growth of the second oxide layer.
  • the base layer may be L-shaped and a quadrant-like filler may or may not fill the space between the legs of the L-shaped base layer.
  • Each spacer 22 comprises a composite, multi-layered base layer (22.1-22.3), an optional etch resistant layer 22.4, and an optional filler region 22.5'.
  • the base layer comprises first oxide layer 22.2 disposed adjacent to the sidewall of the feature, a second oxide layer 22.1 disposed between the sidewall and layer 22.2, and an oxygen-permeable dielectric layer 22.3 disposed on layer 22.2.
  • an etch-resistant cap layer 22.4 is disposed on the dielectric layer 22.3.
  • the spacer may include optional, quadrant-like oxide filler region 22.5' which is disposed between the legs of the L-shaped layer 22.4.
  • device 20 is a MOSFET in which the structural feature 24 is a gate stack, including gate dielectric 24.1, disposed between field oxide (FOX) regions 26.
  • Source and drain regions 28 are located in substrate 30 between the gate stack and the FOX regions 26.
  • substrate is intended to include a single crystal semiconductor body or such a body with one or more layers formed thereon; e.g., an epitaxial layer or a polycrystalline layer. Omitted for simplicity are the well-known metallization and/or silicide regions typically used to make electrical contact to the source, drain and gate.
  • substrate 30 is single crystal silicon
  • gate stack 24 comprises polysilicon
  • gate dielectric 24.1 comprises a silicon oxide
  • first and second oxide layers 22.2 and 22.1 are thermally grown silicon oxides
  • oxygen-permeable layer 22.3 comprises TEOS (i.e., a silicon oxide layer formed by CVD from a tetraethylorthosilicate source)
  • etch-resistant layer 22.4 comprises an etch resistant material such as silicon nitride
  • oxide filler region 22.5' also comprises TEOS.
  • TEOS includes variations and equivalents thereof such as, for example, BPTEOS (boron and phorphorus doped TEOS).
  • the grown oxide layers 22.1 and 22.2 and the deposited oxide layer 22.3 are low defect density oxides fabricated by a grow-deposit-grow process of the type described in U.S. Patent 4,851,370 granted on July 25, 1989 to R. H. Doklan, E. P. Martin, P. K. Roy, S. F. Shive and A. K. Sinha.
  • LDD lightly-doped drain
  • the invention is also suitable for other applications in which, for example, spacers are used to provide dielectric isolation.
  • the latter includes isolation of the gate from source/drain in salicided MOSFETs (FIGS. 8-9) and the isolation of conductive polycrystalline or amorphous silicon levels in EPROMs.
  • fabricating a LDD MOSFET at, for example, 0.5 ⁇ m design rules or less in accordance with the above embodiment of the invention begins with a suitable single crystal silicon substrate 30 as shown in FIG. 1.
  • a polysilicon gate stack 24 is formed between FOX regions 26.
  • Gate oxide layer 24.1 separates gate stack 24 from substrate 30.
  • Oxide layers 25 also cover the location where the spacers and source/drain regions will later be formed. Oxide layers 25 are removed and gate stack 24 is slightly undercut, as shown in FIG. 2, by a wet chemical etch using illustratively 100:1 HF in water.
  • suitable n-type impurities e.g., P or As at a dose of about 2 E13 - 6 E13
  • suitable p-type impurities e.g., B from a BF 2 source at a dose of about 5 E13 - 8 E14
  • suitable p-type impurities e.g., B from a BF 2 source at a dose of about 5 E13 - 8 E14
  • the first step in the grow-deposit-grow process to form the composite, multi-layered base layer is the thermal growth of oxide layer 22.2, as shown in FIG. 3, in an oxygen ambient at a temperature of about 700 - 900°C. Growth of about 3-15 nm (30-150 ⁇ ) of oxide layer 22.2 is adequate.
  • the second step is to deposit an oxygen-permeable TEOS layer 22.3, e.g., about 3-15 nm (30-150 ⁇ ) thick, by the well-known CVD from a tetraethylorthosilicate source (e.g., at about 26.6-39.9 Pa (0.2 - 0.3 torr) and about 600 - 630°C).
  • the third step is to thermally grow oxide layer 22.1 (e.g., about 3-10 nm (30-100 ⁇ ) thick) between polysilicon stack 24 and first oxide layer 22.2.
  • oxide layer 22.1 e.g., about 3-10 nm (30-100 ⁇ ) thick
  • This growth is accomplished by atmospheric or high pressure (e.g., about 5.10 5 -10 6 Pa (5 - 10 atm)) thermal oxidation at an elevated temperature (e.g., at about 700 - 900° C; higher temperatures can be used for rapid thermal oxidation processes).
  • oxygen penetrates through both the TEOS layer 22.3 and the oxide layer 22.2 to grow oxide layer 22.1.
  • This growth step also densifies deposited TEOS layer 22.3.
  • the grown and deposited oxide layers have defect structures that are misaligned with respect to each other and form an interface which acts as both a stress sink and a defect trap.
  • the grown oxide 22.1 is of high dielectric quality (e.g., in terms of leakage current, breakdown strength, and charge-to-breakdown) and forms an interface with polysilicon gate stack that is relatively stress and asperity free.
  • the thicknesses of the thermal oxide layers 22.1 and 22.2, as well as the densification conditions, can be readily tailored to adjust the size of the bird's beak 10' shown in FIG. 5. That is, the size of the bird's beak is related to the time it takes to grow layers 22.1 and 22.2. Because this aspect of the invention utilizes much thinner thermal oxides than the prior art (oxide layer of FIG. 10), thermal oxidation of the gate stack 24 and of substrate 30 penetrates less in the region of the undercut (hence the bird's beak is smaller).
  • the thinner thermal oxides realized by the inventive process give rise to several other advantages: (1) the lateral diffusion of the source/drain implant under the gate edge is reduced, and (2) the reverse short channel effect (which is related to diffusion of the channel implant under the gate) is also reduced. With respect to the latter, see M. Orlowski et al, Proceedings of IEDM , pages 632-635 (1987).
  • an optional etch resistant layer 22.4 may be deposited on TEOS layer 22.3 by techniques well known in the art.
  • layer 22.4 comprises wet-etch resistant material such as about 20-60 nm (200-600 ⁇ ) of silicon nitride. Where GLDs are a problem, layer 22.4 protects the base layer structure from being attacked by subsequent wet chemical etchants (e.g., those such as HF used in cleaning steps) and hence reduces the likelihood that GLDs will be exposed.
  • GLDs unexposed is important, especially where a silicide process or a salicide process is used to form contacts, because silicides tend to form on GLDs (typically silicon particles) but not on silicon nitrides. Thus, the incidence of silicide shorts is expected to be greatly reduced.
  • the nitride layer caps the base layer structure and prevents any substantial further oxidation of the polysilicon gate stack and hence any further growth of the bird's beaks 10'.
  • an optional conformal dielectric layer 22.5 (e.g., about 150-200 nm (1500-2000 ⁇ ) of densified TEOS) may be formed over the wafer, as shown in FIG. 6.
  • the wafer is then anisotropically etched, as shown in FIG. 7, using well-known plasma etching techniques to remove all of layers 22.2, 22.3, 22.4 and 22.5 except the portions thereof which define spacers 22 adjacent gate stack 24. Quadrant-like filler region 22.5' results from this etching process.
  • this implant uses As ions at a dose of about 2-8 10 15
  • this implant uses B from a BF 2 source at a dose of about a 2-8 10 15 .
  • more heavily doped regions 28.2 are shown to be deeper than lightly doped regions 28.1, but in some devices the converse may be true.
  • Contacts are formed to the gate, source and drain using metalization techniques well known in the art.
  • the thickness of dielectric layer 22.3 may be adjusted to give the base layer the desired (e.g., increased) thickness.
  • the base layer itself forms the entire spacer since the filler region is not used.
  • FIG. 8 illustrates this approach where the composite spacer shown would result from anisotropically etching a structure of the type depicted in FIG. 5.
  • a subsequent silicide or salicide process well-known in the art would produce silicide source/drain contacts and silicide gate contact 32, but no silicide would form on nitride portions 22.4, thus isolating these contacts from one another.
  • the embodiments of the invention using a nitride cap are applicable to a "merged window" contact design in which a single window exposes both the end of a gate runner of one transistor and a portion of the drain of another transistor.
  • the nitride protects the underlying layers of the exposed spacer at the end of the runner from attack during the window-opening etch. Protecting the spacer in turn, prevents the contact metallization from directly contacting the shallow, lightly doped region.

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Claims (14)

  1. Verfahren zur Herstellung einer integrierten Schaltung umfassend
    das Ausbilden eines Gatestapels (24) mit einem Gatedielektrikum (24.1) an einem Siliciumeinkristallsubstrat (30), wobei der Stapel Seitenwände mit Silicium hat und
    Ausbilden eines Abstandsstücks (22) mit einer Basisschicht benachbart zu wenigstens einer der Seitenwände, wobei der Schritt des Bildens der Basisschicht die Schritte umfaßt:
    thermisches Aufwachsen einer ersten Oxidschicht (22.2) an der Seitenwand,
    Abscheiden einer Sauerstoff-permeablen dielektrischen Schicht (22.3) an der ersten Oxidschicht, und
    gekennzeichnet ist durch den nachfolgenden Schritt des: thermischen Aufwachsens einer zweiten Oxidschicht (22.1) zwischen dem Gatestapel und der ersten Oxidschicht durch Aussetzen der Schichten einer Sauerstoffumgebung bei einem Druck und einer Temperatur, die ausreichend sind,
    um das Eintreten von Sauerstoff durch die dielektrische Schicht und die erste Oxidschicht zu gestatten.
  2. Verfahren nach Anspruch 1,
    bei welchem die Sauerstoff-permeable dielektrische Schicht durch eine CVD-Abscheidung von TEOS abgeschieden wird und wobei die zweite Oxidschicht bei einem Druck und einer Temperatur aufgewachsen wird, die ausreichend sind, die Sauerstoff-permeable dielektrische Schicht zu verdichten.
  3. Verfahren nach Anspruch 2,
    bei welchem die thermischen Aufwachsschritte eine vogelschwanzartige Anordnung an den Kanten des Gatedielektrikums bilden und wobei die Dicke der ersten und zweiten Oxidschicht wechselseitig angepaßt sind, um die Größe der vogelschwanzartigen Anordnung zu steuern.
  4. Verfahren nach den Ansprüchen 1, 2 oder 3,
    bei welchem der Schritt des Abstandsstückbildens ferner den Schritt umfaßt des Ausbildens einer Deckschicht (22.4), die gegenüber Naßätzen, welches nachfolgend bei dem Verfahren an der Sauerstoff-permeablen dielektrischen Schicht nach dem Schritt des thermischen Aufwachsens der zweiten Oxidschicht verwendet wird, resistent ist.
  5. Verfahren nach Anspruch 4,
    bei welchem die Deckschicht Siliciumnitrit umfaßt.
  6. Verfahren nach Anspruch 4,
    bei welchem der Schritt des Bildens des Abstandsstückes ferner den Schritt des Abscheidens einer konformen Oxidschicht (22.5) über der Deckschicht umfaßt und das anisotrope Ätzen der Schichten, um so ein quadrantenähnliches Abstandsstück zu bilden.
  7. Verfahren nach Anspruch 6,
    ferner umfassend
    (1) vor dem Aufwachsen der ersten Oxidschicht die zusätzlichen Schritte des
    (a) Ausbildens beabstandeter Feldoxidbereiche (26) auf jeder Seite des Stapels,
    (b) das Ionenimplantieren von Verunreinigungen in das Substrat, um relativ schwach dotierte Bereiche (28.1) zwischen dem Stapel und den Feldoxidbereichen zu bilden und
    (2) nach dem Bilden der Abstandsstücke, die zusätzlichen Schritte des
    (a) Ionenimplantierens von Verunreinigungen in das Substrat, um stärker dotierte Sorce/Drainbereiche (28.2) zwischen den Abstandsstücken und den Feldoxidbereichen zu bilden, und
    (b) das Bilden elektrischer Kontakte zu dem Gatestapel und den Sorce/Drainbereichen.
  8. Verfahren nach Anspruch 4,
    bei welchem der Schritt des Bildens der Abstandsstücke ferner das anisotrope Ätzen der Schichten umfaßt, um so ein quadrantenähnliches Abstandsstück zu bilden und die Schichten über dem Stapel und über den Bereichen, in welchen ein Sorce und ein Drain zu bilden ist, zu entfernen.
  9. Verfahren nach Anspruch 8,
    ferner umfassend das Ausbilden einer Silicidschicht an dem Stapel und an den Bereichen.
  10. Verfahren nach Anspruch 1,
    bei welchem die zweite Oxidschicht unter Bedingungen aufgewachsen wird, die dazu beitragen, die Sauerstoff-permeable dielektrische Schicht zu verdichten.
  11. Verfahren nach Anspruch 1,
    bei welchem die Seitenwand Polysilicium umfaßt.
  12. Verfahren nach Anspruch 11,
    bei welchem eine integrierte Schaltung mit einer Konstruktionsregel von ungefähr 0,5 µm oder weniger hergestellt wird und
    bei dem Schritt des thermischen Aufwachsens der zweiten Oxidschicht der Druck und die Themperatur ausreichen, um die Sauerstoff-permeable dielektrische Schicht zu verdichten.
  13. Verfahren nach Anspruch 12,
    bei welchem die dielektrische Schicht durch eine CVD-Abscheidung von TEOS abgeschieden wird.
  14. Verfahren nach Anspruch 13,
    bei welchem die thermischen Aufwachsschritte eine vogelschwanzartige Anordnung an den Kanten des Gatedielektrikums bilden und bei welchen die Dicken der ersten und zweiten Oxidschicht wechselseitig so angepaßt sind, daß die Größe der vogelschwanzartigen Anordnung gesteuert wird.
EP92302308A 1991-03-27 1992-03-18 Verfahren zur Herstellung von Halbleiteranordnungen und integrierten Schaltkreisen mit Verwendung von Seitenwand-Abstandsstücken Expired - Lifetime EP0506287B1 (de)

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EP (1) EP0506287B1 (de)
JP (1) JP2644414B2 (de)
KR (1) KR970002266B1 (de)
DE (1) DE69217682T2 (de)
ES (1) ES2099207T3 (de)
HK (1) HK119597A (de)
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DE69217682D1 (de) 1997-04-10
JPH05121732A (ja) 1993-05-18
EP0506287A1 (de) 1992-09-30
KR970002266B1 (ko) 1997-02-27
JP2644414B2 (ja) 1997-08-25
TW203148B (de) 1993-04-01
HK119597A (en) 1997-09-05
DE69217682T2 (de) 1997-09-18
KR920018977A (ko) 1992-10-22
US5573965A (en) 1996-11-12

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