EP0000883A1 - Transistor à effet de champ à grille isolée - Google Patents

Transistor à effet de champ à grille isolée Download PDF

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Publication number
EP0000883A1
EP0000883A1 EP78100594A EP78100594A EP0000883A1 EP 0000883 A1 EP0000883 A1 EP 0000883A1 EP 78100594 A EP78100594 A EP 78100594A EP 78100594 A EP78100594 A EP 78100594A EP 0000883 A1 EP0000883 A1 EP 0000883A1
Authority
EP
European Patent Office
Prior art keywords
substrate
insulating layer
effect transistor
field effect
channel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP78100594A
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German (de)
English (en)
Other versions
EP0000883B1 (fr
Inventor
Kenneth Edward Beilstein, Jr.
Harish Narandas Kotecha
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International Business Machines Corp
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International Business Machines Corp
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Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of EP0000883A1 publication Critical patent/EP0000883A1/fr
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the invention relates to a novel field-effect transistor with reduced sensitivity of the threshold voltage to fluctuations in the voltage between the source and the substrate.
  • the efficiency of most logic circuits built from MOSFETs depends on how well they are suitable for current control.
  • the current control in turn depends on the threshold voltage, which is a function of the voltage difference between the source electrode and the substrate. Since the source voltage fluctuates in certain circuit applications with unearthed source electrodes, the voltage between the source and the substrate also fluctuates. Therefore, the threshold voltage also changes, so that the current control generated with the transistor changes.
  • the problem is to reduce the sensitivity of the threshold voltage to changes in the voltage between the source and the substrate.
  • the rate of change of the threshold voltage with respect to the voltage between the source and the substrate is generally called the substrate sensitivity of the field effect transistor designated.
  • the substrate sensitivity is a function of various factors, such as the thickness of the oxide layer, the doping of the substrate, the dielectric constant, etc.
  • the aim of the invention is therefore to reduce the fluctuations in the threshold voltage during operation by reducing the substrate sensitivity reduced, resulting in improved current control.
  • This object of the invention is achieved by the structure of a MOS field-effect transistor in which a buried layer of a dopant of the same conductivity type as the source and drain is formed in the channel region, this buried layer being designed such that the depletion zones for the PN junctions at the upper and lower boundaries of this layer merge in the middle of the buried layer, effectively forming a buried insulating layer between the sourcy and drain zones.
  • This Layer has this is that it increases the distance between the mirror image electrostatic charges in the gate electrode and the bulk of the substrate below the channel region of the MOSF E T, and thus the sensitivity of the threshold voltage to changes in the voltage applied between the source and substrate reduces the effectiveness .
  • the electrostatic interaction between the substrate and the gate electrode of an F E T can be reduced by providing an insulating layer of predetermined thickness and depth below the surface of the substrate in the channel region so that the distance between the gate electrode and those inside the mass of the substrate electrostatic charges, which occur in mirror image of the charges actually lying on the gate electrode, is effectively increased. Since the potential difference between the gate electrode and the mirror-image charges in the mass of the substrate is directly proportional to the electrostatic field strength, multiplied by the distance between them, the potential difference is increased with the same field strength, if the distance is increased . If one more charge is supplied to the gate electrode, the overall potential increase required within the substrate to maintain the charge balance increases with increasing thickness of the insulating layer. It can therefore be seen that the influence on the gate potential, which results from changes in the substrate potential, ie the electrostatic interaction, is reduced if the distance between the mirror-image charges is increased by inserting a buried insulating layer.
  • the preferred method for introducing an insulating layer is by ion implantation of a doped layer 10 of the same doping material that produces an N-type conduction as for source and drain, with a predetermined depth of X 1 -X 2 below the substrate surface in the channel region in FIG. 1A.
  • two PN junctions namely an upper PN junction 11 and a lower PN junction 13 with the surrounding P-conducting material of the substrate.
  • a depletion zone is formed in the transition area.
  • the thickness and the concentration of the implanted layer 10 are preferably chosen so that the depletion zone 12 for the upper PN junction and the depletion zone 14 for the lower PN junction 13 move so far that the intermediate layer is practically an insulating layer. Therefore, a buried insulating layer 10, which is desired to reduce the sensitivity of the threshold voltage to the substrate voltage, can be achieved by ion implantation from a layer with the same conductivity as the source and drain region in the channel region.
  • the buried doped insulating layer 10 has too high a concentration in relation to the concentration of the background doping for the substrate 2, an electrical short circuit can occur between the source 4 and the drain 6. If, on the other hand, the concentration of the buried doped insulating layer 10 is too low, there is only a negligible influence on the sensitivity of the threshold voltage with respect to the voltage between the source and the substrate. It has been found that there are critical values for the depth X 1 of the doped insulating layer 10 below the surface of the substrate 2, the thickness (X 2 -X 1 ) of the doped insulating layer 10 and its concentration, within which there is a range of reduced sensitivities the threshold voltage with respect to the voltage present between the source and the substrate. Some examples of these combinations of depth, thickness and concentration for the buried doped insulating layer 10 are shown in FIG. 3.
  • the Gaussian distribution for a deep ion implantation should be normalized for a rectangular distribution, the width of which corresponds to 2-1 / 2 times the standard deviation of the spread of the ion implant, while the dose D is the peak dose. This approximation of the Gaussian distribution is carried out in such a way that the implantation dosage is retained.
  • this analysis is performed for N-channel MOSFETs, with the corresponding changes in polarity it applies equally to P-channel MOSFETs.
  • FIG. 1B is a composite partial figure, which shows the doping profile over the channel region of FIG. 1A from the gate insulator 7 down to the mass 2 of the semiconductor substrate.
  • N a is the doping concentration of the semiconductor substrate 2.
  • the gate-source bias V GS is equal to the threshold voltage and that the substrate-source bias V is so it should be chosen that the channel depletion layer immediately below the gate insulating layer in region 1 does not merge with the depletion layer 12.
  • the implantation conditions are selected such that the depletion layers 12 and 14 do not flow into one another and that therefore the buried layer 10, which is also referred to as zone 2, the source and drain diffusions 4 and 6 for short closes. With this starting point, the condition for the non-conductive or depleted zone 2 should first be developed.
  • V sxc ' an expression for the critical substrate-source bias voltage, V sxc ', is derived, the region 16 of the substrate 2 being completely depleted (also referred to as zone 1) when this size is exceeded, so that together with the depletion zone 2 a field-effect transistor is used receives improved substrate sensitivity. If the substrate bias V sx is less than this critical value and zone 2 is depleted, then the transistor has a substrate sensitivity comparable to that of the prior art.
  • the widths of the depletion layer 12 and 14 are the same on both sides in zone 2. If depletion is to be made in Zone 2, the following applies:
  • V J changes slowly with respect to (X 2 -X 1 ) and can therefore be determined by assuming an approximate value for (X2-X1).
  • Fig. 2 essentially shows the details of Fig. 1B when zones 1, 2 and 3 are depleted.
  • V sxc, V I and V D are the voltages lying above the depleted zones 1, 2 and 3, so that the total about of the substrate source bias voltage V is equal to sx.
  • the electronic field E in the depletion zones in FIG. 2 is by Gaussian law related to those in the zone (X D - X 3 ) related charges by:
  • the depletion zone (X D - X 3 ) is, however, caused by the voltage V D , so that becomes.
  • V FB is the ribbon voltage of the transistor and C ox is the gate insulation capacitance per unit area.
  • a further flat ion implantation of suitable dosage and energy can be used to shift the threshold voltage by the amount V dosage . Since this is a very flat implantation, the improvement in substrate sensitivity achieved by the deep implantation is not affected.
  • the substrate sensitivity of the semiconductor device is given by the differentiation of equation 14:
  • This equation 18 represents the critical relationship between the dosage D, the upper limit value X 1 and the lower limit value X 2 for the buried layer 10 in the substrate 2 of FIG. 1A, which is a doping concentration N a to achieve the desired sensitivity of the threshold voltage dV T / dV sx owns.
  • FIG. 3 shows a graphical representation of the relationship between the substrate sensitivity in millivolts per volt, which is plotted against the implantation dose for phosphorus ions and various implantation energies in the range from 200 to 1000 KeV, where X is from 850 ⁇ to 9213 R and X 2 ranges from 2850 ⁇ to 13588 A.
  • X is from 850 ⁇ to 9213 R
  • X 2 ranges from 2850 ⁇ to 13588 A.
  • a semiconductor structure provided with a depletion zone is formed with a gate oxide layer 7 and a thickness of 700 A (t), with a background doping concentration N a of 7.5 x 10 atoms / cm 3 , a voltage V FB of -1.5 volts, a dosage voltage of -3.38 volts and an implantation dose of 5.3 x 10 11 a tome / cm 2 and an implant thickness for the upper limit x 1 of the buried layer of 9200 ⁇ , and for the lower limit x 2 out of 13580 ⁇ .
  • the diagram of the resulting threshold voltage as a function of the source-substrate voltage is compared with the corresponding threshold voltage as a function of the source-substrate voltage according to the prior art in FIG. 4. It can be seen that the structure constructed according to the invention has a smaller slope or a lower rate of change in the threshold voltage with respect to the source-substrate voltage, which shows that with predetermined changes in the magnitude of the source-substrate voltage there are fewer changes in the threshold voltage result in a device constructed according to the invention.
  • FIG. 5 shows the substrate sensitivity in millivolts per volt as a function of the source-substrate voltage for the improved semiconductor device with the above mentioned parameters in comparison with a semiconductor device according to the prior art. It can be seen that a semiconductor structure constructed in accordance with the invention results in a very substantial reduction in substrate sensitivity compared to the prior art.
  • a simple MOSFET inverter stage can, according to FIGS. 6A and 6B with a self-biasing MOSFET of the depletion type as a load and an active MOSFET of the enrichment type can be produced by using the semiconductor structure constructed according to the invention for the load transistor, as a result of which a considerably higher current control of the current flowing from drain to source is obtained during the switching process compared to the prior art in Fig. 6B.
  • the invention can be practiced by other methods of forming a buried insulating layer between the source and drain.
  • a multilayer silicon epitaxial insulator layer structure could be used to form the channel region of a field effect transistor according to the invention.
  • the concentration profile of the implanted insulating layer 10 can be specially shaped by a number of ion implantation stages in order to achieve an optimal profile.
EP19780100594 1977-08-31 1978-08-04 Transistor à effet de champ à grille isolée Expired EP0000883B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US82939377A 1977-08-31 1977-08-31
US829393 1977-08-31

Publications (2)

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EP0000883A1 true EP0000883A1 (fr) 1979-03-07
EP0000883B1 EP0000883B1 (fr) 1980-05-28

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EP19780100594 Expired EP0000883B1 (fr) 1977-08-31 1978-08-04 Transistor à effet de champ à grille isolée

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EP (1) EP0000883B1 (fr)
JP (1) JPS6019152B2 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2239735A (en) * 1989-12-20 1991-07-10 Sanyo Electric Co "Velocity-modulation transistor"

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58197131A (ja) * 1982-05-12 1983-11-16 Akatake Eng Kk 粉末定量供給装置
JPS58197130A (ja) * 1982-05-12 1983-11-16 Akatake Eng Kk 粉末定量供給装置
JPH01181470A (ja) * 1988-01-08 1989-07-19 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ
KR101125825B1 (ko) * 2004-07-30 2012-03-27 어드밴스드 마이크로 디바이시즈, 인코포레이티드 셀프-바이어싱 트랜지스터 구조 및 ｓｒａｍ 셀

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3283221A (en) * 1962-10-15 1966-11-01 Rca Corp Field effect transistor
US4021835A (en) * 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5280782A (en) * 1975-12-27 1977-07-06 Sony Corp Semiconductor device
JPS53141585A (en) * 1977-05-16 1978-12-09 Nec Corp Manufacture of insulating gate field effect type semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3283221A (en) * 1962-10-15 1966-11-01 Rca Corp Field effect transistor
US4021835A (en) * 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2239735A (en) * 1989-12-20 1991-07-10 Sanyo Electric Co "Velocity-modulation transistor"
GB2239735B (en) * 1989-12-20 1993-08-25 Sanyo Electric Co Velocity-modulation transistor

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Publication number Publication date
JPS5438776A (en) 1979-03-23
EP0000883B1 (fr) 1980-05-28
JPS6019152B2 (ja) 1985-05-14

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