EP0000883A1 - Insulated gate field effect transistor - Google Patents

Abstract

1. Insulation layer field effect transistor with a channel region (16) of a second conductivity type formed between source (4) and drain (6) of a first conductivity type, in a substrate (2) of the second conductivity type and an insulated gate electrode over the channel region, characterised in that a buried insulation layer (10) is provided in the substrate (2) under the channel region (16) between source (4) and drain (6) which extends into the substrate (2) the effective transistor depletion zone appearing in connection with the channel region (16), which layer (10) can be completely depleted by the application of a critical substrate-source bias Vxsc , whereby the distance between the electrostatic charges on the gate electrode and the charges induced by them in the substrate (2) is increased to such an extent that the sensivity of the threshold voltage VT relative to the changes of the substrate-source bias Vxs is reduced.

Description

The invention relates to a novel field-effect transistor with reduced sensitivity of the threshold voltage to fluctuations in the voltage between the source and the substrate.

The efficiency of most logic circuits built from MOSFETs depends on how well they are suitable for current control. The current control in turn depends on the threshold voltage, which is a function of the voltage difference between the source electrode and the substrate. Since the source voltage fluctuates in certain circuit applications with unearthed source electrodes, the voltage between the source and the substrate also fluctuates. Therefore, the threshold voltage also changes, so that the current control generated with the transistor changes. The problem is to reduce the sensitivity of the threshold voltage to changes in the voltage between the source and the substrate. The rate of change of the threshold voltage with respect to the voltage between the source and the substrate is generally called the substrate sensitivity of the field effect transistor designated. The substrate sensitivity is a function of various factors, such as the thickness of the oxide layer, the doping of the substrate, the dielectric constant, etc. The aim of the invention is therefore to reduce the fluctuations in the threshold voltage during operation by reducing the substrate sensitivity reduced, resulting in improved current control.

Many attempts have been made in the prior art to improve substrate sensitivity. For example, it has been proposed to obtain substrates with high resistivity by uniformly changing the doping concentration of the substrate because it was believed that this would also result in better capacitance. However, when using substrate with higher resistivity, difficulties arise with high packing density, such as e.g. B. channel shorts, emitter-collector breakdowns and the like. If the total background conductivity is reduced, inversions can occur in the field areas, so that the circuit does not work properly. Although some benefits can be obtained using high resistivity substrates, a significant portion of the gain is offset by the difficulties encountered.

Another attempt to achieve low substrate sensitivity is to isolate the substrate by isolating the substrate for each transistor. The manufacturing costs are extremely high, since complex processes are used for this double diffusion and the doping of two different zones must be set. In addition, this results in a lower packing density because each transistor must be isolated on its own.

It is known per se to perform a double ion implantation in the channel region of an FET, thereby displacing an implanted depletion-type junction towards the surface of the channel to solve the problem of a depletion-type transistor that would otherwise not control or can be switched off. This is achieved by double ion implantation of materials of opposite conductivity types that provide a sudden transition. However, it is not the case that simple ion implantation necessarily results in the desired reduction in substrate sensitivity.

Object of the invention

It is therefore an object of the invention to reduce the sensitivity of the threshold voltage of a MOSFET to changes in the voltage between the source and the substrate.

Overall presentation of the invention

This object of the invention is achieved by the structure of a MOS field-effect transistor in which a buried layer of a dopant of the same conductivity type as the source and drain is formed in the channel region, this buried layer being designed such that the depletion zones for the PN junctions at the upper and lower boundaries of this layer merge in the middle of the buried layer, effectively forming a buried insulating layer between the sourcy and drain zones. This Layer has this is that it increases the distance between the mirror image electrostatic charges in the gate electrode and the bulk of the substrate below the channel region of the MOSF _E T, and thus the sensitivity of the threshold voltage to changes in the voltage applied between the source and substrate reduces the effectiveness .

The invention will now be described in detail by means of embodiments in conjunction with the accompanying drawings.

• Fig. 1A eine Querschnittsansicht einer erfindungsgemäß aufgebauten Struktur und
• Fig. 1B das zugehörige Dotierungsprofil längs der Schnittlinie X-X' von Fig. 1A, jedoch um 90° gedreht,
• Fig. 2 ein Dotierungsprofil der in Fig. 1A gezeigten Struktur längs der Schnittlinie X-X' in Fig. 1A, jedoch zur Darstellung der Verarmungszonen um 90° gedreht,
• Fig. 3 eine graphische Darstellung der Substrat- empfindlichkeit in Millivolt je Volt als Funktion der Implantierungs-Dosierung für verschiedene Implantierungsenergien für den erfindungsgemäß ausgestalteten Feldeffekttransistor,
• Fig. 4 ein Diagramm zur Darstellung der Schwellwertspannung V als Funktion der zwischen Source und Substrat liegenden Spannung |V_SX| gemäß dem Stand der Technik und der Erfindung,
• Fig. 5 eine graphische Darstellung der Beziehung zwischen der Substratempfindlichkeit in Millivolt je Volt als Funktion der zwischen Source und Substrat liegenden Spannung |V_SX| gemäß dem Stand der Technik und nach der Erfindung,
• Fig. 6A verallgemeinert eine MOSFET-Inverterstufe und
• Fig. 6B ein Diagramm zur Darstellung des normalisierten Drain-Source-Stromes und der Ausgangsspannung unter Verwendung eines MOSFET gemäß Fig. 6A zur Darstellung der durch die Erfindung verbesserten Stromsteuerung.

In the drawings shows

• 1A is a cross-sectional view of a structure constructed according to the invention and
• 1B the associated doping profile along the section line XX 'of FIG. 1A, but rotated by 90 °,
• 2 shows a doping profile of the structure shown in FIG. 1A along the section line XX 'in FIG. 1A, but rotated by 90 ° to show the depletion zones,
• 3 shows a graphical representation of the substrate sensitivity in millivolts per volt as a function of the implantation dosage for different implantation energies for the field effect transistor designed according to the invention,
• 4 shows a diagram to illustrate the threshold voltage V as a function of the voltage | V _SX | between the source and the substrate according to the state of the art and the invention,
• 5 is a graphical representation of the relationship between the substrate sensitivity in millivolts per volt as a function of the voltage | V _SX | between the source and the substrate according to the state of the art and according to the invention,
• 6A generalizes a MOSFET inverter stage and
• 6B is a diagram showing the normalized drain-source current and the output voltage using a MOSFET according to FIG. 6A to show the current control improved by the invention.

The electrostatic interaction between the substrate and the gate electrode of an F _E T can be reduced by providing an insulating layer of predetermined thickness and depth below the surface of the substrate in the channel region so that the distance between the gate electrode and those inside the mass of the substrate electrostatic charges, which occur in mirror image of the charges actually lying on the gate electrode, is effectively increased. Since the potential difference between the gate electrode and the mirror-image charges in the mass of the substrate is directly proportional to the electrostatic field strength, multiplied by the distance between them, the potential difference is increased with the same field strength, if the distance is increased . If one more charge is supplied to the gate electrode, the overall potential increase required within the substrate to maintain the charge balance increases with increasing thickness of the insulating layer. It can therefore be seen that the influence on the gate potential, which results from changes in the substrate potential, ie the electrostatic interaction, is reduced if the distance between the mirror-image charges is increased by inserting a buried insulating layer.

If so high at the gate electrode
There is potential that a current begins to flow between source and drain, i.e. that the gate voltage corresponds to the threshold voltage, then a given magnitude of a voltage change in the voltage between source and substrate will have less effect on the current line in the channel region if the the intermediate insulating layer is thicker, ie if there is a greater distance between the mirror-image induced voltages in the mass of the substrate and in the gate electrode. Therefore, if an insulating layer of a predetermined thickness is introduced at a desired depth below the surface of the substrate in the channel region, the effect of changes in the substrate potential on the threshold voltage is reduced.

The preferred method for introducing an insulating layer is by ion implantation of a doped layer 10 of the same doping material that produces an N-type conduction as for source and drain, with a predetermined depth of X ₁ -X ₂ below the substrate surface in the channel region in FIG. 1A. Thereby one obtains two PN junctions, namely an upper PN junction 11 and a lower PN junction 13 with the surrounding P-conducting material of the substrate. As with all PN transitions, a depletion zone is formed in the transition area. The thickness and the concentration of the implanted layer 10 are preferably chosen so that the depletion zone 12 for the upper PN junction and the depletion zone 14 for the lower PN junction 13 move so far that the intermediate layer is practically an insulating layer. Therefore, a buried insulating layer 10, which is desired to reduce the sensitivity of the threshold voltage to the substrate voltage, can be achieved by ion implantation from a layer with the same conductivity as the source and drain region in the channel region.

It should be noted that if the buried doped insulating layer 10 has too high a concentration in relation to the concentration of the background doping for the substrate 2, an electrical short circuit can occur between the source 4 and the drain 6. If, on the other hand, the concentration of the buried doped insulating layer 10 is too low, there is only a negligible influence on the sensitivity of the threshold voltage with respect to the voltage between the source and the substrate. It has been found that there are critical values for the depth X _{1 of} the doped insulating layer 10 below the surface of the substrate 2, the thickness (X ₂ -X ₁ ) of the doped insulating layer 10 and its concentration, within which there is a range of reduced sensitivities the threshold voltage with respect to the voltage present between the source and the substrate. Some examples of these combinations of depth, thickness and concentration for the buried doped insulating layer 10 are shown in FIG. 3.

In the following, an analysis of the threshold equations with the necessary boundary conditions for an N-channel MOSFET for an improved substrate sensitivity will be given. For this analysis, the Gaussian distribution for a deep ion implantation should be normalized for a rectangular distribution, the width of which corresponds to 2-1 / 2 times the standard deviation of the spread of the ion implant, while the dose D is the peak dose. This approximation of the Gaussian distribution is carried out in such a way that the implantation dosage is retained. Although this analysis is performed for N-channel MOSFETs, with the corresponding changes in polarity it applies equally to P-channel MOSFETs.

FIG. 1B is a composite partial figure, which shows the doping profile over the channel region of FIG. 1A from the gate insulator 7 down to the mass 2 of the semiconductor substrate. N _a is the doping concentration of the semiconductor substrate 2. For the beginning of the analysis in area 1 (see also FIG. 1A), assume that the gate-source bias V _{GS is} equal to the threshold voltage and that the substrate-source bias V is so it should be chosen that the channel depletion layer immediately below the gate insulating layer in region 1 does not merge with the depletion layer 12. Furthermore, it is assumed that the implantation conditions are selected such that the depletion layers 12 and 14 do not flow into one another and that therefore the buried layer 10, which is also referred to as zone 2, the source and drain diffusions 4 and 6 for short closes. With this starting point, the condition for the non-conductive or depleted zone 2 should first be developed.

Subsequently, an expression for the critical substrate-source bias voltage, V _sxc ', is derived, the region 16 of the substrate 2 being completely depleted (also referred to as zone 1) when this size is exceeded, so that together with the depletion zone 2 a field-effect transistor is used receives improved substrate sensitivity. If the substrate bias V _{sx is} less than this critical value and zone 2 is depleted, then the transistor has a substrate sensitivity comparable to that of the prior art.

For reasons of symmetry, the widths of the depletion layer 12 and 14 are the same on both sides in zone 2. If depletion is to be made in Zone 2, the following applies:

wobei

• ε_O die Dielektrizitätskonstante des freien Raumes,
• ε_S die Dielektrizitätskonstante des Halbleitermaterials und
• q die Ladung des Elektrons
• V_J die innere Spannung über der Verarmungszone 12 oder 14 ist.

Since the two sides 11 and 13 of zone 2 are at the same potential under this condition, the depletion zones 12 and 14 are only maintained by the internal voltage across the PN diodes. It is known from the theory of step transitions that

in which

• ε _O the dielectric constant of free space,
• ε _S the dielectric constant of the semiconductor material and
• q the charge of the electron
• V _{J is} the internal voltage across depletion zone 12 or 14.

The equation applies to complete depletion of Zone 2

wobei

• k die Boltzmann-Konstante,
• T die Temperatur und
• n_i die Eigen-Trägerkonzentration des Halbleiter materials ist.

V _{J is} related to (X ₂ -X ₁ ) according to the following expression, which can be derived from any textbook on semiconductor physics and also from equation 3.

in which

• k the Boltzmann constant,
• T the temperature and
• n _{i is} the intrinsic carrier concentration of the semiconductor material.

It can be seen that V _J changes slowly with respect to (X ₂ -X ₁ ) and can therefore be determined by assuming an approximate value for (X2-X1).

mit

wobei ⌀ = das Fermi-Potential der Masse des HalbleiterMaterials ist.For a complete depletion of Zone 1:

With

where ⌀ = the Fermi potential of the mass of the semiconductor material.

die _man für |V_sxc| aus den obigen drei Ausdrücken löst, zu:

Since zone 2 is also impoverished, it follows from the charge neutrality consideration

the _ma n for | V _sxc | solves from the above three expressions:

Fig. 2 essentially shows the details of Fig. 1B when zones 1, 2 and 3 are depleted. V _sxc, V _I and V _D are the voltages lying above the depleted zones 1, 2 and 3, so that the total about of the substrate _source bias voltage V is equal to _sx.

This concludes the analysis to determine the critical conditions for depletion. The various voltage expressions that form the substrate bias and lead to an expression for the improved substrate sensitivity are then to be derived.

From the relationship between X _s and | V _sxc | we ^get the voltage drop over X _s in zone 1 towards the charges in X _s :

The electronic field E in the depletion zones in FIG. 2 (see also FIG. 1A) from the channel surface to X ₃ , which extends beyond the inner field, is by Gaussian law related to those in the zone (X _D - X ₃ ) related charges by:

This gives the voltage due to the charges between X ₃ and X _D in zone 3:

wird.The depletion zone (X _D - X ₃ ) is, however, caused by the voltage V _D , so that

becomes.

wobei V_FB die Flachbandspannung des Transistors und C_ox die Gate-Isolierkapazität je Flächeneinheit ist.As a threshold value condition one sees that

where V _{FB is} the ribbon voltage of the transistor and C _{ox is} the gate insulation capacitance per unit area.

dann ist der Ausdruck für die Schwellwertspannung gegeben durch:

für

und

Es sei darauf hingewiesen, daß in Gleichung 14, wenn D = 0

wird. Das ist aber die klassische Schwellwertspannungsgleichung, die man in jedem Handbuch über Halbleiterphysik finden kann.Convert the expression above using the approximation:

then the expression for the threshold voltage is given by:

For

and

It should be noted that in equation 14, when D = 0

becomes. But this is the classic threshold voltage equation that can be found in any manual on semiconductor physics.

If a depletion-type transistor is to be formed, a further flat ion implantation of suitable dosage and energy can be used to shift the threshold voltage by the amount V _dosage . Since this is a very flat implantation, the improvement in substrate sensitivity achieved by the deep implantation is not affected.

Diese Gleichung 18 stellt die kritische Beziehung zwischen der Dosierung D, dem oberen Grenzwert X₁ und dem unteren Grenzwert X₂ für die vergrabene Schicht 10 im Substrat 2 der Fig. 1A dar, das eine Dotierkonzentration N_a zur Erzielung der gewünschten Empfindlichkeit der Schwellwertspannung dV_T / dV_sx besitzt.The substrate sensitivity of the semiconductor device is given by the differentiation of equation 14:

This equation 18 represents the critical relationship between the dosage D, the upper limit value X ₁ and the lower limit value X ₂ for the buried layer 10 in the substrate 2 of FIG. 1A, which is a doping concentration N _a to achieve the desired sensitivity of the threshold voltage dV _T / dV _sx owns.

If D is 0, the substrate sensitivity of the transistors of the prior art results from equation 19:

für die tiefe Ionen-Implan- tation ergibt.Comparing equations 18 and 19, one immediately sees the substantial improvement in substrate sensitivity according to equation 18, which results from the presence of the expression

for the deep ion implantation.

For further explanation, FIG. 3 shows a graphical representation of the relationship between the substrate sensitivity in millivolts per volt, which is plotted against the implantation dose for phosphorus ions and various implantation energies in the range from 200 to 1000 KeV, where X is from 850 Å to 9213 R and X ₂ ranges from 2850 Å to 13588 _A. When designing, one will select the "substrate sensitivity" variable shown on the ordinate in the diagram in FIG. 3 and draw a horizontal line which intersects one or more of the curves. Each curve represents a different one Ion implantation energy for the phosphorus ions implanted through the channel area to form the buried insulating layer 10. The correct curve is then selected in accordance with the available energies of the ion implantation apparatus and the corresponding dosage for the phosphorus ions is then obtained from it given value on the abscissa.

As an example, a semiconductor structure provided with a depletion zone according to the invention is formed with a gate oxide layer 7 and a thickness of 700 A (t), with a background doping concentration N _a of 7.5 x 10 atoms / cm ³ , a voltage V _FB of -1.5 volts, a dosage voltage of -3.38 volts and an implantation dose of 5.3 x 10 ¹¹ _a tome / cm ² and an implant thickness for the upper limit x ₁ of the buried layer of 9200 Å, and for the lower limit x _{2 out} of 13580 Å. The diagram of the resulting threshold voltage as a function of the source-substrate voltage is compared with the corresponding threshold voltage as a function of the source-substrate voltage according to the prior art in FIG. 4. It can be seen that the structure constructed according to the invention has a smaller slope or a lower rate of change in the threshold voltage with respect to the source-substrate voltage, which shows that with predetermined changes in the magnitude of the source-substrate voltage there are fewer changes in the threshold voltage result in a device constructed according to the invention.

5 shows the substrate sensitivity in millivolts per volt as a function of the source-substrate voltage for the improved semiconductor device with the above mentioned parameters in comparison with a semiconductor device according to the prior art. It can be seen that a semiconductor structure constructed in accordance with the invention results in a very substantial reduction in substrate sensitivity compared to the prior art.

A simple MOSFET inverter stage can, according to FIGS. 6A and 6B with a self-biasing MOSFET of the depletion type as a load and an active MOSFET of the enrichment type can be produced by using the semiconductor structure constructed according to the invention for the load transistor, as a result of which a considerably higher current control of the current flowing from drain to source is obtained during the switching process compared to the prior art in Fig. 6B.

Although the preferred method of inserting the insulating layer has been illustrated by ion implantation, the invention can be practiced by other methods of forming a buried insulating layer between the source and drain. For example, a multilayer silicon epitaxial insulator layer structure could be used to form the channel region of a field effect transistor according to the invention.

It is known that the concentration profile of the implanted insulating layer 10 can be specially shaped by a number of ion implantation stages in order to achieve an optimal profile.

Claims (9)

1. Field effect transistor with a channel formed between the source and drain zone of a first conductivity type of the first conductivity type in a substrate of a second conductivity type and a gate electrode lying above the channel, characterized in that in the substrate (2) below the channel buried insulating layer (10) is provided which extends the depletion zone of the transistor into the substrate, as a result of which the sensitivity of the threshold voltage with respect to the substrate bias is reduced. 2. Field effect transistor according to claim 1, characterized in that
that the insulating layer (10) is a doped zone in which the depletion zones of the lower and the upper PN junction touch and thus form the buried insulating layer. 3. Field effect transistor according to claim 2, characterized

featured,
that the doped insulating layer is formed by ion implantation. 4. Field effect transistor according to claim 3, characterized
featured,
that the doped insulating layer is formed from several ion implantations. 5. Field effect transistor according to claim 1, characterized in
that the buried insulating layer (10) as an ion-implanted layer with a dopant producing the first conductivity type, with a distance X ₁ below the surface of the substrate (2) in the channel zone and between the source and drain zones (4, 6) with a thickness X ₂ - X ₁ and an ion implantation dosage of D is formed in a substrate with an interfering element concentration of N _a atoms / cm ³ , and in the finished transistor a substrate sensitivity of

provides, the relationship between X ₁ , X ₂ , D, Na and

is given by

and sensitivity

the threshold voltage to the substrate voltage by increasing the distance of the mirror-image induced charges between the gate electrode and the substrate by formation the buried insulating layer (10) from the ion-implanted layer is reduced by combining the two depletion zones of the upper and lower PN junction. 6. Field effect transistor according to claim 5, characterized
featured,
that the doped insulating layer (10) is formed by several ion implantations. 7. Field effect transistor according to claim 5, characterized
featured,
that the channel is N-conducting and
that the buried doped insulating layer (10) is formed by implantation with phosphorus ions. 8. Field effect transistor according to claim 5, characterized
featured,
that the channel is P-conducting and
that the buried doped insulating layer is formed by implantation of boron ions. 9. Field effect transistor according to claim 5, characterized
featured,
that a second ion-implanted layer of the first conductivity type is formed on the surface of the channel to form a depletion zone and that, depending on the doping of the channel, the buried insulating layer is formed by implantation of phosphorus or boron ions.

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