DE2347424A1 - METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICES - Google Patents

Description

Priority: September 20, 1972, Japan, No. 93600/1972

Process for manufacturing semiconductor devices

The invention relates to a method for manufacturing semiconductor devices, especially of MOS field effect transistors of the depletion type with P-channel.

In the latest integrated MOS semiconductor circuits, the so-called E / D circuit system has been developed, in which MOS field effect transistors of the enhancement type (enhancement = ^) with P-channel with MOS field effect transistors of the verariaung type (depletion »D) with P-channel in can be combined in a single circuit. In such a system, the depletion MOS transistor serves as a load transistor or the like. The threshold voltage V _{T of} this transistor can be controlled, which results in improvements insofar as the power requirement is reduced and the delay time of the integrated MOS semiconductor circuit can be shortened. The P-channel field effect transistors of the two types, that is to say the enhancement type and the depletion type, have to be combined in one and the same semiconductor substrate. In general, the P-channel enhancement type MOS transistor is fabricated simply by forming P-type source and drain regions in an N-type semiconductor substrate. On the other hand, the depletion MOS transistor with P-channel to form a P-channel depletion zone in production requires the doping of the 3 channel region with P-type interfering substances in order to reduce the

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to control lens voltage V_.

The use of ions has hitherto been known as a method for controlling the threshold voltage by doping impurities. As an example for the application in the manufacture of MOS field effect transistors a method has been mentioned in which to control the threshold voltage Vm of the gate region Ions are used with such an input energy that the contaminant ions only reach the channel area (John Macdougall, "Ion Implantation Offers a Bagful of Benefits for MOS », Electronics, June 22, 1970).

Before completing the present invention, the inventors themselves had further pointed out a method according to which, in order to control the gate threshold voltage V ™ by the use of ions, fluctuations in the doping amount due to the use are prevented from causing scattering or fluctuations in the thickness of the gate oxide films and the input energy in the deployment processes, whereby a high accuracy in the gate threshold voltage V ™ is achieved (essays by Mitsunori Warabisako and Shigeru Nishimatsu with the titles "Ion Injection into Semiconductor", "Lattice Defect of Semiconductor Subjected to Ion Infection ¹¹ and "Ion Injection into MOS Construction," published at the Riken Symposium held at the Physical and Chemical Research Institute in Tokyo, Japan, February 22-24, 1971, these articles also appearing on pages 11-21 of "Tlie Abstract Book for the Symposium ¹¹ published by the Physical and Chemical Research Institute .. and the Ges Society for Applied Physics, Branch of Applied Property of Electron).

In detail, the various publications have the following content. According to the conventional method in which the trailing edge of the feed impurity distribution according to curve (A) of FIG. 9 in the accompanying drawings is used, the level range V _m varies because of the

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Thickness scattering of the gate oxide films or the fluctuations of the ion input energy to a large extent. In contrast to this, the threshold voltage is subject to only slight fluctuations and can be controlled very precisely if the ions are used in such a way that the maximum value of the distribution of the Concentration of impurities by the use of ions occurs essentially on the silicon surface or within the semiconductor beyond the surface, as is illustrated by curves (B) and (C) in FIG. 9, respectively.

The inventors came up with the highly precise control method for the gate threshold voltage. V ™ on NOS Integrated Circuits of the Ξ / D type (i.e. with enrichment and depletion transistors working type). For this purpose, attempts were made to use P-type impurity ions in the channel region of an enhancement MOS transistor carried out with P-channel, whereby the following facts turned out (cf. Fig. 6):

(1) If the amount of introduced ion-use in the channel region .Störstoffe to shifts then AEIE cure \ ^r e gate voltage - drain current (V ~ - I-pq) to himself, and receives in parallel the threshold voltage Vm away. .

(2) If the amount of contaminants introduced is increased further, the Threshold voltage Vm positive values, and the operating mode of the transistor changes

turns into those of a depletion transistor.

(3) If the amount of introduced impurities is increased even further, so that the threshold voltage Vm reaches a value of approximately + 3V, a source-drain leakage current Ι-ηο _Τ occurs which is not controlled by the gate voltage leaves.

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The leakage current causes unnecessary power in the transistor consumption. In addition, e-r leads to a prevention in the Integration classes as well as disadvantages in the operation of an integrated .Circuit. The following circumstances are considered to be the cause of the generation of this leakage current. With the MOS field effect transistor is the depth, measured from the surface, within which control by means of the field effect is accomplished leaves, boundaries. This depth from the surface is commonly referred to as the maximum surface depletion layer depth (or -diclie) x, denoted by given the following expression:

where φγ is the Fermi potential, N. the concentration of contaminants,

^e "the specific inductance of the semiconductor, e the ε _t ο

Electricity constant of vacuum and q. the elementary charge mean.

Fig. 7 illustrates the impurity concentration N ^ an PN junction in the event that boron ions, i.e. the ions of a

P-type impurity element into an N-type silicon semiconductor

15 - "5 with a substrate impurity concentration N _DS = 2x10cm with an acceleration voltage of 31 KeV and an upper

11-2
surface density of 10 χ 10 cm have been used. The distribution of the substance concentration N ^ v / is calculated according to the LSS theory (the theory of Lindhard, Scharff and Schilt). The depth x. of the transition becomes about 1.700 A. As illustrated in FIG. 8, that sub-region 7 'of a P-channel 7 which lies between the maximum depth x ^ _{max of} the surface depletion layer and the depth χ. - of the transition is not controllable by the field effect of the gate zone. The above-mentioned leakage current flows through this "passage" 7 ^{T of} the P ~ line ^{3 r ps.} (According to Fig. 7, ^ _3x - = 1,000 is calculated by approximation, where it is assumed that the

17 - ^
centering Ν _Λ = 10 cm ^ and constant in depth

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As already mentioned, the partial area of the P-channel that is not controlled by the field effect of the gate zone is the cause of the leakage current.

Task of the jT.rfindirn. ^; it is to use the leakage current through ionenej.nsatz in a MOS field effect transistor of the Verarroungtyps nit P-channel to diminish. The object of the invention also includes the Threshold voltage Vm of a MOS semiconductor device accurately steer.

The method according to the invention is used to achieve this object to manufacture a semiconductor device in that at least the first step of forming a doped impurity layer of a first conductivity type is carried out so that the maximum value of the fluctuating concentration this impurity of the first conductivity type substantially on a surface part of a semiconductor substrate or in a inner region of the substrate occurs, and that the second step of using impurity ions of a second conductivity type, which is opposite to the first conductivity type, is carried out so that the fluctuating concentration of the Contaminant of the second conductivity type has its maximum in an inner part of the substrate, wherein the impurity concentration of the doped layer formed by the second step on the substrate surface has a smaller value as the impurity concentration of the doped layer formed in the first process step.

Another embodiment of the method of the present invention for manufacturing a P-channel depletion-type MOS semiconductor device is that a P-type interference doped layer is formed in an N-type semiconductor substrate which has an insulating film on its surface. that the maximum value of the contaminant concentration distribution; substantially at the interface between the substrate and the insulating film or within the maximum depth of the

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23 47 /: 2 4 '

Surface depletion layer occurs within the substrate, and that N-impurities "in an amount that is sufficient around the P-impurity concentration of the doped with the P-Störstoxf Layer in the vicinity of the maximum depth of the depletion layer to compensate, subjected to an ion use so that the Ilaxinal value of the disturbance substance distribution in the Occurs around the maximum depth of the depletion layer.

According to the embodiments mentioned, the P-type impurities are eliminated in that region within the layer doped with the P-type impurity which is deeper than the maximum depth of the depletion layer, and the new PN junction moves from the maximum depth of the depletion layer or beyond this closer to the surface. The leakage current between a source zone and a drain zone, between which there is such a layer doped with an impurity substance as a channel, is thus considerably reduced with respect to the P-impurities, which have the maximum of the impurity concentration distribution on that part of the substrate surface or in the vicinity thereof, are neglected. The gate threshold voltage Vn ₁ is hardly influenced by the use of ions on N-type impurities, which has been proven by a number of experimental results.

The invention is explained in more detail in the following description of preferred exemplary embodiments with reference to the drawings. Show in the drawings

'Fig. 1a to 1e vertical sections through a

Semiconductor device in various Stages of a manufacturing method according to the invention;

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Fig. 2 is a diagram showing curves showing the distribution the concentration of contaminants in an exemplary embodiment according to the invention demonstrate;

Fig. 3 is a vertical section through the semiconductor device of FIG. 1 according to their Completion"

■ Fig. 4a and 4b and FIGS. 5a and 5b

Diagrams with curves showing the distributions of the concentration of contaminants, each in front according to the use of contaminants (a) and after the use of contaminants (b) v / indicate further embodiments of the invention;

6 and 7 are diagrams for explaining the

basic structure according to the invention, v / obei in Fig. 6 curves are drawn, which represent the source-drain current versus the gate voltage, while the curves 7 shows the distribution of the concentration of contaminants indicate?

Fig. 8 is a vertical section through a conventional one KOS semiconductor device; and

9 is a diagram of distribution curves in FIG

Concentration of impurities when using ions to control the threshold voltage Vm from MOS semiconductor devices.

FIGS. 1a to 1e show a production method in which the present invention is based on a MOS field effect transistor of the depletion type with P-channel is applied,

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and illustrate the states of the semiconductor device at successive different stages. According to FIG. 1a, an N-type silicon substrate 1 becomes

prepared. The substrate surface is oxidized, so that a ili. '; 2 is created.

According to FIG. 1b, parts of the silicon oxide film have been removed by photoetching. Acceptors, for example boron atoms, are diffused into the exposed parts of the silicon substrate, so that a source zone 3 and a drain zone 4, each of the P ~ conduction type, are formed.

As shown in Fig. 1c, the cxide film is placed on the substrate at the point where the gate zone should exist, removed between the source and drain zones by photoetching.

Referring to FIG. 1d, the substrate is again subjected to thermal oxidation so that an oxide film 5 is formed on the exposed portion having a thickness of 1000 ^A, is to form the gate insulating film.

According to FIG. 1e, on the one hand, boron ions are inserted into the substrate 1 through the oxide film 5 and form a P-doped layer 6 in the surface region of the substrate. The acceleration voltage for the boron ions is set to 31 KeV at this moment, so that the maximum value of the distribution of the impurity concentration is substantially at the intermediate layer between the oxide film and the silicon substrate or within the substrate. In this case, the distribution curves of the P-impurity concentration have a course as shown in Fig. 2 by the dash-dotted lines (a) and; (b) is reproduced. However, the surface concentration is preferably somewhat below the maximum value of the distribution. The surface concentration can be set in a range from about 0.1 to 1. In Fig. 2, the substrate depth is denoted by χ, where χ - 0 denotes the substrate surface (cf. au'Vh F " ^: g. 1e). The maximum depth of the surface depletion layer is denoted ^{by x da in the impurity distribution} x-dmax lower lying

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Part j inverts to a P-type area and therefore becomes 'the cause of a leakage current. Thereby the P-inversion repealed by the subsequent use of phosphorus.

According to FIG. 1e, as stated, phosphorus is also inserted into the substrate through the oxide film, so that an N-doped layer is formed within the substrate. In this case, the acceleration voltage for the phosphorus ions is 163 KeV, and they are used at 1.3 × 10 ¹¹ cm " ² Phosphorus has been generated, its maximum value at the depth Xo _a as indicated by broken lines (c) and (d) in Fig. 2. At the part of the substrate surface (x = O), the impurity concentration of IT In addition, the phosphorus concentration is made sufficiently small compared to the boron concentration in a region within the maximum depth of the surface depletion layer, so that the carrier density in this region is essentially determined by the boron.

Since the impurities of the P-doped layer and those of the N-doped Layer opposite conductivity type-have, raise cie each other up. This results in concentration distribution curves, which are indicated in Fig. 2 with the solid lines (f) and (g.).

The P-impurities are canceled out by the N-impurities, which are used in such a way that the top of the distribution is close to the depth X-, ". The P-impurities are greatly reduced in their concentration, and their concentration curve '" abruptly decreases. Correspondingly, the peak of the distribution of phosphorus and N-impurities is essentially at 3C ₀ , so that a somewhat less deep area (at x '.) Is formed precisely.

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The use of the N-interfering substances allows an arrangement of the 'PN junction in a depth of about 1,000 ~ e ^A tinter the interface between the silicon oxide film and the silicon substrate. This makes it possible to design the PIT transition zone more deeply than according to the state of the art.

On the other hand, the peak of the distribution of the H-impurities introduced by the ion addition lies in an inner part of the silicon substrate beyond the interface between the Silicon oxide film and the substrate (i.e. beyond the substrate surface), so that the contaminants used have a sufficiently reduced concentration on the substrate surface. For this reason, the IT storage materials influence the distribution the P-impurity concentration in the vicinity of the silicon substrate Hardly any surface before the use of N-contaminants. In this context it should be noted that if to compensate for the uncontrollable P-channel range with a diffusion of phosphorus is worked, the impurity concentration distribution of phosphorus becomes largest on the silicon substrate surface and is there compared to the state changes considerably before the phosphorus diffuses in.

Since the threshold voltage Vm of the I! ÜS ~ field effect transistor is determined by the concentration of those carriers that are present in an area between the semiconductor _{surface and the maximum depth x, q max of} the surface depletion layer, this threshold voltage depends on the concentration of the up to this depth x . boron and phosphorus impurities used down. In the case of the present invention, the impurity concentration of phosphorus in the range mentioned is sufficiently small compared to that of boron, so that the gate threshold voltage Vm is essentially determined only by the use of boron .

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An ion deployment device is equipped with an instrument for measuring the amount deployed, such as a radiation ionitor, so that the amounts of boron and phosphorus used can be precisely controlled. Therefore, it is possible _{to control the threshold voltage Vn 1} with high accuracy. In this case, either the use of ions of the N-impurities or the doping with the P-impurities can precede the production.

Fig. 3 shows the finished state of the KOS field effect transistor produced by the above method. In Fig. the reference numeral 7 denotes a P-channel, while with 8 a a gate electrode disposed on the insulating film 5 is indicated. Electrodes and leads S, D and G are also used for connection to the source zone 3, the drain zone 4 or the gate electrode 8.

In Figs. 2 and 3 the depth is x. the location of the PN junction

after the use of phosphorus.

As explained in connection with the above embodiment, the present invention provides the following effects:

(1) The distribution of impurities in the depth direction of the semiconductor can be reduced abruptly, so that the original impurity concentration on the semiconductor surface or in their environment is hardly changed even by the use of phosphorus. Consequently the position of the PN junction can be precisely controlled. At the same time, a thin PN junction can be created.

(?.) The gate threshold voltage Vm can be control precisely.

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(35) Thanks to the effect (2), the leakage current in your depletion type MOS Földe effect transistor.

In the above exemplary embodiment, work is carried out on doping boron for controlling the threshold voltage V _{T of} an MIS field effect transistor with an ion insert; however, the present invention can also be used for doping boron in conjunction with thermal diffusion or other techniques.

Furthermore, the above exemplary embodiment has been described using a MOS field effect transistor with a P-channel; the present invention can be applied in a similar manner to an N-channel MOS field effect element. For example, in order to reduce the leakage current Ιτ ^ τ between the source and drain of a depletion MOS transistor with N-channel, for example durr.h ion use of phosphorus in the channel of an enrichment MOS transistor with N-channel using Al ₂ O, has been produced for the gate oxide film, the ion use of boron can also be carried out in the vicinity of the maximum depth x _{dmax of} the depletion layer of the channel.

In addition to controlling the threshold voltage V _{T of} an MIS field effect transistor, the present invention can also be used in the following fields:

(1) In the case of the bipolar transistor: In the case of such bipolar transistors according to the prior art, the distribution of the impurity concentration has the profile shown in FIG. 4a. The position of the base-collector _junction J Cß is subject to strong fluctuations at the manufacturing stage, so that the distributions of the frequency frequency f ™ and the current gain factor hp _{2 are} highly uneven.

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If the ion insert is carried out in such a way that the tip of the distribution moves in the vicinity of the base-collector junction J "j> , the position of the resulting base-collector junction comes to the point J'r" shown in FIG. 4b. t>> whereby the positional accuracy is increased at the same time. The non-uniformity in the distributions of and hprg can thus be reduced.

In addition, the base width w can be reduced considerably to the value ^w '>, which makes it possible to produce transistors with a high cut-off frequency and a high current gain factor.

(2.) For the diode with variable capacitance: If with such a diode with prior art variable capacitance resulting from double diffusion exhibits an excessively abrupt transition, as shown by the pollutant concentration distribution is shown in Fig. 5a, the ion insert according to the curve (c) 'of Fig. 5b is carried out, the gradient of the contaminant concentration increases. Consequently the capacity change number becomes larger, so that the sensitivity of the capacitance to voltage is enhanced.

(3) For the light emitting diode:

As explained with reference to FIG. 2 using the example of the MOS transistor, it is according to the invention possible, a very thin PH transition area to train. With such a thin FN transition area, dayrn are emitted Light rays only to a small extent

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absorbed, since the distance to the surface is smaller than according to the prior art., The radiation power is thus increased.

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Claims (2)

2347 ^ 24 Claims 1 .y Method of manufacturing a semiconductor device ;;, characterized in that in a first Method Gehritt one with an impurity of a first conductivity type doped layer is formed in which the maximum value of the concentration of impurities of the first conductivity type essentially ε.η a part of the surface of the semiconductor substrate or in an inner part of the substrate l-iest, and that in a second method step impurity ions of a second conductivity type which are opposite to the first conductivity type is used, so that the concentration of Impurities of the second conductivity type is greatest within the substrate, the concentration of impurities in the second method step formed doped layer on the substrate surface has a sufficiently smaller value than the concentration of contaminants in the first process step formed doped layer. 2. A method for producing a depletion MIS semiconductor device, characterized in that in a semiconductor substrate of a first conductivity type, which has an insulating film on its surface, ^v a doped with an impurity of a second conductivity type layer is formed, the second conductivity type to the first is opposite, and wherein the impurity concentration in the doped layer 409816/0766 • im v / es borrowed at part of the interface between the Substrate and the insulating film or in an inner part of the substrate within a maximum depth of the surfaces Depletion layer at the largest vircl, and that impurities of the aforementioned first conductivity type are introduced in this way by the use of ions be, do 3 of the. j ^ azinale Vrert of the contaminant concentration close to said maximum depth of the surface depletion layer is brought, wherein the impurities of said first conductivity type are used in an amount, which is required to reduce the concentration of impurities of the second conductivity type in the vicinity of the maximum depth of the surface amalgamation layer in the area with the contaminant of the to compensate for the second conductivity type doped layer. BAD ORIGINAL «4098 16/0766 Blank page