EP0000883B1 - Transistor à effet de champ à grille isolée - Google Patents

Transistor à effet de champ à grille isolée Download PDF

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Publication number
EP0000883B1
EP0000883B1 EP19780100594 EP78100594A EP0000883B1 EP 0000883 B1 EP0000883 B1 EP 0000883B1 EP 19780100594 EP19780100594 EP 19780100594 EP 78100594 A EP78100594 A EP 78100594A EP 0000883 B1 EP0000883 B1 EP 0000883B1
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Prior art keywords
substrate
insulation layer
field effect
effect transistor
source
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Application number
EP19780100594
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German (de)
English (en)
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EP0000883A1 (fr
Inventor
Kenneth Edward Beilstein, Jr.
Harish Narandas Kotecha
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7838—Field effect transistors with field effect produced by an insulated gate without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs

Definitions

  • the invention relates to an insulating layer field effect transistor having a channel of a second conductivity type formed between the source and drain zone of a first conductivity type in a substrate of the second conductivity type and an insulated gate electrode lying above the channel.
  • an insulating layer field effect transistor is known from US-A-4021 835.
  • the efficiency of most logic circuits built from MOSFETs depends on how well they are suitable for current control.
  • the current control in turn depends on the threshold voltage, which is a function of the voltage difference between the source electrode and the substrate. Since the source voltage fluctuates in certain circuit applications with ungrounded source electrodes, the voltage between the source and the substrate also fluctuates. Therefore, the threshold voltage also changes so that the current control generated with the transistor changes.
  • the problem is to reduce the sensitivity of the threshold voltage to changes in the voltage between the source and the substrate.
  • the rate of change of the threshold voltage with respect to the voltage between source and substrate is generally referred to as the substrate sensitivity of the field effect transistor.
  • the substrate sensitivity is a function of various factors, such as the thickness of the oxide layer, the doping of the substrate, the dielectric constant, etc. The aim has therefore been to reduce the fluctuations in the threshold voltage during operation by reducing the substrate sensitivity, which results in improved current control.
  • an insulating layer field effect transistor of the type mentioned which is characterized in that a buried insulating layer is provided in the substrate below the channel between the source and drain zones, which in the case of a by applying a critical substrate-source bias V xsc completely depleted channel existing effective depletion zone of the transistor extends deeper into the substrate, so that the distance between the electrostatic charges on the gate electrode and the charges induced by them in the substrate is increased such that the Sensitivity of the threshold voltage V, to changes in the substrate-source bias voltage V " , is reduced.
  • the arrangement is preferably such that the insulating layer is a doped insulating layer of the first conductivity type, in which the depletion zones differ from the insulating layer to the substrate educated lower and the upper formed by the insulating layer with the channel Unite the PN junction approximately in the middle of the insulation layer and thus form a coherent, impoverished area.
  • the electrostatic interaction between the substrate and the gate electrode of an FET can be reduced by providing an insulating layer of predetermined thickness and depth below the surface of the substrate below the channel, so that the distance between the gate electrode and those inside the substrate existing electrostatic charges, which occur in mirror image of the charges actually lying on the gate electrode, is effectively increased. Since the potential difference between the gate electrode and the mirror-image charges in the interior of the substrate is directly proportional to the electrostatic field strength, multiplied by the distance between them, the potential difference is increased with the same field strength, if the distance is increased. If one more charge is supplied to the gate electrode, the overall increase in potential required within the substrate to maintain the charge balance increases with increasing thickness of the insulating layer. It can therefore be seen that the influence on the gate potential which results from changes in the substrate potential, i. H. the electrostatic interaction is reduced if the distance between the mirror-image charges is increased by inserting a buried insulating layer.
  • a given magnitude of a voltage change in the voltage between source and substrate will have less of an effect on the current conduction in the channel region if the insulating layer in between is thicker, i. H. if there is a greater distance between the mirror-image induced charges inside the substrate and in the gate electrode. Therefore, if an insulating layer of a predetermined thickness is introduced at a desired depth below the surface of the substrate in the channel region, the effect of changes in the substrate potential on the threshold voltage is reduced.
  • the preferred method of introducing an insulating layer is by ion implantation of a doped insulating layer 10 of the same N-type dopant as source and drain, with a predetermined depth of X, -X, below the substrate surface in the channel region in Fig. 1A.
  • the thickness and the concentration of the implanted insulating layer 10 is preferably chosen so that the depletion zone 12 for the upper P-N junction and the depletion zone 14 for the lower P-N junction 13 move so far that the intermediate layer is practically an insulating layer. Therefore, a buried insulating layer 10, which is desired to reduce the sensitivity of the threshold voltage to the substrate voltage, can be obtained by ion implantation from a layer with the same conductivity as the source and drain region in the channel region.
  • the buried doped insulating layer 10 has too high a concentration in relation to the concentration of the background doping for the substrate 2, an electrical short circuit can occur between the source zone 4 and the drain zone 6. If, on the other hand, the concentration of the buried doped insulating layer 10 is too low, there is only a negligible influence on the sensitivity of the threshold voltage with respect to the voltage between the source and the substrate. It was found that there are critical values for the depth X, the doped insulating layer 10 below the surface of the substrate 2, the thickness (X 2 -X,) of the doped insulating layer 10 and their concentration, within which a region of reduced emp sensitivity of the threshold voltage in relation to the voltage present between the source and the substrate. Some examples of this combination of depth, thickness and concentration for the buried doped insulating layer 10 are shown in FIG. 3.
  • the Gaussian distribution for a deep ion implantation should be normalized for a rectangular distribution, the width of which corresponds to 2-1 / 2 times the standard deviation of the spread of the ion implant, while the dosage D is the peak dosage. This approximation of the Gaussian distribution is carried out in such a way that the implantation dosage is retained.
  • this analysis is performed for N-channel MOSFETs, it applies in the same way for P-channel MOSFETS with the corresponding polarity changes.
  • FIG. 1B is a composite partial figure that shows the doping profile over the channel region of FIG. 1A from the gate insulating layer 7 down to the inside of the semiconductor substrate 2.
  • N a is the doping concentration of the semiconductor substrate 2.
  • the implantation conditions are selected such that the depletion zones 12 and 14 do not flow into one another and that therefore the buried insulating layer 10, which is also referred to as zone 2, short-circuits the source zone 4 and the drain zone 6.
  • zone 2 the buried insulating layer 10, which is also referred to as zone 2, short-circuits the source zone 4 and the drain zone 6.
  • the widths X in zone 2 are the same on both sides. If depletion is to be produced in zone 2, then X N2 applies to the part of the width of a depletion zone falling in zone 2;
  • V J changes slowly with reference to (X 2 ⁇ X 1 ) and can therefore be determined by assuming an approximate value for (X 2 ⁇ X 1 ).
  • Fig. 2 essentially shows the details of Fig. 1B when zones 1, 2 and 3 are depleted.
  • V SXC , V I and V D are the voltages lying across depleted zones 1, 2 and 3, so that their total sum is approximately equal to the substrate-source bias voltage V sx .
  • the depletion zone (X D - X 3 ) is caused by the voltage V, so that becomes.
  • a further flat ion implantation of suitable dosage and energy can be used to shift the threshold voltage by the amount V dosage . Since this is a very flat implantation, the improvement in substrate sensitivity achieved by the deep implantation is not affected.
  • This equation 18 represents the critical relationship between the dosage D, the upper limit value X 1 and the lower limit value X 2 for the buried insulating layer 10 in the substrate 2 of FIG. 1A, which is a doping concentration N a to achieve the desired sensitivity of the threshold voltage dV T / dV sx owns.
  • FIG. 3 shows a graphical representation of the relationship between the substrate sensitivity in millivolts per volt, which is plotted over the implantation dose for phosphorus ions and various implantation energies in the range from 200 to 1000 KeV, where X, from 85 nm to 921.3 nm and X 2 ranges from 295 nm to 1358.8 nm.
  • X from 85 nm to 921.3 nm
  • X 2 ranges from 295 nm to 1358.8 nm.
  • Select "substrate sensitivity" in the diagram of FIG. 3 and draw a horizontal line that intersects one or more of the curves.
  • Each curve represents a different ion implantation energy for the phosphorus ions implanted through the channel area to form the buried insulating layer 10.
  • the correct curve is then selected in accordance with the available energies of the ion implantation apparatus and the result is then obtained appropriate dosage for the phosphorus ions from the value given on the abscis
  • one with a depletion zone versehe semiconductor structure according to 7 tox a thickness of 70 nm is formed, having a background doping concentration of N to the invention with a gate oxide layer. of 7.5 x 10 15 atoms / cm 3 , a voltage V FB of - 1.5 volts, a voltage dosage of -3.38 volts and an implantation dose of 5.3 x 10 "atoms / cm l and an implantation thickness for the upper limit X i of the buried insulating layer of 920 nm and for the lower limit X z of 1358 nm.
  • the diagram of the resulting threshold voltage as a function of the source-substrate voltage is compared with the corresponding threshold voltage as a function of the source-substrate voltage compared to the prior art in Fig. 4. It can be seen that the structure constructed according to the invention has a smaller slope or a lower rate of change of the threshold voltage with respect to the source-substrate voltage, whereby it is shown that with given changes in the size of the source Substrate voltage, there are less changes in threshold voltage for a device constructed in accordance with the invention.
  • FIG. 5 shows the substrate sensitivity in millivolts per volt as a function of the source-substrate voltage for the improved semiconductor device with the above-mentioned parameters in comparison with a semiconductor device according to the prior art. It can be seen that a semiconductor structure constructed according to the invention results in a very substantial reduction in substrate sensitivity compared to the prior art.
  • a simple MOSFET inverter stage can, according to FIGS. 6A and 6B with a self-biasing MOSFET of the depletion type as a load and an active MOSFET of the enrichment type can be produced by using the semiconductor structure constructed in accordance with the invention for the semiconductor structure constructed in accordance with the invention for the load transistor, as a result of which a significantly higher current control of the flowing from drain to source is achieved Receives current during the switching process compared to the prior art in Fig. 6B.
  • the invention can be practiced by other methods of forming a buried insulating layer between the source and drain.
  • a multilayer silicon epitaxial insulator layer structure could be used to form the channel region of a field effect transistor according to the invention.
  • the concentration profile of the implanted insulating layer 10 can be specially shaped by a number of ion implantation stages in order to achieve an optimal profile.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Claims (8)

1. Transistor à effet de champ à couche isolante ayant une région de canal (16) d'un second type de conductivité formée entre la source (4) et le drain (6) d'un premier type de conductivitié, dans un substrat (2) du second type de conductivité, et un porte isolée sur la région de canal, caractérisé en ce que dans le substrat (2) sous la région de canal (16) entre la source (4) et le drain (6), se trouve enterrée une couche isolante (10) qui s'étale dans le substrat (2), la zone d;'appauvrissement effective du transistor apparaissant dans la région de canal (16) qui est complètement appauvrie par l'application d'une polarisation de substrat-source critique Vxsc, de sorte que la distance entre les charges électrostatiques sur la porte et les charges qu'elles induisent dans le substrat (2) augmente à un point tel qu'il y ait réduction de la sensibilité de la tension de seuil VT relative aux changements de la polarisation de substrat-source Vxs.
2. Transistor à effet de champ à couche isolante selon la revendication 1, caractérisé en ce que la couche isolante est une couch isolante dopée (10) du premier type de conductivité où les zones d'appauvrissement de la jonction PN inférieure formée par la couche isolante (10) avec le substrat (2), et de la jonction PN supérieure formée par la couche isolante (10) avec la région de canal (16), fusionnent approximativement au milieu de la couche isolante (10) pour former ainsi une région appauvrie continue.
3. Transistor à effet de champ à couche isolante selon la revendication 2, caractérisé en ce que la couche isolante dopée (10) est formée par implantation ionique d'un dopant produisant le premier type de conductivité.
4. Transistor à effet de champ à couche isolante selon la revendication 3, caractérisé en ce que la couche isolante dopée (10) est formée à une distance s'étendant de X, à X2 sous la surface du substrat (2) avec un dosage d'implantation ionique D dans un substrat ayant une concentration d'impuretés de Na-atomes/cm3 de sorte que le transistor fini est un substrat dont la sensibilité, c'est-à-dire le rapport du changement de tension de seuil VT et du changement de polarisation de substrat-source Vx,,
Figure imgb0025
est donné par la relation
Figure imgb0026
dans laquelle:
ε0 est la constante diélectrique de l'espace libre,
εs est la constante diélectrique du matériau du substrat,
Cox est la capacité d'isolement de la porte par unité de surface,
q est la charge de l'électron, et
le potentiel de Fermi du matériau du substrat.
5. Transistor à effet de champ à couche isolante selon les revendications 3 ou 4, caractérisé en ce que la couche isolante dopée (10) est faite par plusieurs implantations ioniques.
6. Transistor à effet de champ à couche isolante selon la revendication 4, caractéisé en ce que la région de canal est de type de conductivité N, et en ce que la couche isolante dopée enterrée (10) est faite par implantation de ions phosphore.
7. Transistor à effet de champ à couche isolante selon la revendication 4, caractérisé en ce que la région de canal est de type de conductivité P, et en ce que la couche isolante dopée enterrée est faite par implantation de ions bore.
8. Transistor à effet de champ à couche isolante selon la revendication 4, caractérisé en ce que, pour former une zone d'appauvrissement, une seconde couche d'implantation ionique de premier type de conductivité est formée sur la surface du canal (16), cette couche étant implantée de ions phosphore lorsque le canal est de type de conductivité N, et de ions bore lorsque le canal est de type de conductivité P.
EP19780100594 1977-08-31 1978-08-04 Transistor à effet de champ à grille isolée Expired EP0000883B1 (fr)

Applications Claiming Priority (2)

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US82939377A 1977-08-31 1977-08-31
US829393 1977-08-31

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EP0000883B1 true EP0000883B1 (fr) 1980-05-28

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JPS58197131A (ja) * 1982-05-12 1983-11-16 Akatake Eng Kk 粉末定量供給装置
JPS58197130A (ja) * 1982-05-12 1983-11-16 Akatake Eng Kk 粉末定量供給装置
JPH01181470A (ja) * 1988-01-08 1989-07-19 Mitsubishi Electric Corp Ｍｏｓ型電界効果トランジスタ
US5225895A (en) * 1989-12-20 1993-07-06 Sanyo Electric Co., Ltd. Velocity-modulation transistor with quantum well wire layer
WO2006022915A1 (fr) * 2004-07-30 2006-03-02 Advanced Micro Devices, Inc. Structure a transistors a polarisation automatique et cellule sram

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NL299194A (fr) * 1962-10-15
US4021835A (en) * 1974-01-25 1977-05-03 Hitachi, Ltd. Semiconductor device and a method for fabricating the same
JPS5280782A (en) * 1975-12-27 1977-07-06 Sony Corp Semiconductor device
JPS53141585A (en) * 1977-05-16 1978-12-09 Nec Corp Manufacture of insulating gate field effect type semiconductor device

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EP0000883A1 (fr) 1979-03-07
JPS5438776A (en) 1979-03-23

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