DE69835203T2 - Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten - Google Patents

Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten Download PDF

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Publication number
DE69835203T2
DE69835203T2 DE69835203T DE69835203T DE69835203T2 DE 69835203 T2 DE69835203 T2 DE 69835203T2 DE 69835203 T DE69835203 T DE 69835203T DE 69835203 T DE69835203 T DE 69835203T DE 69835203 T2 DE69835203 T2 DE 69835203T2
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DE
Germany
Prior art keywords
gate
conductivity type
active area
drain regions
photoresist layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69835203T
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German (de)
English (en)
Other versions
DE69835203D1 (de
Inventor
N. Frederick Austin HAUSE
Robert Austin DAWSON
Jim H. Austin FULFORD
I. Mark Cedar Creek GARDNER
W. Mark Cedar Park MICHAEL
T. Bradley Austin MOORE
J. Derick Austin WRISTERS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
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Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE69835203D1 publication Critical patent/DE69835203D1/de
Publication of DE69835203T2 publication Critical patent/DE69835203T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69835203T 1997-04-21 1998-03-19 Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten Expired - Lifetime DE69835203T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US844924 1997-04-21
US08/844,924 US6060345A (en) 1997-04-21 1997-04-21 Method of making NMOS and PMOS devices with reduced masking steps
PCT/US1998/005516 WO1998048457A1 (en) 1997-04-21 1998-03-19 Method of making nmos and pmos devices with reduced masking steps

Publications (2)

Publication Number Publication Date
DE69835203D1 DE69835203D1 (de) 2006-08-24
DE69835203T2 true DE69835203T2 (de) 2007-07-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE69835203T Expired - Lifetime DE69835203T2 (de) 1997-04-21 1998-03-19 Herstellungsverfahren für nmos und pmos bauelemente mit reduzierte maskierungsschritten

Country Status (6)

Country Link
US (1) US6060345A (enExample)
EP (1) EP0978141B1 (enExample)
JP (1) JP2001524263A (enExample)
KR (1) KR100512029B1 (enExample)
DE (1) DE69835203T2 (enExample)
WO (1) WO1998048457A1 (enExample)

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US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
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Also Published As

Publication number Publication date
KR20010020140A (ko) 2001-03-15
KR100512029B1 (ko) 2005-09-05
JP2001524263A (ja) 2001-11-27
US6060345A (en) 2000-05-09
WO1998048457A1 (en) 1998-10-29
EP0978141A1 (en) 2000-02-09
EP0978141B1 (en) 2006-07-12
DE69835203D1 (de) 2006-08-24

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Legal Events

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8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY

8328 Change in the person/name/address of the agent

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER,