KR100512029B1 - 마스킹 단계들이 감소된 ｎｍｏｓ 및 ｐｍｏｓ 디바이스 제조 방법 - Google Patents

마스킹 단계들이 감소된 ｎｍｏｓ 및 ｐｍｏｓ 디바이스 제조 방법 Download PDF

Info

Publication number
KR100512029B1
KR100512029B1 KR10-1999-7009695A KR19997009695A KR100512029B1 KR 100512029 B1 KR100512029 B1 KR 100512029B1 KR 19997009695 A KR19997009695 A KR 19997009695A KR 100512029 B1 KR100512029 B1 KR 100512029B1
Authority
KR
South Korea
Prior art keywords
gate
conductivity type
active region
photoresist layer
low concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR10-1999-7009695A
Other languages
English (en)
Korean (ko)
Other versions
KR20010020140A (ko
Inventor
하우세프레드릭엔.
도손로버트
풀포드에이치.짐
가드너마크아이.
마이클마크더블유.
무어브래들리티.
리스터스데릭제이.
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20010020140A publication Critical patent/KR20010020140A/ko
Application granted granted Critical
Publication of KR100512029B1 publication Critical patent/KR100512029B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
KR10-1999-7009695A 1997-04-21 1998-03-19 마스킹 단계들이 감소된 ｎｍｏｓ 및 ｐｍｏｓ 디바이스 제조 방법 Expired - Fee Related KR100512029B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US8/844,924 1997-04-21
US08/844,924 1997-04-21
US08/844,924 US6060345A (en) 1997-04-21 1997-04-21 Method of making NMOS and PMOS devices with reduced masking steps
PCT/US1998/005516 WO1998048457A1 (en) 1997-04-21 1998-03-19 Method of making nmos and pmos devices with reduced masking steps

Publications (2)

Publication Number Publication Date
KR20010020140A KR20010020140A (ko) 2001-03-15
KR100512029B1 true KR100512029B1 (ko) 2005-09-05

Family

ID=25293980

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1999-7009695A Expired - Fee Related KR100512029B1 (ko) 1997-04-21 1998-03-19 마스킹 단계들이 감소된 ｎｍｏｓ 및 ｐｍｏｓ 디바이스 제조 방법

Country Status (6)

Country Link
US (1) US6060345A (enExample)
EP (1) EP0978141B1 (enExample)
JP (1) JP2001524263A (enExample)
KR (1) KR100512029B1 (enExample)
DE (1) DE69835203T2 (enExample)
WO (1) WO1998048457A1 (enExample)

Families Citing this family (62)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6821852B2 (en) * 2001-02-13 2004-11-23 Micron Technology, Inc. Dual doped gates
JP2002299469A (ja) * 2001-04-04 2002-10-11 Seiko Instruments Inc 半導体装置
US6531365B2 (en) * 2001-06-22 2003-03-11 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
KR100388464B1 (ko) * 2001-06-30 2003-06-25 주식회사 하이닉스반도체 반도체 메모리장치의 제조방법
US6642147B2 (en) 2001-08-23 2003-11-04 International Business Machines Corporation Method of making thermally stable planarizing films
JP2003179071A (ja) * 2001-10-25 2003-06-27 Sharp Corp Ｍｄｄおよび選択ｃｖｄシリサイドを用いて深いサブミクロンｃｍｏｓソース／ドレインを製造する方法
US6882013B2 (en) * 2002-01-31 2005-04-19 Texas Instruments Incorporated Transistor with reduced short channel effects and method
US6562713B1 (en) 2002-02-19 2003-05-13 International Business Machines Corporation Method of protecting semiconductor areas while exposing a gate
US20040152331A1 (en) * 2003-01-31 2004-08-05 Applied Materials, Inc. Process for etching polysilicon gates with good mask selectivity, critical dimension control, and cleanliness
KR100598033B1 (ko) * 2004-02-03 2006-07-07 삼성전자주식회사 반도체 소자의 듀얼 게이트 산화막 형성 방법
KR100800683B1 (ko) * 2006-08-31 2008-02-01 동부일렉트로닉스 주식회사 반도체 소자의 형성방법
US8431972B2 (en) * 2006-12-13 2013-04-30 Infineon Technologies Ag Semiconductor ESD device and method of making same
TW200903655A (en) * 2007-07-02 2009-01-16 Promos Technologies Inc Method of fabricating high-voltage MOS having doubled-diffused drain
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
CN101866931A (zh) * 2010-05-19 2010-10-20 中国科学院微电子研究所 半导体结构及其形成方法
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
KR101195269B1 (ko) * 2011-02-15 2012-11-14 에스케이하이닉스 주식회사 낮은 컨택저항을 갖는 반도체소자의 제조방법
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
KR101891373B1 (ko) 2011-08-05 2018-08-24 엠아이이 후지쯔 세미컨덕터 리미티드 핀 구조물을 갖는 반도체 디바이스 및 그 제조 방법
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8557647B2 (en) * 2011-09-09 2013-10-15 International Business Machines Corporation Method for fabricating field effect transistor devices with high-aspect ratio mask
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
US9431068B2 (en) 2012-10-31 2016-08-30 Mie Fujitsu Semiconductor Limited Dynamic random access memory (DRAM) with low variation transistor peripheral circuits
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
EP3131549B1 (en) * 2014-07-09 2018-03-28 Pierre Fabre Medicament A method for treating movement disorders with befiradol
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5825270A (ja) * 1981-08-07 1983-02-15 Mitsubishi Electric Corp 半導体装置の製造方法
US4599789A (en) * 1984-06-15 1986-07-15 Harris Corporation Process of making twin well VLSI CMOS
US4561170A (en) * 1984-07-02 1985-12-31 Texas Instruments Incorporated Method of making field-plate isolated CMOS devices
DE3583472D1 (de) * 1984-08-28 1991-08-22 Toshiba Kawasaki Kk Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode.
US4621412A (en) * 1984-09-17 1986-11-11 Sony Corporation Manufacturing a complementary MOSFET
JPS63196070A (ja) * 1987-02-10 1988-08-15 Sony Corp Ｃｍｏｓの製造方法
IT1225614B (it) * 1988-08-04 1990-11-22 Sgs Thomson Microelectronics Processo per la fabbricazione di dispositivi integrati cmos con lunghezze di gate ridotte e drain leggermente drogato
JPH0770727B2 (ja) * 1989-06-16 1995-07-31 日本電装株式会社 Ｍｉｓトランジスタ及び相補形ｍｉｓトランジスタの製造方法
US4956311A (en) * 1989-06-27 1990-09-11 National Semiconductor Corporation Double-diffused drain CMOS process using a counterdoping technique
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
US5282972A (en) * 1991-12-18 1994-02-01 Kelco Water Engineering, Inc. Method and apparatus for recycling R/O waste water
JP3055424B2 (ja) * 1994-04-28 2000-06-26 株式会社デンソー Ｍｉｓ型半導体装置の製造方法
US5457060A (en) * 1994-06-20 1995-10-10 Winbond Electronics Corporation Process for manufactuirng MOSFET having relatively shallow junction of doped region
US5512506A (en) * 1995-04-06 1996-04-30 Advanced Micro Devices, Inc. Lightly doped drain profile optimization with high energy implants
US5624863A (en) * 1995-07-17 1997-04-29 Micron Technology, Inc. Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate
US5686324A (en) * 1996-03-28 1997-11-11 Mosel Vitelic, Inc. Process for forming LDD CMOS using large-tilt-angle ion implantation
US5677224A (en) * 1996-09-03 1997-10-14 Advanced Micro Devices, Inc. Method of making asymmetrical N-channel and P-channel devices

Also Published As

Publication number Publication date
EP0978141B1 (en) 2006-07-12
JP2001524263A (ja) 2001-11-27
EP0978141A1 (en) 2000-02-09
DE69835203T2 (de) 2007-07-05
US6060345A (en) 2000-05-09
DE69835203D1 (de) 2006-08-24
KR20010020140A (ko) 2001-03-15
WO1998048457A1 (en) 1998-10-29

Similar Documents

Publication Publication Date Title
KR100512029B1 (ko) 마스킹 단계들이 감소된 ｎｍｏｓ 및 ｐｍｏｓ 디바이스 제조 방법
US5677224A (en) Method of making asymmetrical N-channel and P-channel devices
US5930642A (en) Transistor with buried insulative layer beneath the channel region
US5963803A (en) Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths
US5759897A (en) Method of making an asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
US5648286A (en) Method of making asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
US5656518A (en) Method for fabrication of a non-symmetrical transistor
US6096591A (en) Method of making an IGFET and a protected resistor with reduced processing steps
JP2897004B2 (ja) Ｃｍｏｓｆｅｔ製造方法
EP0465045B1 (en) Method of field effect transistor fabrication for integrated circuits
WO1998002918A1 (en) Method for fabrication of a non-symmetrical transistor
US5923982A (en) Method of making asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region using two source/drain implant steps
US5885887A (en) Method of making an igfet with selectively doped multilevel polysilicon gate
US5877050A (en) Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
US6051459A (en) Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate
US6258646B1 (en) CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
US6027964A (en) Method of making an IGFET with a selectively doped gate in combination with a protected resistor
US5827761A (en) Method of making NMOS and devices with sequentially formed gates having different gate lengths
US6027978A (en) Method of making an IGFET with a non-uniform lateral doping profile in the channel region
US5885874A (en) Method of making enhancement-mode and depletion-mode IGFETS using selective doping of a gate material
WO2009026403A2 (en) Semiconductor device formed with source/drain nitrogen implant
US5874343A (en) CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof
US5970331A (en) Method of making a plug transistor
US5770493A (en) Method of making NMOS and PMOS devices with simultaneously formed gates having different gate lengths
US5874340A (en) Method for fabrication of a non-symmetrical transistor with sequentially formed gate electrode sidewalls

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20100729

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20110826

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20110826

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000