JP2001524263A - 減じられたマスキングステップでｎｍｏｓおよびｐｍｏｓ装置を製造する方法 - Google Patents

減じられたマスキングステップでｎｍｏｓおよびｐｍｏｓ装置を製造する方法

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Publication number
JP2001524263A
JP2001524263A JP54583398A JP54583398A JP2001524263A JP 2001524263 A JP2001524263 A JP 2001524263A JP 54583398 A JP54583398 A JP 54583398A JP 54583398 A JP54583398 A JP 54583398A JP 2001524263 A JP2001524263 A JP 2001524263A
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JP
Japan
Prior art keywords
gate
active region
conductivity type
forming
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP54583398A
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English (en)
Japanese (ja)
Other versions
JP2001524263A5 (enExample
Inventor
ハウス，フレドリック・エヌ
ドーソン，ロバート
フルフォード，エイチ・ジム
ガードナー，マーク・アイ
マイケル，マーク・ダブリュ
ムーア，ブラッドリィ・ティ
リスターズ，デリック・ジェイ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2001524263A publication Critical patent/JP2001524263A/ja
Publication of JP2001524263A5 publication Critical patent/JP2001524263A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP54583398A 1997-04-21 1998-03-19 減じられたマスキングステップでｎｍｏｓおよびｐｍｏｓ装置を製造する方法 Pending JP2001524263A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/844,924 US6060345A (en) 1997-04-21 1997-04-21 Method of making NMOS and PMOS devices with reduced masking steps
US08/844,924 1997-04-21
PCT/US1998/005516 WO1998048457A1 (en) 1997-04-21 1998-03-19 Method of making nmos and pmos devices with reduced masking steps

Publications (2)

Publication Number Publication Date
JP2001524263A true JP2001524263A (ja) 2001-11-27
JP2001524263A5 JP2001524263A5 (enExample) 2005-11-10

Family

ID=25293980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54583398A Pending JP2001524263A (ja) 1997-04-21 1998-03-19 減じられたマスキングステップでｎｍｏｓおよびｐｍｏｓ装置を製造する方法

Country Status (6)

Country Link
US (1) US6060345A (enExample)
EP (1) EP0978141B1 (enExample)
JP (1) JP2001524263A (enExample)
KR (1) KR100512029B1 (enExample)
DE (1) DE69835203T2 (enExample)
WO (1) WO1998048457A1 (enExample)

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JP2002299469A (ja) * 2001-04-04 2002-10-11 Seiko Instruments Inc 半導体装置

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US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
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Also Published As

Publication number Publication date
US6060345A (en) 2000-05-09
KR100512029B1 (ko) 2005-09-05
WO1998048457A1 (en) 1998-10-29
EP0978141A1 (en) 2000-02-09
DE69835203D1 (de) 2006-08-24
DE69835203T2 (de) 2007-07-05
EP0978141B1 (en) 2006-07-12
KR20010020140A (ko) 2001-03-15

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