DE69808956D1 - Teilweise abschaltbare spannungsversorgung für integrierte schaltkreise - Google Patents

Teilweise abschaltbare spannungsversorgung für integrierte schaltkreise

Info

Publication number
DE69808956D1
DE69808956D1 DE69808956T DE69808956T DE69808956D1 DE 69808956 D1 DE69808956 D1 DE 69808956D1 DE 69808956 T DE69808956 T DE 69808956T DE 69808956 T DE69808956 T DE 69808956T DE 69808956 D1 DE69808956 D1 DE 69808956D1
Authority
DE
Germany
Prior art keywords
memory
partial
power supply
integrated circuits
disconnectable power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69808956T
Other languages
English (en)
Other versions
DE69808956T2 (de
Inventor
Brent Keeth
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE69808956D1 publication Critical patent/DE69808956D1/de
Application granted granted Critical
Publication of DE69808956T2 publication Critical patent/DE69808956T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/78Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/83Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption
    • G11C29/832Masking faults in memories by using spares or by reconfiguring using programmable devices with reduced power consumption with disconnection of faulty elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70Masking faults in memories by using spares or by reconfiguring
    • G11C29/88Masking faults in memories by using spares or by reconfiguring with partially good memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69808956T 1997-08-22 1998-08-24 Teilweise abschaltbare spannungsversorgung für integrierte schaltkreise Expired - Lifetime DE69808956T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/918,637 US5946257A (en) 1996-07-24 1997-08-22 Selective power distribution circuit for an integrated circuit
PCT/US1998/017512 WO1999010891A1 (en) 1997-08-22 1998-08-24 Selective power distribution circuit for an integrated circuit

Publications (2)

Publication Number Publication Date
DE69808956D1 true DE69808956D1 (de) 2002-11-28
DE69808956T2 DE69808956T2 (de) 2003-09-11

Family

ID=25440710

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69808956T Expired - Lifetime DE69808956T2 (de) 1997-08-22 1998-08-24 Teilweise abschaltbare spannungsversorgung für integrierte schaltkreise

Country Status (8)

Country Link
US (3) US5946257A (de)
EP (1) EP1019910B1 (de)
JP (1) JP2001514428A (de)
KR (1) KR100358670B1 (de)
AT (1) ATE226752T1 (de)
AU (1) AU9117298A (de)
DE (1) DE69808956T2 (de)
WO (1) WO1999010891A1 (de)

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CN101636837B (zh) * 2007-03-23 2011-07-27 富士通株式会社 电子装置、安装有电子装置的电子设备、安装有电子装置的物品、电子装置的制造方法
US20080291760A1 (en) * 2007-05-23 2008-11-27 Micron Technology, Inc. Sub-array architecture memory devices and related systems and methods
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US20100128447A1 (en) * 2008-11-21 2010-05-27 Tyco Electronics Corporation Memory module having voltage regulator module
US8526252B2 (en) * 2009-03-17 2013-09-03 Seagate Technology Llc Quiescent testing of non-volatile memory array
US8705281B2 (en) * 2010-04-06 2014-04-22 Intel Corporation Method and system to isolate memory modules in a solid state drive
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Also Published As

Publication number Publication date
KR100358670B1 (ko) 2002-10-31
AU9117298A (en) 1999-03-16
ATE226752T1 (de) 2002-11-15
JP2001514428A (ja) 2001-09-11
US5946257A (en) 1999-08-31
WO1999010891A1 (en) 1999-03-04
EP1019910A1 (de) 2000-07-19
US6078540A (en) 2000-06-20
KR20010023171A (ko) 2001-03-26
US6356498B1 (en) 2002-03-12
EP1019910B1 (de) 2002-10-23
DE69808956T2 (de) 2003-09-11

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Legal Events

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