DE69628963D1 - Verfahren zum Löschen eines nichtflüchtigen Halbleiterspeichers mit redundanten Zellen - Google Patents

Verfahren zum Löschen eines nichtflüchtigen Halbleiterspeichers mit redundanten Zellen

Info

Publication number
DE69628963D1
DE69628963D1 DE69628963T DE69628963T DE69628963D1 DE 69628963 D1 DE69628963 D1 DE 69628963D1 DE 69628963 T DE69628963 T DE 69628963T DE 69628963 T DE69628963 T DE 69628963T DE 69628963 D1 DE69628963 D1 DE 69628963D1
Authority
DE
Germany
Prior art keywords
erasing
semiconductor memory
volatile semiconductor
redundant cells
redundant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69628963T
Other languages
English (en)
Other versions
DE69628963T2 (de
Inventor
Takahiko Urai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Publication of DE69628963D1 publication Critical patent/DE69628963D1/de
Application granted granted Critical
Publication of DE69628963T2 publication Critical patent/DE69628963T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404—Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409—Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
DE69628963T 1995-03-10 1996-03-08 Verfahren zum Löschen eines nichtflüchtigen Halbleiterspeichers mit redundanten Zellen Expired - Fee Related DE69628963T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7985095A JP3145894B2 (ja) 1995-03-10 1995-03-10 電気的に書込み・消去可能な不揮発性半導体記憶装置
JP7985095 1995-03-10

Publications (2)

Publication Number Publication Date
DE69628963D1 true DE69628963D1 (de) 2003-08-14
DE69628963T2 DE69628963T2 (de) 2004-05-27

Family

ID=13701681

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69628963T Expired - Fee Related DE69628963T2 (de) 1995-03-10 1996-03-08 Verfahren zum Löschen eines nichtflüchtigen Halbleiterspeichers mit redundanten Zellen

Country Status (4)

Country Link
US (1) US5684747A (de)
EP (1) EP0731470B1 (de)
JP (1) JP3145894B2 (de)
DE (1) DE69628963T2 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3600424B2 (ja) * 1997-02-26 2004-12-15 株式会社東芝 半導体記憶装置
JP2005092962A (ja) 2003-09-16 2005-04-07 Renesas Technology Corp 不揮発性半導体記憶装置
US9330783B1 (en) 2014-12-17 2016-05-03 Apple Inc. Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block
US9390809B1 (en) * 2015-02-10 2016-07-12 Apple Inc. Data storage in a memory block following WL-WL short
US9529663B1 (en) 2015-12-20 2016-12-27 Apple Inc. Detection and localization of failures in 3D NAND flash memory
US9996417B2 (en) 2016-04-12 2018-06-12 Apple Inc. Data recovery in memory having multiple failure modes
US10910061B2 (en) * 2018-03-14 2021-02-02 Silicon Storage Technology, Inc. Method and apparatus for programming analog neural memory in a deep learning artificial neural network
US10762967B2 (en) 2018-06-28 2020-09-01 Apple Inc. Recovering from failure in programming a nonvolatile memory
US10755787B2 (en) 2018-06-28 2020-08-25 Apple Inc. Efficient post programming verification in a nonvolatile memory
US10936455B2 (en) 2019-02-11 2021-03-02 Apple Inc. Recovery of data failing due to impairment whose severity depends on bit-significance value
US10915394B1 (en) 2019-09-22 2021-02-09 Apple Inc. Schemes for protecting data in NVM device using small storage footprint
US11550657B1 (en) 2021-09-01 2023-01-10 Apple Inc. Efficient programming schemes in a nonvolatile memory

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2638654B2 (ja) * 1990-02-06 1997-08-06 三菱電機株式会社 半導体不揮発性記憶装置
JPH04159696A (ja) * 1990-10-22 1992-06-02 Mitsubishi Electric Corp 不揮発性半導体記憶装置
JPH04214300A (ja) * 1990-12-12 1992-08-05 Mitsubishi Electric Corp 不揮発性半導体記憶装置
US5233559A (en) * 1991-02-11 1993-08-03 Intel Corporation Row redundancy for flash memories
US5272669A (en) * 1991-02-20 1993-12-21 Sundisk Corporation Method and structure for programming floating gate memory cells
EP1168362A3 (de) * 1991-12-09 2004-09-29 Fujitsu Limited Flashspeicher mit bessere Löschbarkeit und Schaltungen dazu
JPH05182480A (ja) * 1991-12-28 1993-07-23 Sony Corp プログラマブルリードオンリメモリ
JP2716906B2 (ja) * 1992-03-27 1998-02-18 株式会社東芝 不揮発性半導体記憶装置
US5347489A (en) * 1992-04-21 1994-09-13 Intel Corporation Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy
US5327383A (en) * 1992-04-21 1994-07-05 Intel Corporation Method and circuitry for erasing a nonvolatile semiconductor memory incorporating row redundancy
JPH0676589A (ja) * 1992-07-06 1994-03-18 Sony Corp フラッシュ型ｅ２ ｐｒｏｍの消去方法
JPH0628875A (ja) * 1992-07-10 1994-02-04 Sony Corp フラッシュ型ｅ２ ｐｒｏｍの消去方法
US5357475A (en) * 1992-10-30 1994-10-18 Intel Corporation Method for detaching sectors in a flash EEPROM memory array
JPH06150674A (ja) * 1992-11-09 1994-05-31 Seiko Epson Corp 不揮発性半導体装置
JPH06275095A (ja) * 1993-03-18 1994-09-30 Fujitsu Ltd 半導体記憶装置及び冗長アドレス書込方法
US5559742A (en) * 1995-02-23 1996-09-24 Micron Technology, Inc. Flash memory having transistor redundancy

Also Published As

Publication number Publication date
EP0731470A3 (de) 1999-04-14
EP0731470B1 (de) 2003-07-09
JP3145894B2 (ja) 2001-03-12
US5684747A (en) 1997-11-04
EP0731470A2 (de) 1996-09-11
JPH08249900A (ja) 1996-09-27
DE69628963T2 (de) 2004-05-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee