DE69625740T2 - MOS-gesteuerte Leistungsanordnung mit versenktem Gate und Verfahren zur Herstellung - Google Patents

MOS-gesteuerte Leistungsanordnung mit versenktem Gate und Verfahren zur Herstellung

Info

Publication number
DE69625740T2
DE69625740T2 DE69625740T DE69625740T DE69625740T2 DE 69625740 T2 DE69625740 T2 DE 69625740T2 DE 69625740 T DE69625740 T DE 69625740T DE 69625740 T DE69625740 T DE 69625740T DE 69625740 T2 DE69625740 T2 DE 69625740T2
Authority
DE
Germany
Prior art keywords
sunken
gate
manufacture
power assembly
controlled power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69625740T
Other languages
English (en)
Other versions
DE69625740D1 (de
Inventor
Naoto Okabe
Tsuyashi Yamamoto
Mitsuhiro Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Publication of DE69625740D1 publication Critical patent/DE69625740D1/de
Application granted granted Critical
Publication of DE69625740T2 publication Critical patent/DE69625740T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
DE69625740T 1995-04-26 1996-04-25 MOS-gesteuerte Leistungsanordnung mit versenktem Gate und Verfahren zur Herstellung Expired - Lifetime DE69625740T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10234195A JP3412332B2 (ja) 1995-04-26 1995-04-26 半導体装置

Publications (2)

Publication Number Publication Date
DE69625740D1 DE69625740D1 (de) 2003-02-20
DE69625740T2 true DE69625740T2 (de) 2003-12-04

Family

ID=14324804

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69625740T Expired - Lifetime DE69625740T2 (de) 1995-04-26 1996-04-25 MOS-gesteuerte Leistungsanordnung mit versenktem Gate und Verfahren zur Herstellung

Country Status (4)

Country Link
US (1) US5925911A (de)
EP (1) EP0740352B1 (de)
JP (1) JP3412332B2 (de)
DE (1) DE69625740T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3528420B2 (ja) 1996-04-26 2004-05-17 株式会社デンソー 半導体装置およびその製造方法
JP3298472B2 (ja) * 1997-09-26 2002-07-02 関西日本電気株式会社 絶縁ゲート型半導体装置の製造方法
KR20000014215A (ko) * 1998-08-18 2000-03-06 김덕중 높은 신뢰도의 횡형 디모스 트랜지스터 및 그제조방법
JP3514178B2 (ja) 1998-09-16 2004-03-31 株式会社デンソー 半導体装置の製造方法
US6100162A (en) * 1999-05-14 2000-08-08 Micron Technology, Inc. Method of forming a circuitry isolation region within a semiconductive wafer
JP4765012B2 (ja) * 2000-02-09 2011-09-07 富士電機株式会社 半導体装置及びその製造方法
CN1315195C (zh) * 2000-02-10 2007-05-09 国际整流器有限公司 在单面上带块形连接的垂直导电倒装芯片式器件
US6657255B2 (en) * 2001-10-30 2003-12-02 General Semiconductor, Inc. Trench DMOS device with improved drain contact

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL186665C (nl) * 1980-03-10 1992-01-16 Philips Nv Halfgeleiderinrichting.
JPS57162359A (en) * 1981-03-30 1982-10-06 Toshiba Corp Semiconductor device
JPS5842274A (ja) * 1981-09-07 1983-03-11 Nippon Telegr & Teleph Corp <Ntt> 絶縁ゲ−ト型電界効果トランジスタ
US4589928A (en) * 1984-08-21 1986-05-20 At&T Bell Laboratories Method of making semiconductor integrated circuits having backside gettered with phosphorus
JPS61199666A (ja) * 1985-03-01 1986-09-04 Hitachi Cable Ltd 電界効果トランジスタ
JPS6212167A (ja) * 1985-07-10 1987-01-21 Tdk Corp 溝部を有する縦形半導体装置の製造方法
US4796073A (en) * 1986-11-14 1989-01-03 Burr-Brown Corporation Front-surface N+ gettering techniques for reducing noise in integrated circuits
JP2513055B2 (ja) * 1990-02-14 1996-07-03 日本電装株式会社 半導体装置の製造方法
JP2597412B2 (ja) * 1990-03-20 1997-04-09 三菱電機株式会社 半導体装置およびその製造方法
JPH0494576A (ja) * 1990-08-11 1992-03-26 Sharp Corp 縦型パワーｍｏｓ　ｆｅｔ
US5460985A (en) * 1991-07-26 1995-10-24 Ipics Corporation Production method of a verticle type MOSFET
IT1254799B (it) * 1992-02-18 1995-10-11 St Microelectronics Srl Transistore vdmos con migliorate caratteristiche di tenuta di tensione.
JP2948985B2 (ja) * 1992-06-12 1999-09-13 三菱電機株式会社 半導体装置
US5316959A (en) * 1992-08-12 1994-05-31 Siliconix, Incorporated Trenched DMOS transistor fabrication using six masks
JP3081739B2 (ja) * 1992-10-20 2000-08-28 三菱電機株式会社 絶縁ゲート型半導体装置及びその製造方法
JP3185441B2 (ja) * 1993-02-04 2001-07-09 株式会社日立製作所 高周波高出力電界効果トランジスタ
JP3015679B2 (ja) * 1993-09-01 2000-03-06 株式会社東芝 半導体装置およびその製造方法
US5780324A (en) * 1994-03-30 1998-07-14 Denso Corporation Method of manufacturing a vertical semiconductor device
EP0675529A3 (de) * 1994-03-30 1998-06-03 Denso Corporation Verfahren zur Herstellung von vertikalen MOS-Transistoren
US5698880A (en) * 1994-03-31 1997-12-16 Nippondenso Co., Ltd. Semiconductor device having a groove with a curved part formed on its side surface
US5470770A (en) * 1994-03-31 1995-11-28 Nippondenso Co., Ltd. Manufacturing method of semiconductor device

Also Published As

Publication number Publication date
JP3412332B2 (ja) 2003-06-03
DE69625740D1 (de) 2003-02-20
EP0740352B1 (de) 2003-01-15
EP0740352A3 (de) 1997-10-08
US5925911A (en) 1999-07-20
JPH08298266A (ja) 1996-11-12
EP0740352A2 (de) 1996-10-30

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