DE69614912D1 - Sehr schnelle mehrwertige Festwertspeicheranordnung - Google Patents

Sehr schnelle mehrwertige Festwertspeicheranordnung

Info

Publication number
DE69614912D1
DE69614912D1 DE69614912T DE69614912T DE69614912D1 DE 69614912 D1 DE69614912 D1 DE 69614912D1 DE 69614912 T DE69614912 T DE 69614912T DE 69614912 T DE69614912 T DE 69614912T DE 69614912 D1 DE69614912 D1 DE 69614912D1
Authority
DE
Germany
Prior art keywords
value read
memory arrangement
fast multi
fast
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69614912T
Other languages
English (en)
Other versions
DE69614912T2 (de
Inventor
Masazumi Ikebe
Teiichirou Nishizaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69614912D1 publication Critical patent/DE69614912D1/de
Application granted granted Critical
Publication of DE69614912T2 publication Critical patent/DE69614912T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5692—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency read-only digital stores using storage elements with more than two stable states
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563—Multilevel memory reading aspects
    • G11C2211/5632—Multilevel reading using successive approximation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
DE69614912T 1995-04-28 1996-04-29 Sehr schnelle mehrwertige Festwertspeicheranordnung Expired - Fee Related DE69614912T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10518295A JP2689948B2 (ja) 1995-04-28 1995-04-28 多値メモリセルを有する半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69614912D1 true DE69614912D1 (de) 2001-10-11
DE69614912T2 DE69614912T2 (de) 2002-04-11

Family

ID=14400542

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69614912T Expired - Fee Related DE69614912T2 (de) 1995-04-28 1996-04-29 Sehr schnelle mehrwertige Festwertspeicheranordnung

Country Status (6)

Country Link
US (1) US5721701A (de)
EP (1) EP0740305B1 (de)
JP (1) JP2689948B2 (de)
KR (1) KR100238741B1 (de)
DE (1) DE69614912T2 (de)
TW (1) TW291562B (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6222762B1 (en) * 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US5903495A (en) * 1996-03-18 1999-05-11 Kabushiki Kaisha Toshiba Semiconductor device and memory system
DE69627318T2 (de) * 1996-08-22 2004-02-12 Stmicroelectronics S.R.L., Agrate Brianza Mehrpegelige nichtflüchtige Speicheranordnung
US6857099B1 (en) 1996-09-18 2005-02-15 Nippon Steel Corporation Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
JP3204119B2 (ja) * 1996-09-30 2001-09-04 日本電気株式会社 不揮発性半導体メモリおよびそのデータ書込方法
JP2978813B2 (ja) * 1997-02-27 1999-11-15 日本電気アイシーマイコンシステム株式会社 半導体記憶回路
US5973957A (en) * 1997-09-16 1999-10-26 Intel Corporation Sense amplifier comprising a preamplifier and a differential input latch for flash memories
JPH11213691A (ja) * 1998-01-20 1999-08-06 Toshiba Corp 不揮発性半導体記憶装置
US6038166A (en) * 1998-04-01 2000-03-14 Invox Technology High resolution multi-bit-per-cell memory
US5973958A (en) * 1998-06-23 1999-10-26 Advanced Micro Devices, Inc. Interlaced storage and sense technique for flash multi-level devices
US6178114B1 (en) * 1999-01-12 2001-01-23 Macronix International Co., Ltd. Sensing apparatus and method for fetching multi-level cell data
JP3206591B2 (ja) 1999-02-08 2001-09-10 日本電気株式会社 多値マスクｒｏｍおよび多値マスクｒｏｍの読み出し方法
JP4023953B2 (ja) 1999-06-22 2007-12-19 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US6707713B1 (en) 2000-03-01 2004-03-16 Advanced Micro Devices, Inc. Interlaced multi-level memory
JP2001312898A (ja) 2000-04-28 2001-11-09 Mitsubishi Electric Corp しきい値解析システムおよびしきい値解析方法
US6483743B1 (en) 2001-06-18 2002-11-19 Intel Corporation Multilevel cell memory architecture
ITMI20022531A1 (it) * 2002-11-28 2004-05-29 St Microelectronics Srl Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione
US7132350B2 (en) 2003-07-21 2006-11-07 Macronix International Co., Ltd. Method for manufacturing a programmable eraseless memory
US20050035429A1 (en) * 2003-08-15 2005-02-17 Yeh Chih Chieh Programmable eraseless memory
US7180123B2 (en) * 2003-07-21 2007-02-20 Macronix International Co., Ltd. Method for programming programmable eraseless memory
US7463514B1 (en) 2007-06-21 2008-12-09 Intel Corporation Multi-level cell serial-parallel sense scheme for non-volatile flash memory
US8064253B2 (en) * 2009-09-15 2011-11-22 Toshiba America Research, Inc. Multi-valued ROM using carbon-nanotube and nanowire FET

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5846798B2 (ja) * 1976-12-27 1983-10-18 富士通株式会社 半導体記憶装置
GB2157489A (en) * 1984-03-23 1985-10-23 Hitachi Ltd A semiconductor integrated circuit memory device
JPS62223896A (ja) * 1986-03-26 1987-10-01 Seiko Epson Corp 多値レベル読取り専用メモリ
JP2586729B2 (ja) * 1990-11-19 1997-03-05 日本電気株式会社 半導体記憶装置
US5218569A (en) * 1991-02-08 1993-06-08 Banks Gerald J Electrically alterable non-volatile memory with n-bits per memory cell
US5497354A (en) * 1994-06-02 1996-03-05 Intel Corporation Bit map addressing schemes for flash memory

Also Published As

Publication number Publication date
EP0740305A3 (de) 1998-07-29
EP0740305A2 (de) 1996-10-30
JPH08297982A (ja) 1996-11-12
KR100238741B1 (ko) 2000-01-15
TW291562B (de) 1996-11-21
DE69614912T2 (de) 2002-04-11
US5721701A (en) 1998-02-24
JP2689948B2 (ja) 1997-12-10
KR960038619A (ko) 1996-11-21
EP0740305B1 (de) 2001-09-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee