ITMI20022531A1 - Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione - Google Patents

Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione

Info

Publication number
ITMI20022531A1
ITMI20022531A1 IT002531A ITMI20022531A ITMI20022531A1 IT MI20022531 A1 ITMI20022531 A1 IT MI20022531A1 IT 002531 A IT002531 A IT 002531A IT MI20022531 A ITMI20022531 A IT MI20022531A IT MI20022531 A1 ITMI20022531 A1 IT MI20022531A1
Authority
IT
Italy
Prior art keywords
programming
memory cells
volatile memory
level non
circuit
Prior art date
Application number
IT002531A
Other languages
English (en)
Inventor
Emanuele Confalonieri
Gatto Nicola Del
Marco Ferrario
Francesco Mastroiani
Original Assignee
St Microelectronics Srl
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by St Microelectronics Srl filed Critical St Microelectronics Srl
Priority to IT002531A priority Critical patent/ITMI20022531A1/it
Priority to US10/724,023 priority patent/US6934185B2/en
Publication of ITMI20022531A1 publication Critical patent/ITMI20022531A1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification
IT002531A 2002-11-28 2002-11-28 Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione ITMI20022531A1 (it)

Priority Applications (2)

Application Number Priority Date Filing Date Title
IT002531A ITMI20022531A1 (it) 2002-11-28 2002-11-28 Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione
US10/724,023 US6934185B2 (en) 2002-11-28 2003-11-26 Programming method for non volatile multilevel memory cells and corresponding programming circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT002531A ITMI20022531A1 (it) 2002-11-28 2002-11-28 Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione

Publications (1)

Publication Number Publication Date
ITMI20022531A1 true ITMI20022531A1 (it) 2004-05-29

Family

ID=32983194

Family Applications (1)

Application Number Title Priority Date Filing Date
IT002531A ITMI20022531A1 (it) 2002-11-28 2002-11-28 Metodo di programmazione di celle di memoria non volatile multilivello e relativo circuito di programmazione

Country Status (2)

Country Link
US (1) US6934185B2 (it)
IT (1) ITMI20022531A1 (it)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10062445B2 (en) * 2016-12-02 2018-08-28 Globalfoundries Inc. Parallel programming of one time programmable memory array for reduced test time

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2689948B2 (ja) * 1995-04-28 1997-12-10 日本電気株式会社 多値メモリセルを有する半導体記憶装置
DE69927967T2 (de) * 1999-08-03 2006-07-27 Stmicroelectronics S.R.L., Agrate Brianza Programmierungverfahren eines nichtflüchtigen Multibit Speichers durch Regelung der Gatespannung

Also Published As

Publication number Publication date
US6934185B2 (en) 2005-08-23
US20040190336A1 (en) 2004-09-30

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