DE69602073T2 - Halbleiterspeicheranordnung vom synchronen Typ, insbesondere für Hochfrequenzsystemtakt - Google Patents

Halbleiterspeicheranordnung vom synchronen Typ, insbesondere für Hochfrequenzsystemtakt

Info

Publication number
DE69602073T2
DE69602073T2 DE69602073T DE69602073T DE69602073T2 DE 69602073 T2 DE69602073 T2 DE 69602073T2 DE 69602073 T DE69602073 T DE 69602073T DE 69602073 T DE69602073 T DE 69602073T DE 69602073 T2 DE69602073 T2 DE 69602073T2
Authority
DE
Germany
Prior art keywords
semiconductor memory
system clock
frequency system
memory arrangement
synchronous type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69602073T
Other languages
English (en)
Other versions
DE69602073D1 (de
Inventor
Tomio Suzuki
Shigeru Mori
Takayuki Miyamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Application granted granted Critical
Publication of DE69602073D1 publication Critical patent/DE69602073D1/de
Publication of DE69602073T2 publication Critical patent/DE69602073T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
DE69602073T 1995-12-28 1996-08-01 Halbleiterspeicheranordnung vom synchronen Typ, insbesondere für Hochfrequenzsystemtakt Expired - Fee Related DE69602073T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7343511A JPH09180435A (ja) 1995-12-28 1995-12-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE69602073D1 DE69602073D1 (de) 1999-05-20
DE69602073T2 true DE69602073T2 (de) 1999-10-14

Family

ID=18362087

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69602073T Expired - Fee Related DE69602073T2 (de) 1995-12-28 1996-08-01 Halbleiterspeicheranordnung vom synchronen Typ, insbesondere für Hochfrequenzsystemtakt

Country Status (7)

Country Link
US (1) US5703829A (de)
EP (1) EP0782142B1 (de)
JP (1) JPH09180435A (de)
KR (1) KR100256467B1 (de)
CN (1) CN1156887A (de)
DE (1) DE69602073T2 (de)
TW (1) TW289824B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10106257A (ja) * 1996-09-06 1998-04-24 Texas Instr Inc <Ti> 集積回路のメモリ装置及びプリチャージ動作を与える方法
KR100245078B1 (ko) * 1996-11-15 2000-02-15 김영환 고속 버스트 제어 방법 및 장치
JP4221764B2 (ja) * 1997-04-25 2009-02-12 沖電気工業株式会社 半導体記憶装置
KR100477327B1 (ko) * 1997-06-11 2005-07-07 삼성전자주식회사 동기디램용다이나믹클럭발생회로
US5862072A (en) * 1997-08-22 1999-01-19 Micron Technology, Inc. Memory array architecture and method for dynamic cell plate sensing
JPH1186547A (ja) * 1997-08-30 1999-03-30 Toshiba Corp 半導体集積回路装置
JP2000067577A (ja) 1998-06-10 2000-03-03 Mitsubishi Electric Corp 同期型半導体記憶装置
JP4216415B2 (ja) * 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
KR100378191B1 (ko) * 2001-01-16 2003-03-29 삼성전자주식회사 고주파 동작을 위한 레이턴시 제어회로 및 제어방법과이를구비하는 동기식 반도체 메모리장치
US7242624B2 (en) 2005-06-14 2007-07-10 Qualcomm Incorporated Methods and apparatus for reading a full-swing memory array

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2555900B2 (ja) * 1990-02-06 1996-11-20 日本電気株式会社 半導体メモリの出力制御回路
JPH03237680A (ja) * 1990-02-13 1991-10-23 Mitsubishi Electric Corp 半導体メモリ装置
KR920004417B1 (ko) * 1990-07-09 1992-06-04 삼성전자 주식회사 낮은 동작 전류를 갖는 sam 데이터 억세스회로 및 그 방법
JPH04263191A (ja) * 1991-02-18 1992-09-18 Nec Corp 半導体記憶装置
JPH0520868A (ja) * 1991-07-10 1993-01-29 Toshiba Corp メモリアクセス方法
US5278803A (en) * 1991-09-11 1994-01-11 Compaq Computer Corporation Memory column address strobe buffer and synchronization and data latch interlock
JPH07192470A (ja) * 1993-03-08 1995-07-28 Nec Ic Microcomput Syst Ltd 半導体メモリの出力回路
KR940026946A (ko) * 1993-05-12 1994-12-10 김광호 데이타출력 확장방법과 이를 통한 신뢰성있는 유효데이타의 출력이 이루어지는 반도체집적회로
JP3277603B2 (ja) * 1993-05-19 2002-04-22 富士通株式会社 半導体記憶装置
US5349566A (en) * 1993-05-19 1994-09-20 Micron Semiconductor, Inc. Memory device with pulse circuit for timing data output, and method for outputting data
KR950014086B1 (ko) * 1993-11-11 1995-11-21 현대전자산업주식회사 반도체 메모리 소자의 데이타 출력장치
US5402388A (en) * 1993-12-16 1995-03-28 Mosaid Technologies Incorporated Variable latency scheme for synchronous memory
JPH07182864A (ja) * 1993-12-21 1995-07-21 Mitsubishi Electric Corp 半導体記憶装置
US5452261A (en) * 1994-06-24 1995-09-19 Mosel Vitelic Corporation Serial address generator for burst memory

Also Published As

Publication number Publication date
EP0782142B1 (de) 1999-04-14
KR970051300A (ko) 1997-07-29
TW289824B (en) 1996-11-01
EP0782142A1 (de) 1997-07-02
CN1156887A (zh) 1997-08-13
KR100256467B1 (ko) 2000-05-15
US5703829A (en) 1997-12-30
DE69602073D1 (de) 1999-05-20
JPH09180435A (ja) 1997-07-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee