DE69430525D1 - Niedrige Verlustleistungsinitialisierungsschaltung, insbesondere für Speicherregister - Google Patents

Niedrige Verlustleistungsinitialisierungsschaltung, insbesondere für Speicherregister

Info

Publication number
DE69430525D1
DE69430525D1 DE69430525T DE69430525T DE69430525D1 DE 69430525 D1 DE69430525 D1 DE 69430525D1 DE 69430525 T DE69430525 T DE 69430525T DE 69430525 T DE69430525 T DE 69430525T DE 69430525 D1 DE69430525 D1 DE 69430525D1
Authority
DE
Germany
Prior art keywords
low power
power dissipation
initialization circuit
memory registers
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69430525T
Other languages
English (en)
Other versions
DE69430525T2 (de
Inventor
Pierangelo Confalonieri
Germano Nicollini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE69430525D1 publication Critical patent/DE69430525D1/de
Publication of DE69430525T2 publication Critical patent/DE69430525T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356008—Bistable circuits ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
    • H03K2217/0036—Means reducing energy consumption
DE69430525T 1994-05-31 1994-05-31 Niedrige Verlustleistungsinitialisierungsschaltung, insbesondere für Speicherregister Expired - Fee Related DE69430525T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94830264A EP0685847B1 (de) 1994-05-31 1994-05-31 Niedrige Verlustleistungsinitialisierungsschaltung, insbesondere für Speicherregister

Publications (2)

Publication Number Publication Date
DE69430525D1 true DE69430525D1 (de) 2002-06-06
DE69430525T2 DE69430525T2 (de) 2002-11-28

Family

ID=8218455

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69430525T Expired - Fee Related DE69430525T2 (de) 1994-05-31 1994-05-31 Niedrige Verlustleistungsinitialisierungsschaltung, insbesondere für Speicherregister

Country Status (4)

Country Link
US (1) US5638330A (de)
EP (1) EP0685847B1 (de)
JP (1) JP3658042B2 (de)
DE (1) DE69430525T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5936447A (en) * 1997-01-02 1999-08-10 Texas Instruments Incorporated Power-up input bias circuit and method
JP3963990B2 (ja) * 1997-01-07 2007-08-22 株式会社ルネサステクノロジ 内部電源電圧発生回路
US6084446A (en) * 1998-03-30 2000-07-04 Macronix International Co., Ltd. Power on reset circuit
JP3523593B2 (ja) * 1998-03-30 2004-04-26 マクロニクス インターナショナル カンパニー リミテッド 改良型パワー・オン・リセット回路
US6097225A (en) * 1998-07-14 2000-08-01 National Semiconductor Corporation Mixed signal circuit with analog circuits producing valid reference signals
US6909659B2 (en) * 2001-08-30 2005-06-21 Micron Technology, Inc. Zero power chip standby mode
KR101283540B1 (ko) * 2007-12-14 2013-07-15 삼성전자주식회사 스탠바이 불량(ｓｔａｎｄｂｙ ｆａｉｌ)을 감소시킨반도체 메모리 장치 및 반도체 장치
JP4877282B2 (ja) * 2008-06-12 2012-02-15 株式会社デンソー パワーオンリセット回路
US8680901B2 (en) * 2012-08-06 2014-03-25 Texas Instruments Incorporated Power on reset generation circuits in integrated circuits
KR20140122567A (ko) * 2013-04-10 2014-10-20 에스케이하이닉스 주식회사 파워 온 리셋 회로를 포함하는 반도체 장치
US10566969B2 (en) * 2017-08-28 2020-02-18 Rolls-Royce Corporation Analog power-up reset circuit for logic level reset

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4591745A (en) * 1984-01-16 1986-05-27 Itt Corporation Power-on reset pulse generator
JPH0693616B2 (ja) * 1986-07-21 1994-11-16 沖電気工業株式会社 リセツト回路
JP2772522B2 (ja) * 1987-11-06 1998-07-02 日本電気アイシーマイコンシステム 株式会社 パワーオン信号発生回路
JPH01280923A (ja) * 1988-05-07 1989-11-13 Mitsubishi Electric Corp 半導体集積回路装置
US4996453A (en) * 1989-07-28 1991-02-26 Dallas Semiconductor Power down circuit for low-power circuit with dual supply voltages
JPH0474015A (ja) * 1990-07-13 1992-03-09 Mitsubishi Electric Corp 半導体集積回路装置
US5148051A (en) * 1990-12-14 1992-09-15 Dallas Semiconductor Corporation Power up circuit
US5166545A (en) * 1991-07-10 1992-11-24 Dallas Semiconductor Corporation Power-on-reset circuit including integration capacitor
IT1252334B (it) * 1991-11-26 1995-06-08 Sgs Thomson Microelectronics Circuito di inizializazzione particolarmente per registri di memoria

Also Published As

Publication number Publication date
DE69430525T2 (de) 2002-11-28
JP3658042B2 (ja) 2005-06-08
EP0685847B1 (de) 2002-05-02
JPH0856144A (ja) 1996-02-27
US5638330A (en) 1997-06-10
EP0685847A1 (de) 1995-12-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee