DE69528930T2 - Serielle Zugriffspeicherschaltung durch eine beliebige Adresse - Google Patents

Serielle Zugriffspeicherschaltung durch eine beliebige Adresse

Info

Publication number
DE69528930T2
DE69528930T2 DE69528930T DE69528930T DE69528930T2 DE 69528930 T2 DE69528930 T2 DE 69528930T2 DE 69528930 T DE69528930 T DE 69528930T DE 69528930 T DE69528930 T DE 69528930T DE 69528930 T2 DE69528930 T2 DE 69528930T2
Authority
DE
Germany
Prior art keywords
address
access memory
memory circuit
serial access
serial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69528930T
Other languages
English (en)
Other versions
DE69528930D1 (de
Inventor
Hiroshi Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69528930D1 publication Critical patent/DE69528930D1/de
Application granted granted Critical
Publication of DE69528930T2 publication Critical patent/DE69528930T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
DE69528930T 1994-06-28 1995-06-26 Serielle Zugriffspeicherschaltung durch eine beliebige Adresse Expired - Lifetime DE69528930T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6146349A JP2982618B2 (ja) 1994-06-28 1994-06-28 メモリ選択回路

Publications (2)

Publication Number Publication Date
DE69528930D1 DE69528930D1 (de) 2003-01-09
DE69528930T2 true DE69528930T2 (de) 2003-09-25

Family

ID=15405706

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69528930T Expired - Lifetime DE69528930T2 (de) 1994-06-28 1995-06-26 Serielle Zugriffspeicherschaltung durch eine beliebige Adresse

Country Status (5)

Country Link
US (1) US5815460A (de)
EP (1) EP0690450B1 (de)
JP (1) JP2982618B2 (de)
KR (1) KR0167629B1 (de)
DE (1) DE69528930T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3247603B2 (ja) * 1996-02-05 2002-01-21 インターナショナル・ビジネス・マシーンズ・コーポレーション プレデコーダ回路及びデコーダ回路
TW378330B (en) * 1997-06-03 2000-01-01 Fujitsu Ltd Semiconductor memory device
JP3271591B2 (ja) * 1998-09-30 2002-04-02 日本電気株式会社 半導体記憶装置
KR100301047B1 (ko) * 1998-10-02 2001-09-06 윤종용 2비트프리페치용칼럼어드레스디코더를갖는반도체메모리장치
US6205084B1 (en) * 1999-12-20 2001-03-20 Fujitsu Limited Burst mode flash memory
KR100390238B1 (ko) 2001-05-18 2003-07-07 주식회사 하이닉스반도체 뱅크 어드레스를 이용한 반도체 메모리 소자의 어드레스제어 장치
US6775759B2 (en) * 2001-12-07 2004-08-10 Micron Technology, Inc. Sequential nibble burst ordering for data
KR100468719B1 (ko) 2002-01-11 2005-01-29 삼성전자주식회사 Ｎ 비트 프리페치 방식과 2ｎ 버스트 길이를 지원할 수있는 반도체 메모리 장치
JP2004164769A (ja) 2002-11-14 2004-06-10 Renesas Technology Corp 半導体記憶装置
US20040194500A1 (en) * 2003-04-03 2004-10-07 Broadway Entertainment, Inc. Article of jewelry

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577189A (en) * 1969-01-15 1971-05-04 Ibm Apparatus and method in a digital computer for allowing improved program branching with branch anticipation reduction of the number of branches, and reduction of branch delays
DE69030905T2 (de) * 1989-08-28 1998-01-29 Nec Corp Mikroprozessor mit Pipeline-Predecodereinheit und -Hauptdecodereinheit
JP2799042B2 (ja) * 1990-06-08 1998-09-17 株式会社東芝 半導体記憶装置
KR100214435B1 (ko) * 1990-07-25 1999-08-02 사와무라 시코 동기식 버스트 엑세스 메모리
US5345573A (en) * 1991-10-04 1994-09-06 Bull Hn Information Systems Inc. High speed burst read address generation with high speed transfer
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
JP3231842B2 (ja) * 1992-06-23 2001-11-26 株式会社 沖マイクロデザイン シリアルアクセスメモリ
JPH0636560A (ja) * 1992-07-21 1994-02-10 Mitsubishi Electric Corp 半導体記憶装置
JP2825401B2 (ja) * 1992-08-28 1998-11-18 株式会社東芝 半導体記憶装置
JPH06290582A (ja) * 1993-04-02 1994-10-18 Nec Corp 半導体記憶装置
JP3080520B2 (ja) * 1993-09-21 2000-08-28 富士通株式会社 シンクロナスｄｒａｍ
US5452261A (en) * 1994-06-24 1995-09-19 Mosel Vitelic Corporation Serial address generator for burst memory

Also Published As

Publication number Publication date
DE69528930D1 (de) 2003-01-09
JP2982618B2 (ja) 1999-11-29
EP0690450A2 (de) 1996-01-03
JPH0817184A (ja) 1996-01-19
KR960002010A (ko) 1996-01-26
EP0690450B1 (de) 2002-11-27
US5815460A (en) 1998-09-29
EP0690450A3 (de) 1996-02-07
KR0167629B1 (ko) 1999-01-15

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP