DE69516328T2 - Integrierte Halbleiterschaltung zur Erzeugung einer internen Speisespannung mit reduzierten Spannungsschwankungen - Google Patents

Integrierte Halbleiterschaltung zur Erzeugung einer internen Speisespannung mit reduzierten Spannungsschwankungen

Info

Publication number
DE69516328T2
DE69516328T2 DE69516328T DE69516328T DE69516328T2 DE 69516328 T2 DE69516328 T2 DE 69516328T2 DE 69516328 T DE69516328 T DE 69516328T DE 69516328 T DE69516328 T DE 69516328T DE 69516328 T2 DE69516328 T2 DE 69516328T2
Authority
DE
Germany
Prior art keywords
generating
semiconductor circuit
integrated semiconductor
internal supply
supply voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69516328T
Other languages
English (en)
Other versions
DE69516328D1 (de
Inventor
Tetsuya Kaneko
Takashi Ohsawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE69516328D1 publication Critical patent/DE69516328D1/de
Application granted granted Critical
Publication of DE69516328T2 publication Critical patent/DE69516328T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
DE69516328T 1994-02-25 1995-02-24 Integrierte Halbleiterschaltung zur Erzeugung einer internen Speisespannung mit reduzierten Spannungsschwankungen Expired - Fee Related DE69516328T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP02831394A JP3155879B2 (ja) 1994-02-25 1994-02-25 半導体集積回路装置

Publications (2)

Publication Number Publication Date
DE69516328D1 DE69516328D1 (de) 2000-05-25
DE69516328T2 true DE69516328T2 (de) 2000-09-21

Family

ID=12245135

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69516328T Expired - Fee Related DE69516328T2 (de) 1994-02-25 1995-02-24 Integrierte Halbleiterschaltung zur Erzeugung einer internen Speisespannung mit reduzierten Spannungsschwankungen

Country Status (6)

Country Link
US (1) US5592421A (de)
EP (1) EP0669619B1 (de)
JP (1) JP3155879B2 (de)
KR (1) KR100241209B1 (de)
CN (1) CN1040377C (de)
DE (1) DE69516328T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559707B1 (en) 2001-12-06 2003-05-06 Hynix Semiconductor Inc. Bootstrap circuit

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GB2296586A (en) * 1994-12-23 1996-07-03 At & T Corp Transition assist for fast row driver-decoder
KR0165386B1 (ko) * 1995-04-24 1999-02-01 김광호 반도체장치의 내부 승압회로
JP3199987B2 (ja) 1995-08-31 2001-08-20 株式会社東芝 半導体集積回路装置およびその動作検証方法
JP3261302B2 (ja) * 1996-03-19 2002-02-25 シャープ株式会社 半導体メモリ装置及びその製造方法
DE19612456C2 (de) * 1996-03-28 2000-09-28 Siemens Ag Halbleiterspeichervorrichtung
US6750527B1 (en) * 1996-05-30 2004-06-15 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having a plurality of wells, test method of testing the semiconductor integrated circuit device, and test device which executes the test method
KR100190049B1 (ko) * 1996-06-25 1999-06-01 윤종용 어레이회로 제어용 내부전압을 이용한 승압전원발생장치
US6064250A (en) 1996-07-29 2000-05-16 Townsend And Townsend And Crew Llp Various embodiments for a low power adaptive charge pump circuit
JP3709246B2 (ja) * 1996-08-27 2005-10-26 株式会社日立製作所 半導体集積回路
US7023729B2 (en) * 1997-01-31 2006-04-04 Renesas Technology Corp. Microcomputer and microprocessor having flash memory operable from single external power supply
JPH10283776A (ja) * 1997-04-04 1998-10-23 Mitsubishi Electric Corp 半導体記憶装置
US6005812A (en) 1998-02-27 1999-12-21 Micron Technology, Inc. Device and method for supplying current to a semiconductor memory to support a boosted voltage within the memory during testing
JP3853513B2 (ja) 1998-04-09 2006-12-06 エルピーダメモリ株式会社 ダイナミック型ｒａｍ
US6373753B1 (en) * 1999-02-13 2002-04-16 Robert J. Proebsting Memory array having selected word lines driven to an internally-generated boosted voltage that is substantially independent of VDD
US6356485B1 (en) 1999-02-13 2002-03-12 Integrated Device Technology, Inc. Merging write cycles by comparing at least a portion of the respective write cycle addresses
US6204723B1 (en) 1999-04-29 2001-03-20 International Business Machines Corporation Bias circuit for series connected decoupling capacitors
US6219293B1 (en) 1999-09-01 2001-04-17 Micron Technology Inc. Method and apparatus for supplying regulated power to memory device components
JP2001110184A (ja) * 1999-10-14 2001-04-20 Hitachi Ltd 半導体装置
JP2001160296A (ja) * 1999-12-01 2001-06-12 Toshiba Corp 電圧レベル変換回路及びこれを用いた半導体記憶装置
AU2319600A (en) * 2000-01-27 2001-08-07 Hitachi Limited Semiconductor device
US6320454B1 (en) 2000-06-01 2001-11-20 Atmel Corporation Low power voltage regulator circuit for use in an integrated circuit device
JP3866594B2 (ja) 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
US6785161B2 (en) * 2002-06-28 2004-08-31 Micron Technology, Inc. High voltage regulator for low voltage integrated circuit processes
JP2004070805A (ja) * 2002-08-08 2004-03-04 Fujitsu Ltd 内部電源電圧が制御される半導体集積回路
CN100423421C (zh) * 2003-05-13 2008-10-01 富士通株式会社 半导体集成电路装置
JP5808937B2 (ja) * 2011-04-20 2015-11-10 ラピスセミコンダクタ株式会社 半導体メモリの内部電源電圧生成回路及び内部電源電圧生成方法
US9324383B2 (en) * 2014-03-20 2016-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Source line voltage regulation scheme for leakage reduction
JP6378003B2 (ja) * 2014-08-27 2018-08-22 ラピスセミコンダクタ株式会社 半導体装置、電池監視システム、及び半導体装置の起動方法
JP2017147005A (ja) * 2016-02-16 2017-08-24 ルネサスエレクトロニクス株式会社 フラッシュメモリ

Family Cites Families (5)

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Publication number Priority date Publication date Assignee Title
KR100209449B1 (ko) * 1990-05-21 1999-07-15 가나이 쓰토무 반도체 집적회로 장치
EP0470498A3 (en) * 1990-07-31 1993-06-09 Texas Instruments Incorporated Improvements in or relating to integrated circuits
US5329168A (en) * 1991-12-27 1994-07-12 Nec Corporation Semiconductor integrated circuit device equipped with substrate biasing system selectively powered from internal and external power sources
KR950014099B1 (ko) * 1992-06-12 1995-11-21 가부시기가이샤 도시바 반도체 기억장치
JP2768172B2 (ja) * 1992-09-30 1998-06-25 日本電気株式会社 半導体メモリ装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6559707B1 (en) 2001-12-06 2003-05-06 Hynix Semiconductor Inc. Bootstrap circuit
DE10164360A1 (de) * 2001-12-06 2003-06-18 Hynix Semiconductor Inc Bootstrap-Schaltung

Also Published As

Publication number Publication date
CN1040377C (zh) 1998-10-21
EP0669619A3 (de) 1995-10-04
JP3155879B2 (ja) 2001-04-16
US5592421A (en) 1997-01-07
CN1113347A (zh) 1995-12-13
DE69516328D1 (de) 2000-05-25
KR100241209B1 (ko) 2000-02-01
EP0669619A2 (de) 1995-08-30
JPH07240094A (ja) 1995-09-12
EP0669619B1 (de) 2000-04-19
KR950025773A (ko) 1995-09-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee